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[/] [sgmii/] [trunk/] [build/] [OpenCore_MAC/] [MAC_rx_ctrl.v.bak] - Blame information for rev 26

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  MAC_rx_ctrl.v                                               ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
////                                                              ////
////  Author(s):                                                  ////
////      - Jon Gao (gaojon@yahoo.com)                            ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2006/01/19 14:07:54  maverickist
// verification is complete.
//
// Revision 1.3  2005/12/16 06:44:17  Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.2  2005/12/13 12:15:37  Administrator
// no message
//
// Revision 1.1.1.1  2005/12/13 01:51:45  Administrator
// no message
//
 
module MAC_rx_ctrl (
Reset   ,
Clk     ,
//RMII interface
MCrs_dv ,       //
MRxD    ,       //
MRxErr  ,       //
//CRC_chk interface
CRC_en    ,
CRC_init  ,
CRC_err  ,
//MAC_rx_add_chk interface
MAC_add_en          ,
MAC_rx_add_chk_err  ,
//broadcast_filter
broadcast_ptr   ,
broadcast_drop  ,
//flow_control signals
pause_quanta        ,
pause_quanta_val    ,
//MAC_rx_FF interface
Fifo_data       ,
Fifo_data_en    ,
Fifo_data_err   ,
Fifo_data_end   ,
Fifo_full       ,
//RMON interface
Rx_pkt_type_rmon        ,
Rx_pkt_length_rmon      ,
Rx_apply_rmon           ,
Rx_pkt_err_type_rmon    ,
//CPU
RX_IFG_SET    ,
RX_MAX_LENGTH,
RX_MIN_LENGTH
);
 
input           Reset   ;
input           Clk     ;
                //RMII interface
input           MCrs_dv ;
input   [7:0]   MRxD    ;
input           MRxErr  ;
                //CRC_chk interface
output          CRC_en  ;
output          CRC_init;
input           CRC_err ;
                //MAC_rx_add_chk interface
output          MAC_add_en          ;
input           MAC_rx_add_chk_err  ;
                //broadcast_filter
output          broadcast_ptr           ;
input           broadcast_drop          ;
                //flow_control signals
output  [15:0]  pause_quanta        ;
output          pause_quanta_val    ;
                //MAC_rx_FF interface
output  [7:0]   Fifo_data       ;
output          Fifo_data_en    ;
output          Fifo_data_err   ;
output          Fifo_data_end   ;
input           Fifo_full;
                //RMON interface
output  [15:0]  Rx_pkt_length_rmon      ;
output          Rx_apply_rmon           ;
output  [2:0]   Rx_pkt_err_type_rmon    ;
output  [2:0]   Rx_pkt_type_rmon        ;
                //CPU
input   [5:0]   RX_IFG_SET    ;
input   [15:0]  RX_MAX_LENGTH   ;// 1518
input   [6:0]   RX_MIN_LENGTH   ;// 64
 
//******************************************************************************
//internal signals
//******************************************************************************
parameter       State_idle          =4'd00;
parameter       State_preamble      =4'd01;
parameter       State_SFD           =4'd02;
parameter       State_data          =4'd03;
parameter       State_checkCRC      =4'd04;
parameter       State_OkEnd         =4'd07;
parameter       State_drop          =4'd08;
parameter       State_ErrEnd        =4'd09;
parameter       State_CRCErrEnd     =4'd10;
parameter       State_FFFullDrop    =4'd11;
parameter       State_FFFullErrEnd  =4'd12;
parameter       State_IFG           =4'd13;
 
parameter       Pause_idle          =4'd0;
parameter       Pause_pre_syn       =4'd1;
parameter       Pause_quanta_hi     =4'd2;
parameter       Pause_quanta_lo     =4'd3;
parameter       Pause_syn           =4'd4;
 
reg [3:0]       Current_state /* synthesis syn_keep=1 */;
reg [3:0]       Next_state;
reg [3:0]       Pause_current /* synthesis syn_keep=1 */;
reg [3:0]       Pause_next;
reg [5:0]       IFG_counter;
reg             Crs_dv  ;
reg [7:0]       RxD ;
reg [7:0]       RxD_dl1 ;
reg             RxErr   ;
reg [15:0]      Frame_length_counter;
reg             Too_long;
reg             Too_short;
reg             Fifo_data_en;
reg             Fifo_data_end;
reg             Fifo_data_err;
reg             CRC_en;
reg             CRC_init;
reg             Rx_apply_rmon;
reg             Rx_apply_rmon_tmp;
reg             Rx_apply_rmon_tmp_pl1;
reg [2:0]       Rx_pkt_err_type_rmon;
reg             MAC_add_en;
reg [2:0]       Rx_pkt_type_rmon;
reg [7:0]       pause_quanta_h      ;
reg [15:0]      pause_quanta        ;
reg             pause_quanta_val    ;
reg             pause_quanta_val_tmp;
reg             pause_frame_ptr     ;
reg             broadcast_ptr           ;
//******************************************************************************
//delay signals
//******************************************************************************
 
always @ (posedge Reset or posedge Clk)
    if (Reset)
        begin
            Crs_dv      <=0;
            RxD         <=0;
            RxErr       <=0;
        end
    else
        begin
            Crs_dv      <=MCrs_dv   ;
            RxD         <=MRxD      ;
            RxErr       <=MRxErr    ;
        end
 
always @ (posedge Reset or posedge Clk)
    if (Reset)
        RxD_dl1     <=0;
    else
        RxD_dl1     <=RxD;
 
//******************************************************************************
//State_machine
//******************************************************************************
 
always @ (posedge Reset or posedge Clk)
    if (Reset)
        Current_state   <=State_idle;
    else
        Current_state   <=Next_state;
 
always @ (*)
        case (Current_state)
            State_idle:
                    if (Crs_dv&&RxD==8'h55)
                        Next_state  =State_preamble;
                    else
                        Next_state  =Current_state;
            State_preamble:
                    if (!Crs_dv)
                        Next_state  =State_ErrEnd;
                    else if (RxErr)
                        Next_state  =State_drop;
                    else if (RxD==8'hd5)
                        Next_state  =State_SFD;
                    else if (RxD==8'h55)
                        Next_state  =Current_state;
                    else
                        Next_state  =State_drop;
            State_SFD:
                    if (!Crs_dv)
                        Next_state  =State_ErrEnd;
                    else if (RxErr)
                        Next_state  =State_drop;
                    else
                        Next_state  =State_data;
            State_data:
                    if (!Crs_dv&&!Too_short&&!Too_long)
                        Next_state  =State_checkCRC;
                    else if (!Crs_dv&&(Too_short||Too_long))
                        Next_state  =State_ErrEnd;
                    else if (Fifo_full)
                        Next_state  =State_FFFullErrEnd;
                    else if (RxErr||MAC_rx_add_chk_err||Too_long||broadcast_drop)
                        Next_state  =State_drop;
                    else
                        Next_state  =State_data;
            State_checkCRC:
                     if (CRC_err)
                        Next_state  =State_CRCErrEnd;
                     else
                        Next_state  =State_OkEnd;
            State_drop:
                    if (!Crs_dv)
                        Next_state  =State_ErrEnd;
                    else
                        Next_state  =Current_state;
            State_OkEnd:
                        Next_state  =State_IFG;
            State_ErrEnd:
                        Next_state  =State_IFG;
 
            State_CRCErrEnd:
                        Next_state  =State_IFG;
            State_FFFullDrop:
                    if (!Crs_dv)
                        Next_state  =State_IFG;
                    else
                        Next_state  =Current_state;
            State_FFFullErrEnd:
                        Next_state  =State_FFFullDrop;
            State_IFG:
                    if (IFG_counter==RX_IFG_SET-4)   //remove some additional time
                        Next_state  =State_idle;
                    else
                        Next_state  =Current_state;
 
            default:
                        Next_state  =State_idle;
        endcase
 
 
always @ (posedge Reset or posedge Clk)
    if (Reset)
        IFG_counter     <=0;
    else if (Current_state!=State_IFG)
        IFG_counter     <=0;
    else
        IFG_counter     <=IFG_counter + 1;
//******************************************************************************
//gen fifo interface signals
//******************************************************************************
 
assign  Fifo_data   =RxD_dl1;
 
always @(Current_state)
    if  (Current_state==State_data)
        Fifo_data_en        =1;
    else
        Fifo_data_en        =0;
 
always @(Current_state)
    if  (Current_state==State_ErrEnd||Current_state==State_OkEnd
         ||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd)
        Fifo_data_end       =1;
    else
        Fifo_data_end       =0;
 
always @(Current_state)
    if  (Current_state==State_ErrEnd||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd)
        Fifo_data_err       =1;
    else
        Fifo_data_err       =0;
 
//******************************************************************************
//CRC_chk interface
//******************************************************************************
 
always @(Current_state)
    if (Current_state==State_data)
        CRC_en  =1;
    else
        CRC_en  =0;
 
always @(Current_state)
    if (Current_state==State_SFD)
        CRC_init    =1;
    else
        CRC_init    =0;
 
//******************************************************************************
//gen rmon signals
//******************************************************************************
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Frame_length_counter        <=0;
    else if (Current_state==State_SFD)
        Frame_length_counter        <=1;
    else if (Current_state==State_data)
        Frame_length_counter        <=Frame_length_counter+ 1'b1;
 
always @ (Frame_length_counter or RX_MIN_LENGTH)
    if (Frame_length_counter
        Too_short   =1;
    else
        Too_short   =0;
 
always @ (*)
    if (Frame_length_counter>RX_MAX_LENGTH)
        Too_long    =1;
    else
        Too_long    =0;
 
assign Rx_pkt_length_rmon=Frame_length_counter-1'b1;
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Rx_apply_rmon_tmp   <=0;
    else if (Current_state==State_OkEnd||Current_state==State_ErrEnd
        ||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd)
        Rx_apply_rmon_tmp   <=1;
    else
        Rx_apply_rmon_tmp   <=0;
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Rx_apply_rmon_tmp_pl1   <=0;
    else
        Rx_apply_rmon_tmp_pl1   <=Rx_apply_rmon_tmp;
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Rx_apply_rmon   <=0;
    else if (Current_state==State_OkEnd||Current_state==State_ErrEnd
        ||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd)
        Rx_apply_rmon   <=1;
    else if (Rx_apply_rmon_tmp_pl1)
        Rx_apply_rmon   <=0;
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Rx_pkt_err_type_rmon    <=0;
    else if (Current_state==State_CRCErrEnd)
        Rx_pkt_err_type_rmon    <=3'b001    ;//
    else if (Current_state==State_FFFullErrEnd)
        Rx_pkt_err_type_rmon    <=3'b010    ;//
    else if (Current_state==State_ErrEnd)
        Rx_pkt_err_type_rmon    <=3'b011    ;//
    else if(Current_state==State_OkEnd)
        Rx_pkt_err_type_rmon    <=3'b100    ;
 
 
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Rx_pkt_type_rmon        <=0;
    else if (Current_state==State_OkEnd&&pause_frame_ptr)
        Rx_pkt_type_rmon        <=3'b100    ;//
    else if(Current_state==State_SFD&&Next_state==State_data)
        Rx_pkt_type_rmon        <={1'b0,MRxD[7:6]};
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        broadcast_ptr   <=0;
    else if(Current_state==State_IFG)
        broadcast_ptr   <=0;
    else if(Current_state==State_SFD&&Next_state==State_data&&MRxD[7:6]==2'b11)
        broadcast_ptr   <=1;
 
 
 
//******************************************************************************
//MAC add checker signals
//******************************************************************************
always @ (Frame_length_counter or Fifo_data_en)
    if(Frame_length_counter>=1&&Frame_length_counter<=6)
        MAC_add_en  <=Fifo_data_en;
    else
        MAC_add_en  <=0;
 
//******************************************************************************
//flow control signals
//******************************************************************************
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Pause_current   <=Pause_idle;
    else
        Pause_current   <=Pause_next;
 
always @ (*)
    case (Pause_current)
        Pause_idle  :
            if(Current_state==State_SFD)
                Pause_next  =Pause_pre_syn;
            else
                Pause_next  =Pause_current;
        Pause_pre_syn:
            case (Frame_length_counter)
                16'd1:  if (RxD_dl1==8'h01)
                            Pause_next  =Pause_current;
                        else
                            Pause_next  =Pause_idle;
                16'd2:  if (RxD_dl1==8'h80)
                            Pause_next  =Pause_current;
                        else
                            Pause_next  =Pause_idle;
                16'd3:  if (RxD_dl1==8'hc2)
                            Pause_next  =Pause_current;
                        else
                            Pause_next  =Pause_idle;
                16'd4:  if (RxD_dl1==8'h00)
                            Pause_next  =Pause_current;
                        else
                            Pause_next  =Pause_idle;
                16'd5:  if (RxD_dl1==8'h00)
                            Pause_next  =Pause_current;
                        else
                            Pause_next  =Pause_idle;
                16'd6:  if (RxD_dl1==8'h01)
                            Pause_next  =Pause_current;
                        else
                            Pause_next  =Pause_idle;
                16'd13: if (RxD_dl1==8'h88)
                            Pause_next  =Pause_current;
                        else
                            Pause_next  =Pause_idle;
                16'd14: if (RxD_dl1==8'h08)
                            Pause_next  =Pause_current;
                        else
                            Pause_next  =Pause_idle;
                16'd15: if (RxD_dl1==8'h00)
                            Pause_next  =Pause_current;
                        else
                            Pause_next  =Pause_idle;
                16'd16: if (RxD_dl1==8'h01)
                            Pause_next  =Pause_quanta_hi;
                        else
                            Pause_next  =Pause_idle;
                default:    Pause_next  =Pause_current;
            endcase
        Pause_quanta_hi :
            Pause_next  =Pause_quanta_lo;
        Pause_quanta_lo :
            Pause_next  =Pause_syn;
        Pause_syn       :
            if (Current_state==State_IFG)
                Pause_next  =Pause_idle;
            else
                Pause_next  =Pause_current;
        default
            Pause_next  =Pause_idle;
    endcase
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        pause_quanta_h      <=0;
    else if(Pause_current==Pause_quanta_hi)
        pause_quanta_h      <=RxD_dl1;
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        pause_quanta        <=0;
    else if(Pause_current==Pause_quanta_lo)
        pause_quanta        <={pause_quanta_h,RxD_dl1};
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        pause_quanta_val_tmp    <=0;
    else if(Current_state==State_OkEnd&&Pause_current==Pause_syn)
        pause_quanta_val_tmp    <=1;
    else
        pause_quanta_val_tmp    <=0;
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        pause_quanta_val    <=0;
    else if(Current_state==State_OkEnd&&Pause_current==Pause_syn||pause_quanta_val_tmp)
        pause_quanta_val    <=1;
    else
        pause_quanta_val    <=0;
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        pause_frame_ptr     <=0;
    else if(Pause_current==Pause_syn)
        pause_frame_ptr     <=1;
    else
        pause_frame_ptr     <=0;
 
endmodule
 
 

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[/] [sgmii/] [trunk/] [build/] [OpenCore_MAC/] [MAC_rx_ctrl.v.bak] - Blame information for rev 26

Line No.	Rev	Author	Line
1	26	jefflieu	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// MAC_rx_ctrl.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Jon Gao (gaojon@yahoo.com) ////`
10			`//// ////`
11			`//// ////`
12			`//////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Authors ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer. ////`
20			`//// ////`
21			`//// This source file is free software; you can redistribute it ////`
22			`//// and/or modify it under the terms of the GNU Lesser General ////`
23			`//// Public License as published by the Free Software Foundation; ////`
24			`//// either version 2.1 of the License, or (at your option) any ////`
25			`//// later version. ////`
26			`//// ////`
27			`//// This source is distributed in the hope that it will be ////`
28			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
29			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
30			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
31			`//// details. ////`
32			`//// ////`
33			`//// You should have received a copy of the GNU Lesser General ////`
34			`//// Public License along with this source; if not, download it ////`
35			`//// from http://www.opencores.org/lgpl.shtml ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//`
39			`// CVS Revision History`
40			`//`
41			`// $Log: not supported by cvs2svn $`
42			`// Revision 1.3 2006/01/19 14:07:54 maverickist`
43			`// verification is complete.`
44			`//`
45			`// Revision 1.3 2005/12/16 06:44:17 Administrator`
46			`// replaced tab with space.`
47			`// passed 9.6k length frame test.`
48			`//`
49			`// Revision 1.2 2005/12/13 12:15:37 Administrator`
50			`// no message`
51			`//`
52			`// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator`
53			`// no message`
54			`//`
55
56			`module MAC_rx_ctrl (`
57			`Reset ,`
58			`Clk ,`
59			`//RMII interface`
60			`MCrs_dv , //`
61			`MRxD , //`
62			`MRxErr , //`
63			`//CRC_chk interface`
64			`CRC_en ,`
65			`CRC_init ,`
66			`CRC_err ,`
67			`//MAC_rx_add_chk interface`
68			`MAC_add_en ,`
69			`MAC_rx_add_chk_err ,`
70			`//broadcast_filter`
71			`broadcast_ptr ,`
72			`broadcast_drop ,`
73			`//flow_control signals`
74			`pause_quanta ,`
75			`pause_quanta_val ,`
76			`//MAC_rx_FF interface`
77			`Fifo_data ,`
78			`Fifo_data_en ,`
79			`Fifo_data_err ,`
80			`Fifo_data_end ,`
81			`Fifo_full ,`
82			`//RMON interface`
83			`Rx_pkt_type_rmon ,`
84			`Rx_pkt_length_rmon ,`
85			`Rx_apply_rmon ,`
86			`Rx_pkt_err_type_rmon ,`
87			`//CPU`
88			`RX_IFG_SET ,`
89			`RX_MAX_LENGTH,`
90			`RX_MIN_LENGTH`
91			`);`
92
93			`input Reset ;`
94			`input Clk ;`
95			`//RMII interface`
96			`input MCrs_dv ;`
97			`input [7:0] MRxD ;`
98			`input MRxErr ;`
99			`//CRC_chk interface`
100			`output CRC_en ;`
101			`output CRC_init;`
102			`input CRC_err ;`
103			`//MAC_rx_add_chk interface`
104			`output MAC_add_en ;`
105			`input MAC_rx_add_chk_err ;`
106			`//broadcast_filter`
107			`output broadcast_ptr ;`
108			`input broadcast_drop ;`
109			`//flow_control signals`
110			`output [15:0] pause_quanta ;`
111			`output pause_quanta_val ;`
112			`//MAC_rx_FF interface`
113			`output [7:0] Fifo_data ;`
114			`output Fifo_data_en ;`
115			`output Fifo_data_err ;`
116			`output Fifo_data_end ;`
117			`input Fifo_full;`
118			`//RMON interface`
119			`output [15:0] Rx_pkt_length_rmon ;`
120			`output Rx_apply_rmon ;`
121			`output [2:0] Rx_pkt_err_type_rmon ;`
122			`output [2:0] Rx_pkt_type_rmon ;`
123			`//CPU`
124			`input [5:0] RX_IFG_SET ;`
125			`input [15:0] RX_MAX_LENGTH ;// 1518`
126			`input [6:0] RX_MIN_LENGTH ;// 64`
127
128			`//******************************************************************************`
129			`//internal signals`
130			`//******************************************************************************`
131			`parameter State_idle =4'd00;`
132			`parameter State_preamble =4'd01;`
133			`parameter State_SFD =4'd02;`
134			`parameter State_data =4'd03;`
135			`parameter State_checkCRC =4'd04;`
136			`parameter State_OkEnd =4'd07;`
137			`parameter State_drop =4'd08;`
138			`parameter State_ErrEnd =4'd09;`
139			`parameter State_CRCErrEnd =4'd10;`
140			`parameter State_FFFullDrop =4'd11;`
141			`parameter State_FFFullErrEnd =4'd12;`
142			`parameter State_IFG =4'd13;`
143
144			`parameter Pause_idle =4'd0;`
145			`parameter Pause_pre_syn =4'd1;`
146			`parameter Pause_quanta_hi =4'd2;`
147			`parameter Pause_quanta_lo =4'd3;`
148			`parameter Pause_syn =4'd4;`
149
150			`reg [3:0] Current_state /* synthesis syn_keep=1 */;`
151			`reg [3:0] Next_state;`
152			`reg [3:0] Pause_current /* synthesis syn_keep=1 */;`
153			`reg [3:0] Pause_next;`
154			`reg [5:0] IFG_counter;`
155			`reg Crs_dv ;`
156			`reg [7:0] RxD ;`
157			`reg [7:0] RxD_dl1 ;`
158			`reg RxErr ;`
159			`reg [15:0] Frame_length_counter;`
160			`reg Too_long;`
161			`reg Too_short;`
162			`reg Fifo_data_en;`
163			`reg Fifo_data_end;`
164			`reg Fifo_data_err;`
165			`reg CRC_en;`
166			`reg CRC_init;`
167			`reg Rx_apply_rmon;`
168			`reg Rx_apply_rmon_tmp;`
169			`reg Rx_apply_rmon_tmp_pl1;`
170			`reg [2:0] Rx_pkt_err_type_rmon;`
171			`reg MAC_add_en;`
172			`reg [2:0] Rx_pkt_type_rmon;`
173			`reg [7:0] pause_quanta_h ;`
174			`reg [15:0] pause_quanta ;`
175			`reg pause_quanta_val ;`
176			`reg pause_quanta_val_tmp;`
177			`reg pause_frame_ptr ;`
178			`reg broadcast_ptr ;`
179			`//******************************************************************************`
180			`//delay signals`
181			`//******************************************************************************`
182
183			`always @ (posedge Reset or posedge Clk)`
184			`if (Reset)`
185			`begin`
186			`Crs_dv <=0;`
187			`RxD <=0;`
188			`RxErr <=0;`
189			`end`
190			`else`
191			`begin`
192			`Crs_dv <=MCrs_dv ;`
193			`RxD <=MRxD ;`
194			`RxErr <=MRxErr ;`
195			`end`
196
197			`always @ (posedge Reset or posedge Clk)`
198			`if (Reset)`
199			`RxD_dl1 <=0;`
200			`else`
201			`RxD_dl1 <=RxD;`
202
203			`//******************************************************************************`
204			`//State_machine`
205			`//******************************************************************************`
206
207			`always @ (posedge Reset or posedge Clk)`
208			`if (Reset)`
209			`Current_state <=State_idle;`
210			`else`
211			`Current_state <=Next_state;`
212
213			`always @ (*)`
214			`case (Current_state)`
215			`State_idle:`
216			`if (Crs_dv&&RxD==8'h55)`
217			`Next_state =State_preamble;`
218			`else`
219			`Next_state =Current_state;`
220			`State_preamble:`
221			`if (!Crs_dv)`
222			`Next_state =State_ErrEnd;`
223			`else if (RxErr)`
224			`Next_state =State_drop;`
225			`else if (RxD==8'hd5)`
226			`Next_state =State_SFD;`
227			`else if (RxD==8'h55)`
228			`Next_state =Current_state;`
229			`else`
230			`Next_state =State_drop;`
231			`State_SFD:`
232			`if (!Crs_dv)`
233			`Next_state =State_ErrEnd;`
234			`else if (RxErr)`
235			`Next_state =State_drop;`
236			`else`
237			`Next_state =State_data;`
238			`State_data:`
239			`if (!Crs_dv&&!Too_short&&!Too_long)`
240			`Next_state =State_checkCRC;`
241			`else if (!Crs_dv&&(Too_short\|\|Too_long))`
242			`Next_state =State_ErrEnd;`
243			`else if (Fifo_full)`
244			`Next_state =State_FFFullErrEnd;`
245			`else if (RxErr\|\|MAC_rx_add_chk_err\|\|Too_long\|\|broadcast_drop)`
246			`Next_state =State_drop;`
247			`else`
248			`Next_state =State_data;`
249			`State_checkCRC:`
250			`if (CRC_err)`
251			`Next_state =State_CRCErrEnd;`
252			`else`
253			`Next_state =State_OkEnd;`
254			`State_drop:`
255			`if (!Crs_dv)`
256			`Next_state =State_ErrEnd;`
257			`else`
258			`Next_state =Current_state;`
259			`State_OkEnd:`
260			`Next_state =State_IFG;`
261			`State_ErrEnd:`
262			`Next_state =State_IFG;`
263
264			`State_CRCErrEnd:`
265			`Next_state =State_IFG;`
266			`State_FFFullDrop:`
267			`if (!Crs_dv)`
268			`Next_state =State_IFG;`
269			`else`
270			`Next_state =Current_state;`
271			`State_FFFullErrEnd:`
272			`Next_state =State_FFFullDrop;`
273			`State_IFG:`
274			`if (IFG_counter==RX_IFG_SET-4) //remove some additional time`
275			`Next_state =State_idle;`
276			`else`
277			`Next_state =Current_state;`
278
279			`default:`
280			`Next_state =State_idle;`
281			`endcase`
282
283
284			`always @ (posedge Reset or posedge Clk)`
285			`if (Reset)`
286			`IFG_counter <=0;`
287			`else if (Current_state!=State_IFG)`
288			`IFG_counter <=0;`
289			`else`
290			`IFG_counter <=IFG_counter + 1;`
291			`//******************************************************************************`
292			`//gen fifo interface signals`
293			`//******************************************************************************`
294
295			`assign Fifo_data =RxD_dl1;`
296
297			`always @(Current_state)`
298			`if (Current_state==State_data)`
299			`Fifo_data_en =1;`
300			`else`
301			`Fifo_data_en =0;`
302
303			`always @(Current_state)`
304			`if (Current_state==State_ErrEnd\|\|Current_state==State_OkEnd`
305			`\|\|Current_state==State_CRCErrEnd\|\|Current_state==State_FFFullErrEnd)`
306			`Fifo_data_end =1;`
307			`else`
308			`Fifo_data_end =0;`
309
310			`always @(Current_state)`
311			`if (Current_state==State_ErrEnd\|\|Current_state==State_CRCErrEnd\|\|Current_state==State_FFFullErrEnd)`
312			`Fifo_data_err =1;`
313			`else`
314			`Fifo_data_err =0;`
315
316			`//******************************************************************************`
317			`//CRC_chk interface`
318			`//******************************************************************************`
319
320			`always @(Current_state)`
321			`if (Current_state==State_data)`
322			`CRC_en =1;`
323			`else`
324			`CRC_en =0;`
325
326			`always @(Current_state)`
327			`if (Current_state==State_SFD)`
328			`CRC_init =1;`
329			`else`
330			`CRC_init =0;`
331
332			`//******************************************************************************`
333			`//gen rmon signals`
334			`//******************************************************************************`
335			`always @ (posedge Clk or posedge Reset)`
336			`if (Reset)`
337			`Frame_length_counter <=0;`
338			`else if (Current_state==State_SFD)`
339			`Frame_length_counter <=1;`
340			`else if (Current_state==State_data)`
341			`Frame_length_counter <=Frame_length_counter+ 1'b1;`
342
343			`always @ (Frame_length_counter or RX_MIN_LENGTH)`
344			`if (Frame_length_counter`
345			`Too_short =1;`
346			`else`
347			`Too_short =0;`
348
349			`always @ (*)`
350			`if (Frame_length_counter>RX_MAX_LENGTH)`
351			`Too_long =1;`
352			`else`
353			`Too_long =0;`
354
355			`assign Rx_pkt_length_rmon=Frame_length_counter-1'b1;`
356
357			`always @ (posedge Clk or posedge Reset)`
358			`if (Reset)`
359			`Rx_apply_rmon_tmp <=0;`
360			`else if (Current_state==State_OkEnd\|\|Current_state==State_ErrEnd`
361			`\|\|Current_state==State_CRCErrEnd\|\|Current_state==State_FFFullErrEnd)`
362			`Rx_apply_rmon_tmp <=1;`
363			`else`
364			`Rx_apply_rmon_tmp <=0;`
365
366			`always @ (posedge Clk or posedge Reset)`
367			`if (Reset)`
368			`Rx_apply_rmon_tmp_pl1 <=0;`
369			`else`
370			`Rx_apply_rmon_tmp_pl1 <=Rx_apply_rmon_tmp;`
371
372			`always @ (posedge Clk or posedge Reset)`
373			`if (Reset)`
374			`Rx_apply_rmon <=0;`
375			`else if (Current_state==State_OkEnd\|\|Current_state==State_ErrEnd`
376			`\|\|Current_state==State_CRCErrEnd\|\|Current_state==State_FFFullErrEnd)`
377			`Rx_apply_rmon <=1;`
378			`else if (Rx_apply_rmon_tmp_pl1)`
379			`Rx_apply_rmon <=0;`
380
381			`always @ (posedge Clk or posedge Reset)`
382			`if (Reset)`
383			`Rx_pkt_err_type_rmon <=0;`
384			`else if (Current_state==State_CRCErrEnd)`
385			`Rx_pkt_err_type_rmon <=3'b001 ;//`
386			`else if (Current_state==State_FFFullErrEnd)`
387			`Rx_pkt_err_type_rmon <=3'b010 ;//`
388			`else if (Current_state==State_ErrEnd)`
389			`Rx_pkt_err_type_rmon <=3'b011 ;//`
390			`else if(Current_state==State_OkEnd)`
391			`Rx_pkt_err_type_rmon <=3'b100 ;`
392
393
394
395			`always @ (posedge Clk or posedge Reset)`
396			`if (Reset)`
397			`Rx_pkt_type_rmon <=0;`
398			`else if (Current_state==State_OkEnd&&pause_frame_ptr)`
399			`Rx_pkt_type_rmon <=3'b100 ;//`
400			`else if(Current_state==State_SFD&&Next_state==State_data)`
401			`Rx_pkt_type_rmon <={1'b0,MRxD[7:6]};`
402
403			`always @ (posedge Clk or posedge Reset)`
404			`if (Reset)`
405			`broadcast_ptr <=0;`
406			`else if(Current_state==State_IFG)`
407			`broadcast_ptr <=0;`
408			`else if(Current_state==State_SFD&&Next_state==State_data&&MRxD[7:6]==2'b11)`
409			`broadcast_ptr <=1;`
410
411
412
413			`//******************************************************************************`
414			`//MAC add checker signals`
415			`//******************************************************************************`
416			`always @ (Frame_length_counter or Fifo_data_en)`
417			`if(Frame_length_counter>=1&&Frame_length_counter<=6)`
418			`MAC_add_en <=Fifo_data_en;`
419			`else`
420			`MAC_add_en <=0;`
421
422			`//******************************************************************************`
423			`//flow control signals`
424			`//******************************************************************************`
425			`always @ (posedge Clk or posedge Reset)`
426			`if (Reset)`
427			`Pause_current <=Pause_idle;`
428			`else`
429			`Pause_current <=Pause_next;`
430
431			`always @ (*)`
432			`case (Pause_current)`
433			`Pause_idle :`
434			`if(Current_state==State_SFD)`
435			`Pause_next =Pause_pre_syn;`
436			`else`
437			`Pause_next =Pause_current;`
438			`Pause_pre_syn:`
439			`case (Frame_length_counter)`
440			`16'd1: if (RxD_dl1==8'h01)`
441			`Pause_next =Pause_current;`
442			`else`
443			`Pause_next =Pause_idle;`
444			`16'd2: if (RxD_dl1==8'h80)`
445			`Pause_next =Pause_current;`
446			`else`
447			`Pause_next =Pause_idle;`
448			`16'd3: if (RxD_dl1==8'hc2)`
449			`Pause_next =Pause_current;`
450			`else`
451			`Pause_next =Pause_idle;`
452			`16'd4: if (RxD_dl1==8'h00)`
453			`Pause_next =Pause_current;`
454			`else`
455			`Pause_next =Pause_idle;`
456			`16'd5: if (RxD_dl1==8'h00)`
457			`Pause_next =Pause_current;`
458			`else`
459			`Pause_next =Pause_idle;`
460			`16'd6: if (RxD_dl1==8'h01)`
461			`Pause_next =Pause_current;`
462			`else`
463			`Pause_next =Pause_idle;`
464			`16'd13: if (RxD_dl1==8'h88)`
465			`Pause_next =Pause_current;`
466			`else`
467			`Pause_next =Pause_idle;`
468			`16'd14: if (RxD_dl1==8'h08)`
469			`Pause_next =Pause_current;`
470			`else`
471			`Pause_next =Pause_idle;`
472			`16'd15: if (RxD_dl1==8'h00)`
473			`Pause_next =Pause_current;`
474			`else`
475			`Pause_next =Pause_idle;`
476			`16'd16: if (RxD_dl1==8'h01)`
477			`Pause_next =Pause_quanta_hi;`
478			`else`
479			`Pause_next =Pause_idle;`
480			`default: Pause_next =Pause_current;`
481			`endcase`
482			`Pause_quanta_hi :`
483			`Pause_next =Pause_quanta_lo;`
484			`Pause_quanta_lo :`
485			`Pause_next =Pause_syn;`
486			`Pause_syn :`
487			`if (Current_state==State_IFG)`
488			`Pause_next =Pause_idle;`
489			`else`
490			`Pause_next =Pause_current;`
491			`default`
492			`Pause_next =Pause_idle;`
493			`endcase`
494
495			`always @ (posedge Clk or posedge Reset)`
496			`if (Reset)`
497			`pause_quanta_h <=0;`
498			`else if(Pause_current==Pause_quanta_hi)`
499			`pause_quanta_h <=RxD_dl1;`
500
501			`always @ (posedge Clk or posedge Reset)`
502			`if (Reset)`
503			`pause_quanta <=0;`
504			`else if(Pause_current==Pause_quanta_lo)`
505			`pause_quanta <={pause_quanta_h,RxD_dl1};`
506
507			`always @ (posedge Clk or posedge Reset)`
508			`if (Reset)`
509			`pause_quanta_val_tmp <=0;`
510			`else if(Current_state==State_OkEnd&&Pause_current==Pause_syn)`
511			`pause_quanta_val_tmp <=1;`
512			`else`
513			`pause_quanta_val_tmp <=0;`
514
515			`always @ (posedge Clk or posedge Reset)`
516			`if (Reset)`
517			`pause_quanta_val <=0;`
518			`else if(Current_state==State_OkEnd&&Pause_current==Pause_syn\|\|pause_quanta_val_tmp)`
519			`pause_quanta_val <=1;`
520			`else`
521			`pause_quanta_val <=0;`
522
523			`always @ (posedge Clk or posedge Reset)`
524			`if (Reset)`
525			`pause_frame_ptr <=0;`
526			`else if(Pause_current==Pause_syn)`
527			`pause_frame_ptr <=1;`
528			`else`
529			`pause_frame_ptr <=0;`
530
531			`endmodule`
532
533