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jefflieu |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// MAC_top.v ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
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//// ////
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//// Author(s): ////
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//// - Jon Gao (gaojon@yahoo.com) ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2006/01/19 14:07:52 maverickist
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// verification is complete.
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//
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// Revision 1.2 2005/12/16 06:44:13 Administrator
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// replaced tab with space.
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// passed 9.6k length frame test.
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//
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// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
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// no message
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//
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// Due to CycloneIV starter board uses SGMII interface
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// It's possible to remove the Phy_int module, and use PCS/PMA of Cyclone GxB
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// Added Clk_MACTx and remove clock module as not necessary anymore
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module MAC_top(
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//system signals
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input Reset ,
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input Clk_user ,
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input Clk_reg ,
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output [2:0] Speed ,
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//user interface
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output Rx_mac_ra ,
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input Rx_mac_rd ,
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output [31:0] Rx_mac_data ,
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output [1:0] Rx_mac_BE ,
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output Rx_mac_pa ,
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output Rx_mac_sop ,
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output Rx_mac_eop ,
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//user interface
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output Tx_mac_wa ,
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input Tx_mac_wr ,
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input [31:0] Tx_mac_data ,
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input [1:0] Tx_mac_BE ,//big endian
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input Tx_mac_sop ,
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input Tx_mac_eop ,
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//pkg_lgth fifo
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input Pkg_lgth_fifo_rd ,
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output Pkg_lgth_fifo_ra ,
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output [15:0] Pkg_lgth_fifo_data ,
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//Phy interface
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//Phy interface
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output Gtx_clk_d ,//shifted clock
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output Gtx_clk ,//used only in GMII mode
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input GMII_Tx_clk ,
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input GMII_Rx_clk ,
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input Rx_clk ,
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input Tx_clk ,//used only in MII mode
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output Tx_er ,
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output Tx_en ,
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output [7:0] Txd ,
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input Rx_er ,
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input Rx_dv ,
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input [7:0] Rxd ,
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input Crs ,
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input Col ,
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//host interface
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input CSB ,
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input WRB ,
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input [15:0] CD_in ,
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output [15:0] CD_out ,
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input [7:0] CA ,
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output [23:0] Monitoring ,
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//mdx
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output Mdo, // MII Management Data Output
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output MdoEn, // MII Management Data Output Enable
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input Mdi,
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output Mdc // MII Management Data Clock
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);
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//******************************************************************************
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//internal signals
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//******************************************************************************
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//RMON interface
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wire [15:0] Rx_pkt_length_rmon ;
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wire Rx_apply_rmon ;
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wire [2:0] Rx_pkt_err_type_rmon ;
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wire [2:0] Rx_pkt_type_rmon ;
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wire [2:0] Tx_pkt_type_rmon ;
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wire [15:0] Tx_pkt_length_rmon ;
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wire Tx_apply_rmon ;
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wire [2:0] Tx_pkt_err_type_rmon ;
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//PHY interface
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wire MCrs_dv ;
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wire [7:0] MRxD ;
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wire MRxErr ;
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//flow_control signals
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wire [15:0] pause_quanta ;
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wire pause_quanta_val ;
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//PHY interface
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wire [7:0] MTxD ;
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wire MTxEn ;
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wire MCRS ;
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//interface clk signals
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wire MAC_tx_clk ;
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wire MAC_rx_clk ;
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wire MAC_tx_clk_div ;
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wire MAC_rx_clk_div ;
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//reg signals
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wire [4:0] Tx_Hwmark ;
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wire [4:0] Tx_Lwmark ;
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wire pause_frame_send_en ;
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wire [15:0] pause_quanta_set ;
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wire MAC_tx_add_en ;
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wire FullDuplex ;
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wire [3:0] MaxRetry ;
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wire [5:0] IFGset ;
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wire [7:0] MAC_tx_add_prom_data ;
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wire [2:0] MAC_tx_add_prom_add ;
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wire MAC_tx_add_prom_wr ;
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wire tx_pause_en ;
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wire xoff_cpu ;
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wire xon_cpu ;
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//Rx host interface
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wire MAC_rx_add_chk_en ;
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wire [7:0] MAC_rx_add_prom_data ;
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wire [2:0] MAC_rx_add_prom_add ;
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wire MAC_rx_add_prom_wr ;
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wire broadcast_filter_en ;
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wire [15:0] broadcast_MAX ;
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wire RX_APPEND_CRC ;
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wire [4:0] Rx_Hwmark ;
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wire [4:0] Rx_Lwmark ;
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wire CRC_chk_en ;
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wire [5:0] RX_IFG_SET ;
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wire [15:0] RX_MAX_LENGTH ;
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wire [6:0] RX_MIN_LENGTH ;
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//RMON host interface
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wire [5:0] CPU_rd_addr ;
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wire CPU_rd_apply ;
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wire CPU_rd_grant ;
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wire [31:0] CPU_rd_dout ;
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//Phy int host interface
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wire Line_loop_en ;
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//MII to CPU
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wire [7:0] Divider ;
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wire [15:0] CtrlData ;
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wire [4:0] Rgad ;
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wire [4:0] Fiad ;
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wire NoPre ;
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wire WCtrlData ;
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wire RStat ;
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wire ScanStat ;
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wire Busy ;
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wire LinkFail ;
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wire Nvalid ;
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wire [15:0] Prsd ;
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wire WCtrlDataStart ;
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wire RStatStart ;
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wire UpdateMIIRX_DATAReg ;
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wire [15:0] broadcast_bucket_depth ;
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wire [15:0] broadcast_bucket_interval ;
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wire Pkg_lgth_fifo_empty;
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reg rx_pkg_lgth_fifo_wr_tmp;
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reg rx_pkg_lgth_fifo_wr_tmp_pl1;
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reg rx_pkg_lgth_fifo_wr;
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//******************************************************************************
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//internal signals
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//******************************************************************************
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MAC_rx U_MAC_rx(
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.Monitoring (Monitoring),
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.Reset (Reset ),
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.Clk_user (Clk_user ),
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.Clk (MAC_rx_clk_div ),
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//RMII interface (//PHY interface ),
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.MCrs_dv (MCrs_dv ),
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.MRxD (MRxD ),
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.MRxErr (MRxErr ),
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//flow_control signals (//flow_control signals ),
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.pause_quanta (pause_quanta ),
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.pause_quanta_val (pause_quanta_val ),
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//user interface (//user interface ),
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.Rx_mac_ra (Rx_mac_ra ),
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.Rx_mac_rd (Rx_mac_rd ),
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.Rx_mac_data (Rx_mac_data ),
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.Rx_mac_BE (Rx_mac_BE ),
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.Rx_mac_pa (Rx_mac_pa ),
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.Rx_mac_sop (Rx_mac_sop ),
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.Rx_mac_eop (Rx_mac_eop ),
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//CPU (//CPU ),
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.MAC_rx_add_chk_en (MAC_rx_add_chk_en ),
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.MAC_add_prom_data (MAC_rx_add_prom_data ),
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.MAC_add_prom_add (MAC_rx_add_prom_add ),
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.MAC_add_prom_wr (MAC_rx_add_prom_wr ),
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.broadcast_filter_en (broadcast_filter_en ),
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.broadcast_bucket_depth (broadcast_bucket_depth ),
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.broadcast_bucket_interval (broadcast_bucket_interval ),
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.RX_APPEND_CRC (RX_APPEND_CRC ),
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.Rx_Hwmark (Rx_Hwmark ),
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.Rx_Lwmark (Rx_Lwmark ),
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.CRC_chk_en (CRC_chk_en ),
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.RX_IFG_SET (RX_IFG_SET ),
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.RX_MAX_LENGTH (RX_MAX_LENGTH ),
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.RX_MIN_LENGTH (RX_MIN_LENGTH ),
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//RMON interface (//RMON interface ),
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.Rx_pkt_length_rmon (Rx_pkt_length_rmon ),
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.Rx_apply_rmon (Rx_apply_rmon ),
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.Rx_pkt_err_type_rmon (Rx_pkt_err_type_rmon ),
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.Rx_pkt_type_rmon (Rx_pkt_type_rmon )
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);
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MAC_tx U_MAC_tx(
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.Reset (Reset ),
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.Clk (MAC_tx_clk_div ),
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.Clk_user (Clk_user ),
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//PHY interface (//PHY interface ),
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.TxD (MTxD ),
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.TxEn (MTxEn ),
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.CRS (MCRS ),
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//RMON (//RMON ),
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.Tx_pkt_type_rmon (Tx_pkt_type_rmon ),
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.Tx_pkt_length_rmon (Tx_pkt_length_rmon ),
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.Tx_apply_rmon (Tx_apply_rmon ),
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.Tx_pkt_err_type_rmon (Tx_pkt_err_type_rmon ),
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//user interface (//user interface ),
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.Tx_mac_wa (Tx_mac_wa ),
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.Tx_mac_wr (Tx_mac_wr ),
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.Tx_mac_data (Tx_mac_data ),
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.Tx_mac_BE (Tx_mac_BE ),
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.Tx_mac_sop (Tx_mac_sop ),
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.Tx_mac_eop (Tx_mac_eop ),
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//host interface (//host interface ),
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.Tx_Hwmark (Tx_Hwmark ),
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.Tx_Lwmark (Tx_Lwmark ),
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.pause_frame_send_en (pause_frame_send_en ),
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.pause_quanta_set (pause_quanta_set ),
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.MAC_tx_add_en (MAC_tx_add_en ),
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.FullDuplex (FullDuplex ),
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.MaxRetry (MaxRetry ),
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.IFGset (IFGset ),
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.MAC_add_prom_data (MAC_tx_add_prom_data ),
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.MAC_add_prom_add (MAC_tx_add_prom_add ),
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| 278 |
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.MAC_add_prom_wr (MAC_tx_add_prom_wr ),
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| 279 |
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.tx_pause_en (tx_pause_en ),
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.xoff_cpu (xoff_cpu ),
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.xon_cpu (xon_cpu ),
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| 282 |
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//MAC_rx_flow (//MAC_rx_flow ),
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| 283 |
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.pause_quanta (pause_quanta ),
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.pause_quanta_val (pause_quanta_val )
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);
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| 286 |
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| 287 |
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| 288 |
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assign Pkg_lgth_fifo_ra=!Pkg_lgth_fifo_empty;
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| 289 |
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always @ (posedge Reset or posedge MAC_rx_clk_div)
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| 290 |
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if (Reset)
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| 291 |
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rx_pkg_lgth_fifo_wr_tmp <=0;
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| 292 |
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else if(Rx_apply_rmon&&Rx_pkt_err_type_rmon==3'b100)
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rx_pkg_lgth_fifo_wr_tmp <=1;
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| 294 |
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else
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| 295 |
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rx_pkg_lgth_fifo_wr_tmp <=0;
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| 296 |
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| 297 |
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always @ (posedge Reset or posedge MAC_rx_clk_div)
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| 298 |
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if (Reset)
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rx_pkg_lgth_fifo_wr_tmp_pl1 <=0;
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| 300 |
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else
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rx_pkg_lgth_fifo_wr_tmp_pl1 <=rx_pkg_lgth_fifo_wr_tmp;
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| 302 |
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| 303 |
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always @ (posedge Reset or posedge MAC_rx_clk_div)
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| 304 |
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if (Reset)
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rx_pkg_lgth_fifo_wr <=0;
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| 306 |
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else if(rx_pkg_lgth_fifo_wr_tmp&!rx_pkg_lgth_fifo_wr_tmp_pl1)
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| 307 |
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rx_pkg_lgth_fifo_wr <=1;
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| 308 |
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else
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| 309 |
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rx_pkg_lgth_fifo_wr <=0;
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| 310 |
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afifo U_rx_pkg_lgth_fifo (
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.din (RX_APPEND_CRC?Rx_pkt_length_rmon:Rx_pkt_length_rmon-4),
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.wr_en (rx_pkg_lgth_fifo_wr ),
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| 314 |
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.wr_clk (MAC_rx_clk_div ),
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| 315 |
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.rd_en (Pkg_lgth_fifo_rd ),
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| 316 |
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.rd_clk (Clk_user ),
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| 317 |
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.ainit (Reset ),
|
| 318 |
|
|
.dout (Pkg_lgth_fifo_data ),
|
| 319 |
|
|
.full ( ),
|
| 320 |
|
|
.almost_full ( ),
|
| 321 |
|
|
.empty (Pkg_lgth_fifo_empty ),
|
| 322 |
|
|
.wr_count ( ),
|
| 323 |
|
|
.rd_count ( ),
|
| 324 |
|
|
.rd_ack ( ),
|
| 325 |
|
|
.wr_ack ( ));
|
| 326 |
|
|
|
| 327 |
|
|
|
| 328 |
|
|
RMON U_RMON(
|
| 329 |
|
|
.Clk (Clk_reg ),
|
| 330 |
|
|
.Reset (Reset ),
|
| 331 |
|
|
//Tx_RMON (//Tx_RMON ),
|
| 332 |
|
|
.Tx_pkt_type_rmon (Tx_pkt_type_rmon ),
|
| 333 |
|
|
.Tx_pkt_length_rmon (Tx_pkt_length_rmon ),
|
| 334 |
|
|
.Tx_apply_rmon (Tx_apply_rmon ),
|
| 335 |
|
|
.Tx_pkt_err_type_rmon (Tx_pkt_err_type_rmon ),
|
| 336 |
|
|
//Tx_RMON (//Tx_RMON ),
|
| 337 |
|
|
.Rx_pkt_type_rmon (Rx_pkt_type_rmon ),
|
| 338 |
|
|
.Rx_pkt_length_rmon (Rx_pkt_length_rmon ),
|
| 339 |
|
|
.Rx_apply_rmon (Rx_apply_rmon ),
|
| 340 |
|
|
.Rx_pkt_err_type_rmon (Rx_pkt_err_type_rmon ),
|
| 341 |
|
|
//CPU (//CPU ),
|
| 342 |
|
|
.CPU_rd_addr (CPU_rd_addr ),
|
| 343 |
|
|
.CPU_rd_apply (CPU_rd_apply ),
|
| 344 |
|
|
.CPU_rd_grant (CPU_rd_grant ),
|
| 345 |
|
|
.CPU_rd_dout (CPU_rd_dout )
|
| 346 |
|
|
);
|
| 347 |
|
|
|
| 348 |
|
|
|
| 349 |
|
|
|
| 350 |
|
|
//Instead, tie signals from Tx/Rx statemachine directly to top
|
| 351 |
|
|
assign Tx_er = 1'b0;
|
| 352 |
|
|
assign Tx_en = MTxEn;
|
| 353 |
|
|
assign Txd = MTxD;
|
| 354 |
|
|
assign MRxErr = Rx_er;
|
| 355 |
|
|
assign MCrs_dv= Rx_dv;
|
| 356 |
|
|
assign MRxD = Rxd;
|
| 357 |
|
|
|
| 358 |
|
|
/* This module is disable */
|
| 359 |
|
|
//Phy_int U_Phy_int(
|
| 360 |
|
|
//.Reset (Reset ),
|
| 361 |
|
|
//.MAC_rx_clk (MAC_rx_clk ),
|
| 362 |
|
|
//.MAC_tx_clk (MAC_tx_clk ),
|
| 363 |
|
|
// //Rx interface (//Rx interface ),
|
| 364 |
|
|
//.MCrs_dv (MCrs_dv ),
|
| 365 |
|
|
//.MRxD (MRxD ),
|
| 366 |
|
|
//.MRxErr (MRxErr ),
|
| 367 |
|
|
// //Tx interface (//Tx interface ),
|
| 368 |
|
|
//.MTxD (MTxD ),
|
| 369 |
|
|
//.MTxEn (MTxEn ),
|
| 370 |
|
|
//.MCRS (MCRS ),
|
| 371 |
|
|
// //Phy interface (//Phy interface ),
|
| 372 |
|
|
//.Tx_er (Tx_er ),
|
| 373 |
|
|
//.Tx_en (Tx_en ),
|
| 374 |
|
|
//.Txd (Txd ),
|
| 375 |
|
|
//.Rx_er (Rx_er ),
|
| 376 |
|
|
//.Rx_dv (Rx_dv ),
|
| 377 |
|
|
//.Rxd (Rxd ),
|
| 378 |
|
|
//.Crs (Crs ),
|
| 379 |
|
|
//.Col (Col ),
|
| 380 |
|
|
// //host interface (//host interface ),
|
| 381 |
|
|
//.Line_loop_en (Line_loop_en ),
|
| 382 |
|
|
//.Speed (Speed )
|
| 383 |
|
|
//);
|
| 384 |
|
|
|
| 385 |
|
|
assign MAC_tx_clk_div = GMII_Tx_clk;
|
| 386 |
|
|
assign MAC_rx_clk_div = GMII_Rx_clk;
|
| 387 |
|
|
|
| 388 |
|
|
|
| 389 |
|
|
/* This block is no longer necessary */
|
| 390 |
|
|
/*
|
| 391 |
|
|
Clk_ctrl U_Clk_ctrl(
|
| 392 |
|
|
.Reset (Reset ),
|
| 393 |
|
|
.Clk_125M (Clk_125M ),
|
| 394 |
|
|
.Clk_25M (Clk_25M),
|
| 395 |
|
|
.Clk_125M_90 (Clk_125M_90),
|
| 396 |
|
|
.Clk_25M_90 (Clk_25M_90),
|
| 397 |
|
|
//host interface (//host interface ),
|
| 398 |
|
|
.Speed (Speed ),
|
| 399 |
|
|
//Phy interface (//Phy interface ),
|
| 400 |
|
|
.Gtx_clk (Gtx_clk ),
|
| 401 |
|
|
.Rx_clk (Rx_clk ),
|
| 402 |
|
|
//.Tx_clk (Tx_clk ),
|
| 403 |
|
|
//interface clk (//interface clk ),
|
| 404 |
|
|
.MAC_tx_clk_d (Gtx_clk_d),
|
| 405 |
|
|
.MAC_tx_clk (MAC_tx_clk ),
|
| 406 |
|
|
.MAC_rx_clk (MAC_rx_clk ),
|
| 407 |
|
|
.MAC_tx_clk_div (MAC_tx_clk_div ),
|
| 408 |
|
|
.MAC_rx_clk_div (MAC_rx_clk_div)
|
| 409 |
|
|
);*/
|
| 410 |
|
|
|
| 411 |
|
|
eth_miim U_eth_miim(
|
| 412 |
|
|
.Clk (Clk_reg ),
|
| 413 |
|
|
.Reset (Reset ),
|
| 414 |
|
|
.Divider (Divider ),
|
| 415 |
|
|
.NoPre (NoPre ),
|
| 416 |
|
|
.CtrlData (CtrlData ),
|
| 417 |
|
|
.Rgad (Rgad ),
|
| 418 |
|
|
.Fiad (Fiad ),
|
| 419 |
|
|
.WCtrlData (WCtrlData ),
|
| 420 |
|
|
.RStat (RStat ),
|
| 421 |
|
|
.ScanStat (ScanStat ),
|
| 422 |
|
|
.Mdo (Mdo ),
|
| 423 |
|
|
.MdoEn (MdoEn ),
|
| 424 |
|
|
.Mdi (Mdi ),
|
| 425 |
|
|
.Mdc (Mdc ),
|
| 426 |
|
|
.Busy (Busy ),
|
| 427 |
|
|
.Prsd (Prsd ),
|
| 428 |
|
|
.LinkFail (LinkFail ),
|
| 429 |
|
|
.Nvalid (Nvalid ),
|
| 430 |
|
|
.WCtrlDataStart (WCtrlDataStart ),
|
| 431 |
|
|
.RStatStart (RStatStart ),
|
| 432 |
|
|
.UpdateMIIRX_DATAReg (UpdateMIIRX_DATAReg ));
|
| 433 |
|
|
|
| 434 |
|
|
Reg_int U_Reg_int(
|
| 435 |
|
|
.Reset (Reset ),
|
| 436 |
|
|
.Clk_reg (Clk_reg ),
|
| 437 |
|
|
.CSB (CSB ),
|
| 438 |
|
|
.WRB (WRB ),
|
| 439 |
|
|
.CD_in (CD_in ),
|
| 440 |
|
|
.CD_out (CD_out ),
|
| 441 |
|
|
.CA (CA ),
|
| 442 |
|
|
//Tx host interface (//Tx host interface ),
|
| 443 |
|
|
.Tx_Hwmark (Tx_Hwmark ),
|
| 444 |
|
|
.Tx_Lwmark (Tx_Lwmark ),
|
| 445 |
|
|
.pause_frame_send_en (pause_frame_send_en ),
|
| 446 |
|
|
.pause_quanta_set (pause_quanta_set ),
|
| 447 |
|
|
.MAC_tx_add_en (MAC_tx_add_en ),
|
| 448 |
|
|
.FullDuplex (FullDuplex ),
|
| 449 |
|
|
.MaxRetry (MaxRetry ),
|
| 450 |
|
|
.IFGset (IFGset ),
|
| 451 |
|
|
.MAC_tx_add_prom_data (MAC_tx_add_prom_data ),
|
| 452 |
|
|
.MAC_tx_add_prom_add (MAC_tx_add_prom_add ),
|
| 453 |
|
|
.MAC_tx_add_prom_wr (MAC_tx_add_prom_wr ),
|
| 454 |
|
|
.tx_pause_en (tx_pause_en ),
|
| 455 |
|
|
.xoff_cpu (xoff_cpu ),
|
| 456 |
|
|
.xon_cpu (xon_cpu ),
|
| 457 |
|
|
//Rx host interface (//Rx host interface ),
|
| 458 |
|
|
.MAC_rx_add_chk_en (MAC_rx_add_chk_en ),
|
| 459 |
|
|
.MAC_rx_add_prom_data (MAC_rx_add_prom_data ),
|
| 460 |
|
|
.MAC_rx_add_prom_add (MAC_rx_add_prom_add ),
|
| 461 |
|
|
.MAC_rx_add_prom_wr (MAC_rx_add_prom_wr ),
|
| 462 |
|
|
.broadcast_filter_en (broadcast_filter_en ),
|
| 463 |
|
|
.broadcast_bucket_depth (broadcast_bucket_depth ),
|
| 464 |
|
|
.broadcast_bucket_interval (broadcast_bucket_interval ),
|
| 465 |
|
|
.RX_APPEND_CRC (RX_APPEND_CRC ),
|
| 466 |
|
|
.Rx_Hwmark (Rx_Hwmark ),
|
| 467 |
|
|
.Rx_Lwmark (Rx_Lwmark ),
|
| 468 |
|
|
.CRC_chk_en (CRC_chk_en ),
|
| 469 |
|
|
.RX_IFG_SET (RX_IFG_SET ),
|
| 470 |
|
|
.RX_MAX_LENGTH (RX_MAX_LENGTH ),
|
| 471 |
|
|
.RX_MIN_LENGTH (RX_MIN_LENGTH ),
|
| 472 |
|
|
//RMON host interface (//RMON host interface ),
|
| 473 |
|
|
.CPU_rd_addr (CPU_rd_addr ),
|
| 474 |
|
|
.CPU_rd_apply (CPU_rd_apply ),
|
| 475 |
|
|
.CPU_rd_grant (CPU_rd_grant ),
|
| 476 |
|
|
.CPU_rd_dout (CPU_rd_dout ),
|
| 477 |
|
|
//Phy int host interface (//Phy int host interface ),
|
| 478 |
|
|
.Line_loop_en (Line_loop_en ),
|
| 479 |
|
|
.Speed (Speed ),
|
| 480 |
|
|
//MII to CPU (//MII to CPU ),
|
| 481 |
|
|
.Divider (Divider ),
|
| 482 |
|
|
.CtrlData (CtrlData ),
|
| 483 |
|
|
.Rgad (Rgad ),
|
| 484 |
|
|
.Fiad (Fiad ),
|
| 485 |
|
|
.NoPre (NoPre ),
|
| 486 |
|
|
.WCtrlData (WCtrlData ),
|
| 487 |
|
|
.RStat (RStat ),
|
| 488 |
|
|
.ScanStat (ScanStat ),
|
| 489 |
|
|
.Busy (Busy ),
|
| 490 |
|
|
.LinkFail (LinkFail ),
|
| 491 |
|
|
.Nvalid (Nvalid ),
|
| 492 |
|
|
.Prsd (Prsd ),
|
| 493 |
|
|
.WCtrlDataStart (WCtrlDataStart ),
|
| 494 |
|
|
.RStatStart (RStatStart ),
|
| 495 |
|
|
.UpdateMIIRX_DATAReg (UpdateMIIRX_DATAReg )
|
| 496 |
|
|
);
|
| 497 |
|
|
|
| 498 |
|
|
endmodule
|
| 499 |
|
|
|
| 500 |
|
|
|
| 501 |
|
|
|
| 502 |
|
|
|
| 503 |
|
|
|
| 504 |
|
|
|
| 505 |
|
|
|
| 506 |
|
|
|
| 507 |
|
|
|
| 508 |
|
|
|
| 509 |
|
|
|
| 510 |
|
|
|
| 511 |
|
|
|
| 512 |
|
|
|
| 513 |
|
|
|
| 514 |
|
|
|
| 515 |
|
|
|
