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[/] [sgmii/] [trunk/] [build/] [OpenCore_MAC/] [MAC_top.v.bak] - Blame information for rev 26

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Line No. Rev Author Line
1 26 jefflieu
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  MAC_top.v                                                   ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Jon Gao (gaojon@yahoo.com)                            ////
10
////                                                              ////
11
////                                                              ////
12
//////////////////////////////////////////////////////////////////////
13
////                                                              ////
14
//// Copyright (C) 2001 Authors                                   ////
15
////                                                              ////
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//// This source file may be used and distributed without         ////
17
//// restriction provided that this copyright statement is not    ////
18
//// removed from the file and that any derivative work contains  ////
19
//// the original copyright notice and the associated disclaimer. ////
20
////                                                              ////
21
//// This source file is free software; you can redistribute it   ////
22
//// and/or modify it under the terms of the GNU Lesser General   ////
23
//// Public License as published by the Free Software Foundation; ////
24
//// either version 2.1 of the License, or (at your option) any   ////
25
//// later version.                                               ////
26
////                                                              ////
27
//// This source is distributed in the hope that it will be       ////
28
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
29
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
30
//// PURPOSE.  See the GNU Lesser General Public License for more ////
31
//// details.                                                     ////
32
////                                                              ////
33
//// You should have received a copy of the GNU Lesser General    ////
34
//// Public License along with this source; if not, download it   ////
35
//// from http://www.opencores.org/lgpl.shtml                     ////
36
////                                                              ////
37
//////////////////////////////////////////////////////////////////////
38
//
39
// CVS Revision History
40
//
41
// $Log: not supported by cvs2svn $
42
// Revision 1.3  2006/01/19 14:07:52  maverickist
43
// verification is complete.
44
//
45
// Revision 1.2  2005/12/16 06:44:13  Administrator
46
// replaced tab with space.
47
// passed 9.6k length frame test.
48
//
49
// Revision 1.1.1.1  2005/12/13 01:51:44  Administrator
50
// no message
51
//
52
// Due to CycloneIV starter board uses SGMII interface
53
// It's possible to remove the Phy_int module, and use PCS/PMA of Cyclone GxB
54
// Added Clk_MACTx and remove clock module as not necessary anymore
55
 
56
module MAC_top(
57
                //system signals
58
input           Reset                   ,
59
input           Clk_125M                ,
60
input           Clk_user                ,
61
input           Clk_reg                 ,
62
input                   Clk_125M_90                             ,
63
input                   Clk_25M_90                              ,
64
 
65
 
66
output  [2:0]   Speed                   ,
67
                //user interface
68
output          Rx_mac_ra               ,
69
input           Rx_mac_rd               ,
70
output  [31:0]  Rx_mac_data             ,
71
output  [1:0]   Rx_mac_BE               ,
72
output          Rx_mac_pa               ,
73
output          Rx_mac_sop              ,
74
output          Rx_mac_eop              ,
75
                //user interface
76
output          Tx_mac_wa               ,
77
input           Tx_mac_wr               ,
78
input   [31:0]  Tx_mac_data             ,
79
input   [1:0]   Tx_mac_BE               ,//big endian
80
input           Tx_mac_sop              ,
81
input           Tx_mac_eop              ,
82
                //pkg_lgth fifo
83
input           Pkg_lgth_fifo_rd        ,
84
output          Pkg_lgth_fifo_ra        ,
85
output  [15:0]  Pkg_lgth_fifo_data      ,
86
                //Phy interface
87
                //Phy interface
88
output                  Gtx_clk_d                               ,//shifted clock
89
output          Gtx_clk                 ,//used only in GMII mode
90
input           Rx_clk                  ,
91
input           Tx_clk                  ,//used only in MII mode
92
output          Tx_er                   ,
93
output          Tx_en                   ,
94
output  [7:0]   Txd                     ,
95
input           Rx_er                   ,
96
input           Rx_dv                   ,
97
input   [7:0]   Rxd                     ,
98
input           Crs                     ,
99
input           Col                     ,
100
                //host interface
101
input           CSB                     ,
102
input           WRB                     ,
103
input   [15:0]  CD_in                   ,
104
output  [15:0]  CD_out                  ,
105
input   [7:0]   CA                      ,
106
 
107
output  [23:0]  Monitoring                                       ,
108
                //mdx
109
output          Mdo,                // MII Management Data Output
110
output          MdoEn,              // MII Management Data Output Enable
111
input           Mdi,
112
output          Mdc                      // MII Management Data Clock
113
 
114
);
115
//******************************************************************************
116
//internal signals
117
//******************************************************************************
118
                //RMON interface
119
wire    [15:0]  Rx_pkt_length_rmon      ;
120
wire            Rx_apply_rmon           ;
121
wire    [2:0]   Rx_pkt_err_type_rmon    ;
122
wire    [2:0]   Rx_pkt_type_rmon        ;
123
wire    [2:0]   Tx_pkt_type_rmon        ;
124
wire    [15:0]  Tx_pkt_length_rmon      ;
125
wire            Tx_apply_rmon           ;
126
wire    [2:0]   Tx_pkt_err_type_rmon    ;
127
                //PHY interface
128
wire            MCrs_dv                 ;
129
wire    [7:0]   MRxD                    ;
130
wire            MRxErr                  ;
131
                //flow_control signals
132
wire    [15:0]  pause_quanta            ;
133
wire            pause_quanta_val        ;
134
                //PHY interface
135
wire    [7:0]   MTxD                    ;
136
wire            MTxEn                   ;
137
wire            MCRS                    ;
138
                //interface clk signals
139
wire            MAC_tx_clk              ;
140
wire            MAC_rx_clk              ;
141
wire            MAC_tx_clk_div          ;
142
wire            MAC_rx_clk_div          ;
143
                //reg signals
144
wire    [4:0]   Tx_Hwmark                               ;
145
wire    [4:0]   Tx_Lwmark                               ;
146
wire                    pause_frame_send_en             ;
147
wire    [15:0]  pause_quanta_set                ;
148
wire                    MAC_tx_add_en                   ;
149
wire                    FullDuplex                      ;
150
wire    [3:0]   MaxRetry                        ;
151
wire    [5:0]   IFGset                                  ;
152
wire    [7:0]   MAC_tx_add_prom_data    ;
153
wire    [2:0]   MAC_tx_add_prom_add             ;
154
wire                    MAC_tx_add_prom_wr              ;
155
wire                    tx_pause_en                             ;
156
wire                    xoff_cpu                        ;
157
wire                    xon_cpu                 ;
158
                        //Rx host interface
159
wire                    MAC_rx_add_chk_en               ;
160
wire    [7:0]   MAC_rx_add_prom_data    ;
161
wire    [2:0]   MAC_rx_add_prom_add             ;
162
wire                    MAC_rx_add_prom_wr              ;
163
wire                    broadcast_filter_en         ;
164
wire    [15:0]  broadcast_MAX           ;
165
wire                    RX_APPEND_CRC                   ;
166
wire    [4:0]   Rx_Hwmark                           ;
167
wire    [4:0]   Rx_Lwmark                           ;
168
wire                    CRC_chk_en                              ;
169
wire    [5:0]   RX_IFG_SET                              ;
170
wire    [15:0]  RX_MAX_LENGTH                   ;
171
wire    [6:0]   RX_MIN_LENGTH                   ;
172
                                        //RMON host interface
173
wire    [5:0]   CPU_rd_addr                             ;
174
wire                    CPU_rd_apply                    ;
175
wire                    CPU_rd_grant                    ;
176
wire    [31:0]  CPU_rd_dout                             ;
177
                                        //Phy int host interface
178
wire                    Line_loop_en                    ;
179
                                        //MII to CPU
180
wire    [7:0]   Divider                         ;
181
wire    [15:0]  CtrlData                        ;
182
wire    [4:0]   Rgad                            ;
183
wire    [4:0]   Fiad                            ;
184
wire            NoPre                           ;
185
wire            WCtrlData                       ;
186
wire            RStat                           ;
187
wire            ScanStat                        ;
188
wire            Busy                            ;
189
wire            LinkFail                        ;
190
wire            Nvalid                          ;
191
wire    [15:0]  Prsd                            ;
192
wire            WCtrlDataStart                  ;
193
wire            RStatStart                      ;
194
wire            UpdateMIIRX_DATAReg             ;
195
wire    [15:0]  broadcast_bucket_depth              ;
196
wire    [15:0]  broadcast_bucket_interval           ;
197
wire            Pkg_lgth_fifo_empty;
198
 
199
reg             rx_pkg_lgth_fifo_wr_tmp;
200
reg             rx_pkg_lgth_fifo_wr_tmp_pl1;
201
reg             rx_pkg_lgth_fifo_wr;
202
 
203
//******************************************************************************
204
//internal signals
205
//******************************************************************************
206
MAC_rx U_MAC_rx(
207
.Monitoring                                              (Monitoring),
208
.Reset                      (Reset                      ),
209
.Clk_user                   (Clk_user                   ),
210
.Clk                        (MAC_rx_clk_div             ),
211
 //RMII interface           (//PHY interface            ),
212
.MCrs_dv                    (MCrs_dv                    ),
213
.MRxD                       (MRxD                       ),
214
.MRxErr                     (MRxErr                     ),
215
 //flow_control signals     (//flow_control signals     ),
216
.pause_quanta               (pause_quanta               ),
217
.pause_quanta_val           (pause_quanta_val           ),
218
 //user interface           (//user interface           ),
219
.Rx_mac_ra                  (Rx_mac_ra                  ),
220
.Rx_mac_rd                  (Rx_mac_rd                  ),
221
.Rx_mac_data                (Rx_mac_data                ),
222
.Rx_mac_BE                  (Rx_mac_BE                  ),
223
.Rx_mac_pa                  (Rx_mac_pa                  ),
224
.Rx_mac_sop                 (Rx_mac_sop                 ),
225
.Rx_mac_eop                 (Rx_mac_eop                 ),
226
 //CPU                      (//CPU                      ),
227
.MAC_rx_add_chk_en          (MAC_rx_add_chk_en          ),
228
.MAC_add_prom_data          (MAC_rx_add_prom_data       ),
229
.MAC_add_prom_add           (MAC_rx_add_prom_add        ),
230
.MAC_add_prom_wr            (MAC_rx_add_prom_wr         ),
231
.broadcast_filter_en        (broadcast_filter_en        ),
232
.broadcast_bucket_depth     (broadcast_bucket_depth     ),
233
.broadcast_bucket_interval  (broadcast_bucket_interval  ),
234
.RX_APPEND_CRC              (RX_APPEND_CRC              ),
235
.Rx_Hwmark                  (Rx_Hwmark                  ),
236
.Rx_Lwmark                  (Rx_Lwmark                  ),
237
.CRC_chk_en                 (CRC_chk_en                 ),
238
.RX_IFG_SET                 (RX_IFG_SET                 ),
239
.RX_MAX_LENGTH              (RX_MAX_LENGTH              ),
240
.RX_MIN_LENGTH              (RX_MIN_LENGTH              ),
241
 //RMON interface           (//RMON interface           ),
242
.Rx_pkt_length_rmon         (Rx_pkt_length_rmon         ),
243
.Rx_apply_rmon              (Rx_apply_rmon              ),
244
.Rx_pkt_err_type_rmon       (Rx_pkt_err_type_rmon       ),
245
.Rx_pkt_type_rmon           (Rx_pkt_type_rmon           )
246
);
247
 
248
MAC_tx U_MAC_tx(
249
.Reset                      (Reset                      ),
250
.Clk                        (MAC_tx_clk_div             ),
251
.Clk_user                   (Clk_user                   ),
252
 //PHY interface            (//PHY interface            ),
253
.TxD                        (MTxD                       ),
254
.TxEn                       (MTxEn                      ),
255
.CRS                        (MCRS                       ),
256
 //RMON                     (//RMON                     ),
257
.Tx_pkt_type_rmon           (Tx_pkt_type_rmon           ),
258
.Tx_pkt_length_rmon         (Tx_pkt_length_rmon         ),
259
.Tx_apply_rmon              (Tx_apply_rmon              ),
260
.Tx_pkt_err_type_rmon       (Tx_pkt_err_type_rmon       ),
261
 //user interface           (//user interface           ),
262
.Tx_mac_wa                  (Tx_mac_wa                  ),
263
.Tx_mac_wr                  (Tx_mac_wr                  ),
264
.Tx_mac_data                (Tx_mac_data                ),
265
.Tx_mac_BE                  (Tx_mac_BE                  ),
266
.Tx_mac_sop                 (Tx_mac_sop                 ),
267
.Tx_mac_eop                 (Tx_mac_eop                 ),
268
 //host interface           (//host interface           ),
269
.Tx_Hwmark                  (Tx_Hwmark                  ),
270
.Tx_Lwmark                  (Tx_Lwmark                  ),
271
.pause_frame_send_en        (pause_frame_send_en        ),
272
.pause_quanta_set           (pause_quanta_set           ),
273
.MAC_tx_add_en              (MAC_tx_add_en              ),
274
.FullDuplex                 (FullDuplex                 ),
275
.MaxRetry                   (MaxRetry                   ),
276
.IFGset                     (IFGset                     ),
277
.MAC_add_prom_data          (MAC_tx_add_prom_data       ),
278
.MAC_add_prom_add           (MAC_tx_add_prom_add        ),
279
.MAC_add_prom_wr            (MAC_tx_add_prom_wr         ),
280
.tx_pause_en                (tx_pause_en                ),
281
.xoff_cpu                   (xoff_cpu                   ),
282
.xon_cpu                    (xon_cpu                    ),
283
 //MAC_rx_flow              (//MAC_rx_flow              ),
284
.pause_quanta               (pause_quanta               ),
285
.pause_quanta_val           (pause_quanta_val           )
286
);
287
 
288
 
289
assign Pkg_lgth_fifo_ra=!Pkg_lgth_fifo_empty;
290
always @ (posedge Reset or posedge MAC_rx_clk_div)
291
    if (Reset)
292
        rx_pkg_lgth_fifo_wr_tmp <=0;
293
    else if(Rx_apply_rmon&&Rx_pkt_err_type_rmon==3'b100)
294
        rx_pkg_lgth_fifo_wr_tmp <=1;
295
    else
296
        rx_pkg_lgth_fifo_wr_tmp <=0;
297
 
298
always @ (posedge Reset or posedge MAC_rx_clk_div)
299
    if (Reset)
300
        rx_pkg_lgth_fifo_wr_tmp_pl1 <=0;
301
    else
302
        rx_pkg_lgth_fifo_wr_tmp_pl1 <=rx_pkg_lgth_fifo_wr_tmp;
303
 
304
always @ (posedge Reset or posedge MAC_rx_clk_div)
305
    if (Reset)
306
        rx_pkg_lgth_fifo_wr <=0;
307
    else if(rx_pkg_lgth_fifo_wr_tmp&!rx_pkg_lgth_fifo_wr_tmp_pl1)
308
        rx_pkg_lgth_fifo_wr <=1;
309
    else
310
        rx_pkg_lgth_fifo_wr <=0;
311
 
312
afifo U_rx_pkg_lgth_fifo (
313
.din                        (RX_APPEND_CRC?Rx_pkt_length_rmon:Rx_pkt_length_rmon-4),
314
.wr_en                      (rx_pkg_lgth_fifo_wr        ),
315
.wr_clk                     (MAC_rx_clk_div             ),
316
.rd_en                      (Pkg_lgth_fifo_rd           ),
317
.rd_clk                     (Clk_user                   ),
318
.ainit                      (Reset                      ),
319
.dout                       (Pkg_lgth_fifo_data         ),
320
.full                       (                           ),
321
.almost_full                (                           ),
322
.empty                      (Pkg_lgth_fifo_empty        ),
323
.wr_count                   (                           ),
324
.rd_count                   (                           ),
325
.rd_ack                     (                           ),
326
.wr_ack                     (                           ));
327
 
328
 
329
RMON U_RMON(
330
.Clk                        (Clk_reg                    ),
331
.Reset                      (Reset                      ),
332
 //Tx_RMON                  (//Tx_RMON                  ),
333
.Tx_pkt_type_rmon           (Tx_pkt_type_rmon           ),
334
.Tx_pkt_length_rmon         (Tx_pkt_length_rmon         ),
335
.Tx_apply_rmon              (Tx_apply_rmon              ),
336
.Tx_pkt_err_type_rmon       (Tx_pkt_err_type_rmon       ),
337
 //Tx_RMON                  (//Tx_RMON                  ),
338
.Rx_pkt_type_rmon           (Rx_pkt_type_rmon           ),
339
.Rx_pkt_length_rmon         (Rx_pkt_length_rmon         ),
340
.Rx_apply_rmon              (Rx_apply_rmon              ),
341
.Rx_pkt_err_type_rmon       (Rx_pkt_err_type_rmon       ),
342
 //CPU                      (//CPU                      ),
343
.CPU_rd_addr                (CPU_rd_addr                ),
344
.CPU_rd_apply               (CPU_rd_apply               ),
345
.CPU_rd_grant               (CPU_rd_grant               ),
346
.CPU_rd_dout                (CPU_rd_dout                )
347
);
348
 
349
 
350
 
351
//Instead, tie signals from Tx/Rx statemachine directly to top
352
//assign Tx_er  = 1'b0;
353
//assign Tx_en  = MTxEn;
354
//assign Txd    = MTxD;
355
//assign MRxErr = Rx_er;
356
//assign MCrs_dv= Rx_dv;
357
//assign MRxD   = Rxd;
358
 
359
/* This module is disable */
360
Phy_int U_Phy_int(
361
.Reset                      (Reset                      ),
362
.MAC_rx_clk                 (MAC_rx_clk                 ),
363
.MAC_tx_clk                 (MAC_tx_clk                 ),
364
 //Rx interface             (//Rx interface             ),
365
.MCrs_dv                    (MCrs_dv                    ),
366
.MRxD                       (MRxD                       ),
367
.MRxErr                     (MRxErr                     ),
368
 //Tx interface             (//Tx interface             ),
369
.MTxD                       (MTxD                       ),
370
.MTxEn                      (MTxEn                      ),
371
.MCRS                       (MCRS                       ),
372
 //Phy interface            (//Phy interface            ),
373
.Tx_er                      (Tx_er                      ),
374
.Tx_en                      (Tx_en                      ),
375
.Txd                        (Txd                        ),
376
.Rx_er                      (Rx_er                      ),
377
.Rx_dv                      (Rx_dv                      ),
378
.Rxd                        (Rxd                        ),
379
.Crs                        (Crs                        ),
380
.Col                        (Col                        ),
381
 //host interface           (//host interface           ),
382
.Line_loop_en               (Line_loop_en               ),
383
.Speed                      (Speed                      )
384
);
385
 
386
/* This block is no longer necessary */
387
Clk_ctrl U_Clk_ctrl(
388
.Reset                      (Reset                      ),
389
.Clk_125M                   (Clk_125M                   ),
390
.Clk_25M                                        (Clk_25M),
391
.Clk_125M_90                            (Clk_125M_90),
392
.Clk_25M_90                                     (Clk_25M_90),
393
 //host interface           (//host interface           ),
394
.Speed                      (Speed                      ),
395
 //Phy interface            (//Phy interface            ),
396
.Gtx_clk                    (Gtx_clk                    ),
397
.Rx_clk                     (Rx_clk                     ),
398
.Tx_clk                     (Tx_clk                     ),
399
 //interface clk            (//interface clk            ),
400
.MAC_tx_clk_d                           (Gtx_clk_d),
401
.MAC_tx_clk                 (MAC_tx_clk                 ),
402
.MAC_rx_clk                 (MAC_rx_clk                 ),
403
.MAC_tx_clk_div             (MAC_tx_clk_div             ),
404
.MAC_rx_clk_div             (MAC_rx_clk_div)
405
);
406
 
407
eth_miim U_eth_miim(
408
.Clk                        (Clk_reg                    ),
409
.Reset                      (Reset                      ),
410
.Divider                    (Divider                    ),
411
.NoPre                      (NoPre                      ),
412
.CtrlData                   (CtrlData                   ),
413
.Rgad                       (Rgad                       ),
414
.Fiad                       (Fiad                       ),
415
.WCtrlData                  (WCtrlData                  ),
416
.RStat                      (RStat                      ),
417
.ScanStat                   (ScanStat                   ),
418
.Mdo                        (Mdo                        ),
419
.MdoEn                      (MdoEn                      ),
420
.Mdi                        (Mdi                        ),
421
.Mdc                        (Mdc                        ),
422
.Busy                       (Busy                       ),
423
.Prsd                       (Prsd                       ),
424
.LinkFail                   (LinkFail                   ),
425
.Nvalid                     (Nvalid                     ),
426
.WCtrlDataStart             (WCtrlDataStart             ),
427
.RStatStart                 (RStatStart                 ),
428
.UpdateMIIRX_DATAReg        (UpdateMIIRX_DATAReg        ));
429
 
430
Reg_int U_Reg_int(
431
.Reset                          (Reset                          ),
432
.Clk_reg                        (Clk_reg                        ),
433
.CSB                        (CSB                        ),
434
.WRB                        (WRB                        ),
435
.CD_in                      (CD_in                      ),
436
.CD_out                     (CD_out                     ),
437
.CA                         (CA                         ),
438
 //Tx host interface        (//Tx host interface        ),
439
.Tx_Hwmark                                  (Tx_Hwmark                              ),
440
.Tx_Lwmark                                  (Tx_Lwmark                              ),
441
.pause_frame_send_en            (pause_frame_send_en            ),
442
.pause_quanta_set                   (pause_quanta_set               ),
443
.MAC_tx_add_en                      (MAC_tx_add_en                          ),
444
.FullDuplex                     (FullDuplex                     ),
445
.MaxRetry                           (MaxRetry                       ),
446
.IFGset                                     (IFGset                                         ),
447
.MAC_tx_add_prom_data       (MAC_tx_add_prom_data           ),
448
.MAC_tx_add_prom_add            (MAC_tx_add_prom_add            ),
449
.MAC_tx_add_prom_wr                 (MAC_tx_add_prom_wr             ),
450
.tx_pause_en                            (tx_pause_en                            ),
451
.xoff_cpu                           (xoff_cpu                       ),
452
.xon_cpu                        (xon_cpu                        ),
453
 //Rx host interface        (//Rx host interface            ),
454
.MAC_rx_add_chk_en                  (MAC_rx_add_chk_en              ),
455
.MAC_rx_add_prom_data       (MAC_rx_add_prom_data           ),
456
.MAC_rx_add_prom_add            (MAC_rx_add_prom_add            ),
457
.MAC_rx_add_prom_wr                 (MAC_rx_add_prom_wr             ),
458
.broadcast_filter_en        (broadcast_filter_en            ),
459
.broadcast_bucket_depth     (broadcast_bucket_depth     ),
460
.broadcast_bucket_interval  (broadcast_bucket_interval  ),
461
.RX_APPEND_CRC                      (RX_APPEND_CRC                          ),
462
.Rx_Hwmark                              (Rx_Hwmark                                      ),
463
.Rx_Lwmark                  (Rx_Lwmark                  ),
464
.CRC_chk_en                                 (CRC_chk_en                             ),
465
.RX_IFG_SET                                 (RX_IFG_SET                             ),
466
.RX_MAX_LENGTH                      (RX_MAX_LENGTH                          ),
467
.RX_MIN_LENGTH                      (RX_MIN_LENGTH                          ),
468
 //RMON host interface      (//RMON host interface      ),
469
.CPU_rd_addr                            (CPU_rd_addr                            ),
470
.CPU_rd_apply                       (CPU_rd_apply                           ),
471
.CPU_rd_grant                       (CPU_rd_grant                           ),
472
.CPU_rd_dout                            (CPU_rd_dout                            ),
473
 //Phy int host interface   (//Phy int host interface   ),
474
.Line_loop_en                       (Line_loop_en                           ),
475
.Speed                                      (Speed                                          ),
476
 //MII to CPU               (//MII to CPU               ),
477
.Divider                        (Divider                        ),
478
.CtrlData                       (CtrlData                       ),
479
.Rgad                           (Rgad                           ),
480
.Fiad                           (Fiad                           ),
481
.NoPre                          (NoPre                          ),
482
.WCtrlData                      (WCtrlData                      ),
483
.RStat                          (RStat                          ),
484
.ScanStat                       (ScanStat                       ),
485
.Busy                           (Busy                           ),
486
.LinkFail                       (LinkFail                       ),
487
.Nvalid                         (Nvalid                         ),
488
.Prsd                           (Prsd                           ),
489
.WCtrlDataStart                 (WCtrlDataStart                 ),
490
.RStatStart                     (RStatStart                     ),
491
.UpdateMIIRX_DATAReg            (UpdateMIIRX_DATAReg            )
492
);
493
 
494
endmodule
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