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jefflieu |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// MAC_tx.v ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
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//// ////
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//// Author(s): ////
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//// - Jon Gao (gaojon@yahoo.com) ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2006/01/19 14:07:53 maverickist
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// verification is complete.
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//
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// Revision 1.2 2005/12/16 06:44:14 Administrator
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// replaced tab with space.
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// passed 9.6k length frame test.
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//
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// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
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// no message
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//
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`include "header.v"
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module MAC_tx(
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input Reset ,
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input Clk ,
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input Clk_user ,
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//PHY interface
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output [7:0] TxD ,
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output TxEn ,
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input CRS ,
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//RMON
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output [2:0] Tx_pkt_type_rmon ,
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output [15:0] Tx_pkt_length_rmon ,
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output Tx_apply_rmon ,
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output [2:0] Tx_pkt_err_type_rmon,
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//user interface
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output Tx_mac_wa ,
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input Tx_mac_wr ,
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input [31:0] Tx_mac_data ,
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input [1:0] Tx_mac_BE ,//big endian
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input Tx_mac_sop ,
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input Tx_mac_eop ,
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//host interface
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input [4:0] Tx_Hwmark ,
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input [4:0] Tx_Lwmark ,
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input pause_frame_send_en ,
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input [15:0] pause_quanta_set ,
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input MAC_tx_add_en ,
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input FullDuplex ,
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input [3:0] MaxRetry ,
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input [5:0] IFGset ,
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input [7:0] MAC_add_prom_data ,
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input [2:0] MAC_add_prom_add ,
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input MAC_add_prom_wr ,
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input tx_pause_en ,
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input xoff_cpu ,
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input xon_cpu ,
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//MAC_rx_flow ,
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input [15:0] pause_quanta ,
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input pause_quanta_val
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);
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//******************************************************************************
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//internal signals
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//******************************************************************************
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//CRC_gen Interface
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wire CRC_init ;
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wire[7:0] Frame_data ;
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wire Data_en ;
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wire CRC_rd ;
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wire CRC_end ;
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wire[7:0] CRC_out ;
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//Ramdon_gen interface
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wire Random_init ;
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wire[3:0] RetryCnt ;
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wire Random_time_meet ;//levle hight indicate random time passed away
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//flow control
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wire pause_apply ;
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wire pause_quanta_sub ;
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wire xoff_gen ;
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wire xoff_gen_complete ;
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wire xon_gen ;
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wire xon_gen_complete ;
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//MAC_rx_FF
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wire[7:0] Fifo_data ;
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wire Fifo_rd ;
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wire Fifo_eop ;
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wire Fifo_da ;
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wire Fifo_rd_finish ;
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wire Fifo_rd_retry ;
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wire Fifo_ra ;
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wire Fifo_data_err_empty ;
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wire Fifo_data_err_full ;
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//MAC_tx_addr_add
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wire MAC_tx_addr_init ;
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wire MAC_tx_addr_rd ;
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wire[7:0] MAC_tx_addr_data ;
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//******************************************************************************
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//instantiation
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//******************************************************************************
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MAC_tx_ctrl U_MAC_tx_ctrl(
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.Reset (Reset ),
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.Clk (Clk ),
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//CRC_gen Interface (//CRC_gen Interface ),
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.CRC_init (CRC_init ),
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.Frame_data (Frame_data ),
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.Data_en (Data_en ),
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.CRC_rd (CRC_rd ),
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.CRC_end (CRC_end ),
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.CRC_out (CRC_out ),
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//Ramdon_gen interfac (//Ramdon_gen interfac ),
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.Random_init (Random_init ),
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.RetryCnt (RetryCnt ),
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.Random_time_meet (Random_time_meet ),
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//flow control (//flow control ),
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.pause_apply (pause_apply ),
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.pause_quanta_sub (pause_quanta_sub ),
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.xoff_gen (xoff_gen ),
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.xoff_gen_complete (xoff_gen_complete ),
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.xon_gen (xon_gen ),
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.xon_gen_complete (xon_gen_complete ),
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//MAC_tx_FF (//MAC_tx_FF ),
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.Fifo_data (Fifo_data ),
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.Fifo_rd (Fifo_rd ),
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.Fifo_eop (Fifo_eop ),
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.Fifo_da (Fifo_da ),
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.Fifo_rd_finish (Fifo_rd_finish ),
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.Fifo_rd_retry (Fifo_rd_retry ),
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.Fifo_ra (Fifo_ra ),
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.Fifo_data_err_empty (Fifo_data_err_empty ),
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.Fifo_data_err_full (Fifo_data_err_full ),
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//RMII (//RMII ),
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.TxD (TxD ),
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.TxEn (TxEn ),
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.CRS (CRS ),
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//MAC_tx_addr_add (//MAC_tx_addr_add ),
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.MAC_tx_addr_rd (MAC_tx_addr_rd ),
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.MAC_tx_addr_data (MAC_tx_addr_data ),
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.MAC_tx_addr_init (MAC_tx_addr_init ),
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//RMON (//RMON ),
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.Tx_pkt_type_rmon (Tx_pkt_type_rmon ),
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.Tx_pkt_length_rmon (Tx_pkt_length_rmon ),
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.Tx_apply_rmon (Tx_apply_rmon ),
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.Tx_pkt_err_type_rmon (Tx_pkt_err_type_rmon ),
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//CPU (//CPU ),
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.pause_frame_send_en (pause_frame_send_en ),
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.pause_quanta_set (pause_quanta_set ),
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.MAC_tx_add_en (MAC_tx_add_en ),
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.FullDuplex (FullDuplex ),
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.MaxRetry (MaxRetry ),
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.IFGset (IFGset )
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);
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CRC_gen U_CRC_gen(
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.Reset (Reset ),
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.Clk (Clk ),
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.Init (CRC_init ),
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.Frame_data (Frame_data ),
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.Data_en (Data_en ),
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.CRC_rd (CRC_rd ),
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.CRC_out (CRC_out ),
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.CRC_end (CRC_end )
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);
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flow_ctrl U_flow_ctrl(
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.Reset (Reset ),
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.Clk (Clk ),
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//host processor (//host processor ),
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.tx_pause_en (tx_pause_en ),
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.xoff_cpu (xoff_cpu ),
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.xon_cpu (xon_cpu ),
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//MAC_rx_flow (//MAC_rx_flow ),
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.pause_quanta (pause_quanta ),
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.pause_quanta_val (pause_quanta_val ),
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//MAC_tx_ctrl (//MAC_tx_ctrl ),
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.pause_apply (pause_apply ),
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.pause_quanta_sub (pause_quanta_sub ),
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.xoff_gen (xoff_gen ),
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.xoff_gen_complete (xoff_gen_complete ),
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.xon_gen (xon_gen ),
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.xon_gen_complete (xon_gen_complete )
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);
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`ifdef MAC_SOURCE_REPLACE_EN
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MAC_tx_addr_add U_MAC_tx_addr_add(
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.Reset (Reset ),
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.Clk (Clk ),
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.MAC_tx_addr_rd (MAC_tx_addr_rd ),
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.MAC_tx_addr_init (MAC_tx_addr_init ),
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.MAC_tx_addr_data (MAC_tx_addr_data ),
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//CPU (//CPU ),
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.MAC_add_prom_data (MAC_add_prom_data ),
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.MAC_add_prom_add (MAC_add_prom_add ),
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.MAC_add_prom_wr (MAC_add_prom_wr )
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);
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`else
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assign MAC_tx_addr_data=0;
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`endif
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MAC_tx_FF U_MAC_tx_FF(
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.Reset (Reset ),
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.Clk_MAC (Clk ),
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.Clk_SYS (Clk_user ),
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//MAC_rx_ctrl interf (//MAC_rx_ctrl interf ),
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.Fifo_data (Fifo_data ),
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.Fifo_rd (Fifo_rd ),
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.Fifo_rd_finish (Fifo_rd_finish ),
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.Fifo_rd_retry (Fifo_rd_retry ),
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.Fifo_eop (Fifo_eop ),
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.Fifo_da (Fifo_da ),
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.Fifo_ra (Fifo_ra ),
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.Fifo_data_err_empty (Fifo_data_err_empty ),
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.Fifo_data_err_full (Fifo_data_err_full ),
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//user interface (//user interface ),
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.Tx_mac_wa (Tx_mac_wa ),
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.Tx_mac_wr (Tx_mac_wr ),
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.Tx_mac_data (Tx_mac_data ),
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.Tx_mac_BE (Tx_mac_BE ),
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.Tx_mac_sop (Tx_mac_sop ),
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.Tx_mac_eop (Tx_mac_eop ),
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//host interface (//host interface ),
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.FullDuplex (FullDuplex ),
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.Tx_Hwmark (Tx_Hwmark ),
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.Tx_Lwmark (Tx_Lwmark )
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);
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Ramdon_gen U_Ramdon_gen(
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.Reset (Reset ),
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.Clk (Clk ),
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.Init (Random_init ),
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.RetryCnt (RetryCnt ),
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.Random_time_meet (Random_time_meet )
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);
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endmodule
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