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[/] [sgmii/] [trunk/] [build/] [OpenCore_MAC/] [MAC_tx_Ctrl.v] - Blame information for rev 26

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  MAC_tx_ctrl.v                                               ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
////                                                              ////
////  Author(s):                                                  ////
////      - Jon Gao (gaojon@yahoo.com)                            ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//                                                                    
// CVS Revision History                                               
//                                                                    
// $Log: not supported by cvs2svn $
// Revision 1.3  2006/01/19 14:07:54  maverickist
// verification is complete.
//
// Revision 1.3  2005/12/16 06:44:17  Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.2  2005/12/13 12:15:38  Administrator
// no message
//
// Revision 1.1.1.1  2005/12/13 01:51:45  Administrator
// no message
//                                           
 
module MAC_tx_ctrl (
Reset               ,
Clk                 ,
//CRC_gen Interface  
CRC_init            ,
Frame_data          ,
Data_en             ,
CRC_rd              ,
CRC_end             ,
CRC_out             ,
//Ramdon_gen interfac
Random_init         ,
RetryCnt            ,
Random_time_meet    ,
//flow control      
pause_apply         ,
pause_quanta_sub    ,
xoff_gen            ,
xoff_gen_complete   ,
xon_gen             ,
xon_gen_complete    ,
//MAC_tx_FF          
Fifo_data           ,
Fifo_rd             ,
Fifo_eop            ,
Fifo_da             ,
Fifo_rd_finish      ,
Fifo_rd_retry       ,
Fifo_ra             ,
Fifo_data_err_empty ,
Fifo_data_err_full  ,
//RMII               
TxD                 ,
TxEn                ,
CRS                 ,
//MAC_tx_addr_add   
MAC_tx_addr_rd      ,
MAC_tx_addr_data    ,
MAC_tx_addr_init    ,
//RMON               
Tx_pkt_type_rmon    ,
Tx_pkt_length_rmon  ,
Tx_apply_rmon       ,
Tx_pkt_err_type_rmon,
//CPU  
pause_frame_send_en ,
pause_quanta_set    ,
MAC_tx_add_en       ,
FullDuplex          ,
MaxRetry            ,
IFGset
);
 
input           Reset               ;
input           Clk                 ;
                //CRC_gen Interface 
output          CRC_init            ;
output  [7:0]   Frame_data          ;
output          Data_en             ;
output          CRC_rd              ;
input           CRC_end             ;
input   [7:0]   CRC_out             ;
                //Ramdon_gen interface
output          Random_init         ;
output  [3:0]   RetryCnt            ;
input           Random_time_meet    ;//levle hight indicate random time passed away
                //flow control
input           pause_apply         ;
output          pause_quanta_sub    ;
input           xoff_gen            ;
output          xoff_gen_complete   ;
input           xon_gen             ;
output          xon_gen_complete    ;
                //MAC_rx_FF
input   [7:0]   Fifo_data           ;
output          Fifo_rd             ;
input           Fifo_eop            ;
input           Fifo_da             ;
output          Fifo_rd_finish      ;
output          Fifo_rd_retry       ;
input           Fifo_ra             ;
input           Fifo_data_err_empty ;
input           Fifo_data_err_full  ;
                //RMII
output  [7:0]   TxD                 ;
output          TxEn                ;
input           CRS                 ;
                //MAC_tx_addr_add
output          MAC_tx_addr_init    ;
output          MAC_tx_addr_rd      ;
input   [7:0]   MAC_tx_addr_data    ;
                //RMON
output  [2:0]   Tx_pkt_type_rmon    ;
output  [15:0]  Tx_pkt_length_rmon  ;
output          Tx_apply_rmon       ;
output  [2:0]   Tx_pkt_err_type_rmon;
                //CPU
input           pause_frame_send_en ;
input   [15:0]  pause_quanta_set    ;
input           MAC_tx_add_en       ;
input           FullDuplex          ;
input   [3:0]   MaxRetry            ;
input   [5:0]   IFGset              ;
//******************************************************************************        
//internal signals                                                              
//******************************************************************************   
parameter       StateIdle           =4'd00;
parameter       StatePreamble       =4'd01;
parameter       StateSFD            =4'd02;
parameter       StateData           =4'd03;
parameter       StatePause          =4'd04;
parameter       StatePAD            =4'd05;
parameter       StateFCS            =4'd06;
parameter       StateIFG            =4'd07;
parameter       StateJam            =4'd08;
parameter       StateBackOff        =4'd09;
parameter       StateJamDrop        =4'd10;
parameter       StateFFEmptyDrop    =4'd11;
parameter       StateSwitchNext     =4'd12;
parameter       StateDefer          =4'd13;
parameter       StateSendPauseFrame =4'd14;
 
reg [3:0]       Current_state   /*synthesis syn_keep=1 */;
reg [3:0]       Next_state;
reg [5:0]       IFG_counter;
reg [4:0]       Preamble_counter;//
reg [7:0]       TxD_tmp             ;
reg             TxEn_tmp            ;
reg [15:0]      Tx_pkt_length_rmon  ;
reg             Tx_apply_rmon       ;
reg             Tx_apply_rmon_tmp   ;
reg             Tx_apply_rmon_tmp_pl1;
reg [2:0]       Tx_pkt_err_type_rmon;
reg [3:0]       RetryCnt            ;
reg             Random_init         ;
reg             Fifo_rd_finish      ;
reg             Fifo_rd_retry       ;
reg [7:0]       TxD                 ;
reg             TxEn                ;
reg             CRC_init            ;
reg             Data_en             ;
reg             CRC_rd              ;
reg             Fifo_rd             ;
reg             MAC_tx_addr_rd      ;
reg             MAC_header_slot     ;
reg             MAC_header_slot_tmp ;
reg [2:0]       Tx_pkt_type_rmon    ;
wire            Collision           ;
reg             MAC_tx_addr_init    ;
reg             Src_MAC_ptr         ;
reg [7:0]       IPLengthCounter     ;//for pad append
reg [1:0]       PADCounter          ;
reg [7:0]       JamCounter          ;
reg             PktDrpEvenPtr       ;
reg [7:0]       pause_counter       ;
reg             pause_quanta_sub    ;
reg             pause_frame_send_en_dl1 ;
reg [15:0]      pause_quanta_set_dl1    ;
reg             xoff_gen_complete   ;
reg             xon_gen_complete    ;
//******************************************************************************    
//boundery signal processing                                                             
//****************************************************************************** 
always @(posedge Clk or posedge Reset)
    if (Reset)
        begin
        pause_frame_send_en_dl1         <=0;
        pause_quanta_set_dl1            <=0;
        end
    else
        begin
        pause_frame_send_en_dl1         <=pause_frame_send_en   ;
        pause_quanta_set_dl1            <=pause_quanta_set      ;
        end
//******************************************************************************    
//state machine                                                             
//****************************************************************************** 
assign Collision=TxEn&CRS;
 
always @(posedge Clk or posedge Reset)
    if (Reset)
        pause_counter   <=0;
    else if (Current_state!=StatePause)
        pause_counter   <=0;
    else
        pause_counter   <=pause_counter+1;
 
always @(posedge Clk or posedge Reset)
    if (Reset)
        IPLengthCounter     <=0;
    else if (Current_state==StateDefer)
        IPLengthCounter     <=0;
    else if (IPLengthCounter!=8'hff&&(Current_state==StateData||Current_state==StateSendPauseFrame||Current_state==StatePAD))
        IPLengthCounter     <=IPLengthCounter+1;
 
always @(posedge Clk or posedge Reset)
    if (Reset)
        PADCounter      <=0;
    else if (Current_state!=StatePAD)
        PADCounter      <=0;
    else
        PADCounter      <=PADCounter+1;
 
always @(posedge Clk or posedge Reset)
    if (Reset)
        Current_state       <=StateDefer;
    else
        Current_state       <=Next_state;
 
always @ (*)
        case (Current_state)
            StateDefer:
                if ((FullDuplex)||(!FullDuplex&&!CRS))
                    Next_state=StateIFG;
                else
                    Next_state=Current_state;
            StateIFG:
                if (!FullDuplex&&CRS)
                    Next_state=StateDefer;
                else if ((FullDuplex&&IFG_counter==IFGset-4)||(!FullDuplex&&!CRS&&IFG_counter==IFGset-4))//remove some additional time
                    Next_state=StateIdle;
                else
                    Next_state=Current_state;
            StateIdle:
                if (!FullDuplex&&CRS)
                    Next_state=StateDefer;
                else if (pause_apply)
                    Next_state=StatePause;
                else if ((FullDuplex&&Fifo_ra)||(!FullDuplex&&!CRS&&Fifo_ra)||(pause_frame_send_en_dl1&&(xoff_gen||xon_gen)))
                    Next_state=StatePreamble;
                else
                    Next_state=Current_state;
            StatePause:
                if (pause_counter==512/8)
                    Next_state=StateDefer;
                else
                    Next_state=Current_state;
            StatePreamble:
                if (!FullDuplex&&Collision)
                    Next_state=StateJam;
                else if ((FullDuplex&&Preamble_counter==6)||(!FullDuplex&&!Collision&&Preamble_counter==6))
                    Next_state=StateSFD;
                else
                    Next_state=Current_state;
            StateSFD:
                if (!FullDuplex&&Collision)
                    Next_state=StateJam;
                else if (pause_frame_send_en_dl1&&(xoff_gen||xon_gen))
                    Next_state=StateSendPauseFrame;
                else
                    Next_state=StateData;
            StateSendPauseFrame:
                if (IPLengthCounter==17)
                    Next_state=StatePAD;
                else
                    Next_state=Current_state;
            StateData:
                if (!FullDuplex&&Collision)
                    Next_state=StateJam;
                else if (Fifo_data_err_empty)
                    Next_state=StateFFEmptyDrop;
                else if (Fifo_eop&&IPLengthCounter>=59)//IP+MAC+TYPE=60 ,start from 0
                    Next_state=StateFCS;
                else if (Fifo_eop)
                    Next_state=StatePAD;
                else
                    Next_state=StateData;
            StatePAD:
                if (!FullDuplex&&Collision)
                    Next_state=StateJam;
                else if (IPLengthCounter>=59)
                    Next_state=StateFCS;
                else
                    Next_state=Current_state;
            StateJam:
                if (RetryCnt<=MaxRetry&&JamCounter==16)
                    Next_state=StateBackOff;
                else if (RetryCnt>MaxRetry)
                    Next_state=StateJamDrop;
                else
                    Next_state=Current_state;
            StateBackOff:
                if (Random_time_meet)
                    Next_state  =StateDefer;
                else
                    Next_state  =Current_state;
            StateFCS:
                if (!FullDuplex&&Collision)
                    Next_state  =StateJam;
                else if (CRC_end)
                    Next_state  =StateSwitchNext;
                else
                    Next_state  =Current_state;
            StateFFEmptyDrop:
                if (Fifo_eop)
                    Next_state  =StateSwitchNext;
                else
                    Next_state  =Current_state;
            StateJamDrop:
                if (Fifo_eop)
                    Next_state  =StateSwitchNext;
                else
                    Next_state  =Current_state;
            StateSwitchNext:
                    Next_state  =StateDefer;
            default:
                Next_state  =StateDefer;
        endcase
 
 
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        JamCounter      <=0;
    else if (Current_state!=StateJam)
        JamCounter      <=0;
    else if (Current_state==StateJam)
        JamCounter      <=JamCounter+1;
 
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        RetryCnt        <=0;
    else if (Current_state==StateSwitchNext)
        RetryCnt        <=0;
    else if (Current_state==StateJam&&Next_state==StateBackOff)
        RetryCnt        <=RetryCnt + 1;
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        IFG_counter     <=0;
    else if (Current_state!=StateIFG)
        IFG_counter     <=0;
    else
        IFG_counter     <=IFG_counter + 1;
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Preamble_counter    <=0;
    else if (Current_state!=StatePreamble)
        Preamble_counter    <=0;
    else
        Preamble_counter    <=Preamble_counter+ 1;
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        PktDrpEvenPtr       <=0;
    else if(Current_state==StateJamDrop||Current_state==StateFFEmptyDrop)
        PktDrpEvenPtr       <=~PktDrpEvenPtr;
//******************************************************************************    
//generate output signals                                                           
//****************************************************************************** 
//CRC related
always @(Current_state)
    if (Current_state==StateSFD)
        CRC_init    =1;
    else
        CRC_init    =0;
 
assign Frame_data=TxD_tmp;
 
always @(Current_state)
    if (Current_state==StateData||Current_state==StateSendPauseFrame||Current_state==StatePAD)
        Data_en     =1;
    else
        Data_en     =0;
 
always @(Current_state)
    if (Current_state==StateFCS)
        CRC_rd      =1;
    else
        CRC_rd      =0;
 
//Ramdon_gen interface
always @(Current_state or Next_state)
    if (Current_state==StateJam&&Next_state==StateBackOff)
        Random_init =1;
    else
        Random_init =0;
 
//MAC_rx_FF
//data have one cycle delay after fifo read signals  
always @ (*)
    if (Current_state==StateData ||
        Current_state==StateSFD&&!(pause_frame_send_en_dl1&&(xoff_gen||xon_gen))  ||
        Current_state==StateJamDrop&&PktDrpEvenPtr||
        Current_state==StateFFEmptyDrop&&PktDrpEvenPtr )
        Fifo_rd     =1;
    else
        Fifo_rd     =0;
 
always @ (Current_state)
    if (Current_state==StateSwitchNext)
        Fifo_rd_finish  =1;
    else
        Fifo_rd_finish  =0;
 
always @ (Current_state)
    if (Current_state==StateJam)
        Fifo_rd_retry   =1;
    else
        Fifo_rd_retry   =0;
//RMII
always @(Current_state)
    if (Current_state==StatePreamble||Current_state==StateSFD||
        Current_state==StateData||Current_state==StateSendPauseFrame||
        Current_state==StateFCS||Current_state==StatePAD||Current_state==StateJam)
        TxEn_tmp    =1;
    else
        TxEn_tmp    =0;
 
//gen txd data      
always @(*)
    case (Current_state)
        StatePreamble:
            TxD_tmp =8'h55;
        StateSFD:
            TxD_tmp =8'hd5;
        StateData:
            if (Src_MAC_ptr&&MAC_tx_add_en)
                TxD_tmp =MAC_tx_addr_data;
            else
                TxD_tmp =Fifo_data;
        StateSendPauseFrame:
            if (Src_MAC_ptr&&MAC_tx_add_en)
                TxD_tmp =MAC_tx_addr_data;
            else
                case (IPLengthCounter)
                    7'd0:   TxD_tmp =8'h01;
                    7'd1:   TxD_tmp =8'h80;
                    7'd2:   TxD_tmp =8'hc2;
                    7'd3:   TxD_tmp =8'h00;
                    7'd4:   TxD_tmp =8'h00;
                    7'd5:   TxD_tmp =8'h01;
                    7'd12:  TxD_tmp =8'h88;//type
                    7'd13:  TxD_tmp =8'h08;//
                    7'd14:  TxD_tmp =8'h00;//opcode
                    7'd15:  TxD_tmp =8'h01;
                    7'd16:  TxD_tmp =xon_gen?8'b0:pause_quanta_set_dl1[15:8];
                    7'd17:  TxD_tmp =xon_gen?8'b0:pause_quanta_set_dl1[7:0];
//                    7'd60:  TxD_tmp =8'h26;
//                    7'd61:  TxD_tmp =8'h6b;
//                    7'd62:  TxD_tmp =8'hae;
//                    7'd63:  TxD_tmp =8'h0a;
                    default:TxD_tmp =0;
                endcase
 
        StatePAD:
                TxD_tmp =8'h00;
        StateJam:
                TxD_tmp =8'h01; //jam sequence
        StateFCS:
            TxD_tmp =CRC_out;
        default:
            TxD_tmp =2'b0;
    endcase
always @ (posedge Clk or posedge Reset)
    if (Reset)
        begin
        TxD     <=0;
        TxEn    <=0;
        end
    else
        begin
        TxD     <=TxD_tmp;
        TxEn    <=TxEn_tmp;
        end
//RMON
 
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Tx_pkt_length_rmon      <=0;
    else if (Current_state==StateSFD)
        Tx_pkt_length_rmon      <=0;
    else if (Current_state==StateData||Current_state==StateSendPauseFrame||Current_state==StatePAD||Current_state==StateFCS)
        Tx_pkt_length_rmon      <=Tx_pkt_length_rmon+1;
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Tx_apply_rmon_tmp       <=0;
    else if ((Fifo_eop&&Current_state==StateJamDrop)||
             (Fifo_eop&&Current_state==StateFFEmptyDrop)||
             CRC_end)
        Tx_apply_rmon_tmp       <=1;
    else
        Tx_apply_rmon_tmp       <=0;
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Tx_apply_rmon_tmp_pl1   <=0;
    else
        Tx_apply_rmon_tmp_pl1   <=Tx_apply_rmon_tmp;
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Tx_apply_rmon       <=0;
    else if ((Fifo_eop&&Current_state==StateJamDrop)||
             (Fifo_eop&&Current_state==StateFFEmptyDrop)||
             CRC_end)
        Tx_apply_rmon       <=1;
    else if (Tx_apply_rmon_tmp_pl1)
        Tx_apply_rmon       <=0;
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Tx_pkt_err_type_rmon    <=0;
    else if(Fifo_eop&&Current_state==StateJamDrop)
        Tx_pkt_err_type_rmon    <=3'b001;//
    else if(Fifo_eop&&Current_state==StateFFEmptyDrop)
        Tx_pkt_err_type_rmon    <=3'b010;//underflow
    else if(Fifo_eop&&Fifo_data_err_full)
        Tx_pkt_err_type_rmon    <=3'b011;//overflow
    else if(CRC_end)
        Tx_pkt_err_type_rmon    <=3'b100;//normal
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        MAC_header_slot_tmp <=0;
    else if(Current_state==StateSFD&&Next_state==StateData)
        MAC_header_slot_tmp <=1;
    else
        MAC_header_slot_tmp <=0;
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        MAC_header_slot     <=0;
    else
        MAC_header_slot     <=MAC_header_slot_tmp;
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Tx_pkt_type_rmon    <=0;
    else if (Current_state==StateSendPauseFrame)
        Tx_pkt_type_rmon    <=3'b100;
    else if(MAC_header_slot)
        Tx_pkt_type_rmon    <={1'b0,TxD[7:6]};
 
 
always @(Tx_pkt_length_rmon)
    if (Tx_pkt_length_rmon>=6&&Tx_pkt_length_rmon<=11)
        Src_MAC_ptr         =1;
    else
        Src_MAC_ptr         =0;
 
//MAC_tx_addr_add  
always @ (posedge Clk or posedge Reset)
    if (Reset)
        MAC_tx_addr_rd  <=0;
    else if ((Tx_pkt_length_rmon>=4&&Tx_pkt_length_rmon<=9)&&(MAC_tx_add_en||Current_state==StateSendPauseFrame))
        MAC_tx_addr_rd  <=1;
    else
        MAC_tx_addr_rd  <=0;
 
always @ (Tx_pkt_length_rmon or Fifo_rd)
    if ((Tx_pkt_length_rmon==3)&&Fifo_rd)
        MAC_tx_addr_init=1;
    else
        MAC_tx_addr_init=0;
 
//flow control
always @ (posedge Clk or posedge Reset)
    if (Reset)
        pause_quanta_sub    <=0;
    else if(pause_counter==512/8)
        pause_quanta_sub    <=1;
    else
        pause_quanta_sub    <=0;
 
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        xoff_gen_complete   <=0;
    else if(Current_state==StateDefer&&xoff_gen)
        xoff_gen_complete   <=1;
    else
        xoff_gen_complete   <=0;
 
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        xon_gen_complete    <=0;
    else if(Current_state==StateDefer&&xon_gen)
        xon_gen_complete    <=1;
    else
        xon_gen_complete    <=0;
 
endmodule

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[/] [sgmii/] [trunk/] [build/] [OpenCore_MAC/] [MAC_tx_Ctrl.v] - Blame information for rev 26

Line No.	Rev	Author	Line
1	26	jefflieu	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// MAC_tx_ctrl.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Jon Gao (gaojon@yahoo.com) ////`
10			`//// ////`
11			`//// ////`
12			`//////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Authors ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer. ////`
20			`//// ////`
21			`//// This source file is free software; you can redistribute it ////`
22			`//// and/or modify it under the terms of the GNU Lesser General ////`
23			`//// Public License as published by the Free Software Foundation; ////`
24			`//// either version 2.1 of the License, or (at your option) any ////`
25			`//// later version. ////`
26			`//// ////`
27			`//// This source is distributed in the hope that it will be ////`
28			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
29			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
30			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
31			`//// details. ////`
32			`//// ////`
33			`//// You should have received a copy of the GNU Lesser General ////`
34			`//// Public License along with this source; if not, download it ////`
35			`//// from http://www.opencores.org/lgpl.shtml ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//`
39			`// CVS Revision History`
40			`//`
41			`// $Log: not supported by cvs2svn $`
42			`// Revision 1.3 2006/01/19 14:07:54 maverickist`
43			`// verification is complete.`
44			`//`
45			`// Revision 1.3 2005/12/16 06:44:17 Administrator`
46			`// replaced tab with space.`
47			`// passed 9.6k length frame test.`
48			`//`
49			`// Revision 1.2 2005/12/13 12:15:38 Administrator`
50			`// no message`
51			`//`
52			`// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator`
53			`// no message`
54			`//`
55
56			`module MAC_tx_ctrl (`
57			`Reset ,`
58			`Clk ,`
59			`//CRC_gen Interface`
60			`CRC_init ,`
61			`Frame_data ,`
62			`Data_en ,`
63			`CRC_rd ,`
64			`CRC_end ,`
65			`CRC_out ,`
66			`//Ramdon_gen interfac`
67			`Random_init ,`
68			`RetryCnt ,`
69			`Random_time_meet ,`
70			`//flow control`
71			`pause_apply ,`
72			`pause_quanta_sub ,`
73			`xoff_gen ,`
74			`xoff_gen_complete ,`
75			`xon_gen ,`
76			`xon_gen_complete ,`
77			`//MAC_tx_FF`
78			`Fifo_data ,`
79			`Fifo_rd ,`
80			`Fifo_eop ,`
81			`Fifo_da ,`
82			`Fifo_rd_finish ,`
83			`Fifo_rd_retry ,`
84			`Fifo_ra ,`
85			`Fifo_data_err_empty ,`
86			`Fifo_data_err_full ,`
87			`//RMII`
88			`TxD ,`
89			`TxEn ,`
90			`CRS ,`
91			`//MAC_tx_addr_add`
92			`MAC_tx_addr_rd ,`
93			`MAC_tx_addr_data ,`
94			`MAC_tx_addr_init ,`
95			`//RMON`
96			`Tx_pkt_type_rmon ,`
97			`Tx_pkt_length_rmon ,`
98			`Tx_apply_rmon ,`
99			`Tx_pkt_err_type_rmon,`
100			`//CPU`
101			`pause_frame_send_en ,`
102			`pause_quanta_set ,`
103			`MAC_tx_add_en ,`
104			`FullDuplex ,`
105			`MaxRetry ,`
106			`IFGset`
107			`);`
108
109			`input Reset ;`
110			`input Clk ;`
111			`//CRC_gen Interface`
112			`output CRC_init ;`
113			`output [7:0] Frame_data ;`
114			`output Data_en ;`
115			`output CRC_rd ;`
116			`input CRC_end ;`
117			`input [7:0] CRC_out ;`
118			`//Ramdon_gen interface`
119			`output Random_init ;`
120			`output [3:0] RetryCnt ;`
121			`input Random_time_meet ;//levle hight indicate random time passed away`
122			`//flow control`
123			`input pause_apply ;`
124			`output pause_quanta_sub ;`
125			`input xoff_gen ;`
126			`output xoff_gen_complete ;`
127			`input xon_gen ;`
128			`output xon_gen_complete ;`
129			`//MAC_rx_FF`
130			`input [7:0] Fifo_data ;`
131			`output Fifo_rd ;`
132			`input Fifo_eop ;`
133			`input Fifo_da ;`
134			`output Fifo_rd_finish ;`
135			`output Fifo_rd_retry ;`
136			`input Fifo_ra ;`
137			`input Fifo_data_err_empty ;`
138			`input Fifo_data_err_full ;`
139			`//RMII`
140			`output [7:0] TxD ;`
141			`output TxEn ;`
142			`input CRS ;`
143			`//MAC_tx_addr_add`
144			`output MAC_tx_addr_init ;`
145			`output MAC_tx_addr_rd ;`
146			`input [7:0] MAC_tx_addr_data ;`
147			`//RMON`
148			`output [2:0] Tx_pkt_type_rmon ;`
149			`output [15:0] Tx_pkt_length_rmon ;`
150			`output Tx_apply_rmon ;`
151			`output [2:0] Tx_pkt_err_type_rmon;`
152			`//CPU`
153			`input pause_frame_send_en ;`
154			`input [15:0] pause_quanta_set ;`
155			`input MAC_tx_add_en ;`
156			`input FullDuplex ;`
157			`input [3:0] MaxRetry ;`
158			`input [5:0] IFGset ;`
159			`//******************************************************************************`
160			`//internal signals`
161			`//******************************************************************************`
162			`parameter StateIdle =4'd00;`
163			`parameter StatePreamble =4'd01;`
164			`parameter StateSFD =4'd02;`
165			`parameter StateData =4'd03;`
166			`parameter StatePause =4'd04;`
167			`parameter StatePAD =4'd05;`
168			`parameter StateFCS =4'd06;`
169			`parameter StateIFG =4'd07;`
170			`parameter StateJam =4'd08;`
171			`parameter StateBackOff =4'd09;`
172			`parameter StateJamDrop =4'd10;`
173			`parameter StateFFEmptyDrop =4'd11;`
174			`parameter StateSwitchNext =4'd12;`
175			`parameter StateDefer =4'd13;`
176			`parameter StateSendPauseFrame =4'd14;`
177
178			`reg [3:0] Current_state /synthesis syn_keep=1 /;`
179			`reg [3:0] Next_state;`
180			`reg [5:0] IFG_counter;`
181			`reg [4:0] Preamble_counter;//`
182			`reg [7:0] TxD_tmp ;`
183			`reg TxEn_tmp ;`
184			`reg [15:0] Tx_pkt_length_rmon ;`
185			`reg Tx_apply_rmon ;`
186			`reg Tx_apply_rmon_tmp ;`
187			`reg Tx_apply_rmon_tmp_pl1;`
188			`reg [2:0] Tx_pkt_err_type_rmon;`
189			`reg [3:0] RetryCnt ;`
190			`reg Random_init ;`
191			`reg Fifo_rd_finish ;`
192			`reg Fifo_rd_retry ;`
193			`reg [7:0] TxD ;`
194			`reg TxEn ;`
195			`reg CRC_init ;`
196			`reg Data_en ;`
197			`reg CRC_rd ;`
198			`reg Fifo_rd ;`
199			`reg MAC_tx_addr_rd ;`
200			`reg MAC_header_slot ;`
201			`reg MAC_header_slot_tmp ;`
202			`reg [2:0] Tx_pkt_type_rmon ;`
203			`wire Collision ;`
204			`reg MAC_tx_addr_init ;`
205			`reg Src_MAC_ptr ;`
206			`reg [7:0] IPLengthCounter ;//for pad append`
207			`reg [1:0] PADCounter ;`
208			`reg [7:0] JamCounter ;`
209			`reg PktDrpEvenPtr ;`
210			`reg [7:0] pause_counter ;`
211			`reg pause_quanta_sub ;`
212			`reg pause_frame_send_en_dl1 ;`
213			`reg [15:0] pause_quanta_set_dl1 ;`
214			`reg xoff_gen_complete ;`
215			`reg xon_gen_complete ;`
216			`//******************************************************************************`
217			`//boundery signal processing`
218			`//******************************************************************************`
219			`always @(posedge Clk or posedge Reset)`
220			`if (Reset)`
221			`begin`
222			`pause_frame_send_en_dl1 <=0;`
223			`pause_quanta_set_dl1 <=0;`
224			`end`
225			`else`
226			`begin`
227			`pause_frame_send_en_dl1 <=pause_frame_send_en ;`
228			`pause_quanta_set_dl1 <=pause_quanta_set ;`
229			`end`
230			`//******************************************************************************`
231			`//state machine`
232			`//******************************************************************************`
233			`assign Collision=TxEn&CRS;`
234
235			`always @(posedge Clk or posedge Reset)`
236			`if (Reset)`
237			`pause_counter <=0;`
238			`else if (Current_state!=StatePause)`
239			`pause_counter <=0;`
240			`else`
241			`pause_counter <=pause_counter+1;`
242
243			`always @(posedge Clk or posedge Reset)`
244			`if (Reset)`
245			`IPLengthCounter <=0;`
246			`else if (Current_state==StateDefer)`
247			`IPLengthCounter <=0;`
248			`else if (IPLengthCounter!=8'hff&&(Current_state==StateData\|\|Current_state==StateSendPauseFrame\|\|Current_state==StatePAD))`
249			`IPLengthCounter <=IPLengthCounter+1;`
250
251			`always @(posedge Clk or posedge Reset)`
252			`if (Reset)`
253			`PADCounter <=0;`
254			`else if (Current_state!=StatePAD)`
255			`PADCounter <=0;`
256			`else`
257			`PADCounter <=PADCounter+1;`
258
259			`always @(posedge Clk or posedge Reset)`
260			`if (Reset)`
261			`Current_state <=StateDefer;`
262			`else`
263			`Current_state <=Next_state;`
264
265			`always @ (*)`
266			`case (Current_state)`
267			`StateDefer:`
268			`if ((FullDuplex)\|\|(!FullDuplex&&!CRS))`
269			`Next_state=StateIFG;`
270			`else`
271			`Next_state=Current_state;`
272			`StateIFG:`
273			`if (!FullDuplex&&CRS)`
274			`Next_state=StateDefer;`
275			`else if ((FullDuplex&&IFG_counter==IFGset-4)\|\|(!FullDuplex&&!CRS&&IFG_counter==IFGset-4))//remove some additional time`
276			`Next_state=StateIdle;`
277			`else`
278			`Next_state=Current_state;`
279			`StateIdle:`
280			`if (!FullDuplex&&CRS)`
281			`Next_state=StateDefer;`
282			`else if (pause_apply)`
283			`Next_state=StatePause;`
284			`else if ((FullDuplex&&Fifo_ra)\|\|(!FullDuplex&&!CRS&&Fifo_ra)\|\|(pause_frame_send_en_dl1&&(xoff_gen\|\|xon_gen)))`
285			`Next_state=StatePreamble;`
286			`else`
287			`Next_state=Current_state;`
288			`StatePause:`
289			`if (pause_counter==512/8)`
290			`Next_state=StateDefer;`
291			`else`
292			`Next_state=Current_state;`
293			`StatePreamble:`
294			`if (!FullDuplex&&Collision)`
295			`Next_state=StateJam;`
296			`else if ((FullDuplex&&Preamble_counter==6)\|\|(!FullDuplex&&!Collision&&Preamble_counter==6))`
297			`Next_state=StateSFD;`
298			`else`
299			`Next_state=Current_state;`
300			`StateSFD:`
301			`if (!FullDuplex&&Collision)`
302			`Next_state=StateJam;`
303			`else if (pause_frame_send_en_dl1&&(xoff_gen\|\|xon_gen))`
304			`Next_state=StateSendPauseFrame;`
305			`else`
306			`Next_state=StateData;`
307			`StateSendPauseFrame:`
308			`if (IPLengthCounter==17)`
309			`Next_state=StatePAD;`
310			`else`
311			`Next_state=Current_state;`
312			`StateData:`
313			`if (!FullDuplex&&Collision)`
314			`Next_state=StateJam;`
315			`else if (Fifo_data_err_empty)`
316			`Next_state=StateFFEmptyDrop;`
317			`else if (Fifo_eop&&IPLengthCounter>=59)//IP+MAC+TYPE=60 ,start from 0`
318			`Next_state=StateFCS;`
319			`else if (Fifo_eop)`
320			`Next_state=StatePAD;`
321			`else`
322			`Next_state=StateData;`
323			`StatePAD:`
324			`if (!FullDuplex&&Collision)`
325			`Next_state=StateJam;`
326			`else if (IPLengthCounter>=59)`
327			`Next_state=StateFCS;`
328			`else`
329			`Next_state=Current_state;`
330			`StateJam:`
331			`if (RetryCnt<=MaxRetry&&JamCounter==16)`
332			`Next_state=StateBackOff;`
333			`else if (RetryCnt>MaxRetry)`
334			`Next_state=StateJamDrop;`
335			`else`
336			`Next_state=Current_state;`
337			`StateBackOff:`
338			`if (Random_time_meet)`
339			`Next_state =StateDefer;`
340			`else`
341			`Next_state =Current_state;`
342			`StateFCS:`
343			`if (!FullDuplex&&Collision)`
344			`Next_state =StateJam;`
345			`else if (CRC_end)`
346			`Next_state =StateSwitchNext;`
347			`else`
348			`Next_state =Current_state;`
349			`StateFFEmptyDrop:`
350			`if (Fifo_eop)`
351			`Next_state =StateSwitchNext;`
352			`else`
353			`Next_state =Current_state;`
354			`StateJamDrop:`
355			`if (Fifo_eop)`
356			`Next_state =StateSwitchNext;`
357			`else`
358			`Next_state =Current_state;`
359			`StateSwitchNext:`
360			`Next_state =StateDefer;`
361			`default:`
362			`Next_state =StateDefer;`
363			`endcase`
364
365
366
367			`always @ (posedge Clk or posedge Reset)`
368			`if (Reset)`
369			`JamCounter <=0;`
370			`else if (Current_state!=StateJam)`
371			`JamCounter <=0;`
372			`else if (Current_state==StateJam)`
373			`JamCounter <=JamCounter+1;`
374
375
376			`always @ (posedge Clk or posedge Reset)`
377			`if (Reset)`
378			`RetryCnt <=0;`
379			`else if (Current_state==StateSwitchNext)`
380			`RetryCnt <=0;`
381			`else if (Current_state==StateJam&&Next_state==StateBackOff)`
382			`RetryCnt <=RetryCnt + 1;`
383
384			`always @ (posedge Clk or posedge Reset)`
385			`if (Reset)`
386			`IFG_counter <=0;`
387			`else if (Current_state!=StateIFG)`
388			`IFG_counter <=0;`
389			`else`
390			`IFG_counter <=IFG_counter + 1;`
391
392			`always @ (posedge Clk or posedge Reset)`
393			`if (Reset)`
394			`Preamble_counter <=0;`
395			`else if (Current_state!=StatePreamble)`
396			`Preamble_counter <=0;`
397			`else`
398			`Preamble_counter <=Preamble_counter+ 1;`
399
400			`always @ (posedge Clk or posedge Reset)`
401			`if (Reset)`
402			`PktDrpEvenPtr <=0;`
403			`else if(Current_state==StateJamDrop\|\|Current_state==StateFFEmptyDrop)`
404			`PktDrpEvenPtr <=~PktDrpEvenPtr;`
405			`//******************************************************************************`
406			`//generate output signals`
407			`//******************************************************************************`
408			`//CRC related`
409			`always @(Current_state)`
410			`if (Current_state==StateSFD)`
411			`CRC_init =1;`
412			`else`
413			`CRC_init =0;`
414
415			`assign Frame_data=TxD_tmp;`
416
417			`always @(Current_state)`
418			`if (Current_state==StateData\|\|Current_state==StateSendPauseFrame\|\|Current_state==StatePAD)`
419			`Data_en =1;`
420			`else`
421			`Data_en =0;`
422
423			`always @(Current_state)`
424			`if (Current_state==StateFCS)`
425			`CRC_rd =1;`
426			`else`
427			`CRC_rd =0;`
428
429			`//Ramdon_gen interface`
430			`always @(Current_state or Next_state)`
431			`if (Current_state==StateJam&&Next_state==StateBackOff)`
432			`Random_init =1;`
433			`else`
434			`Random_init =0;`
435
436			`//MAC_rx_FF`
437			`//data have one cycle delay after fifo read signals`
438			`always @ (*)`
439			`if (Current_state==StateData \|\|`
440			`Current_state==StateSFD&&!(pause_frame_send_en_dl1&&(xoff_gen\|\|xon_gen)) \|\|`
441			`Current_state==StateJamDrop&&PktDrpEvenPtr\|\|`
442			`Current_state==StateFFEmptyDrop&&PktDrpEvenPtr )`
443			`Fifo_rd =1;`
444			`else`
445			`Fifo_rd =0;`
446
447			`always @ (Current_state)`
448			`if (Current_state==StateSwitchNext)`
449			`Fifo_rd_finish =1;`
450			`else`
451			`Fifo_rd_finish =0;`
452
453			`always @ (Current_state)`
454			`if (Current_state==StateJam)`
455			`Fifo_rd_retry =1;`
456			`else`
457			`Fifo_rd_retry =0;`
458			`//RMII`
459			`always @(Current_state)`
460			`if (Current_state==StatePreamble\|\|Current_state==StateSFD\|\|`
461			`Current_state==StateData\|\|Current_state==StateSendPauseFrame\|\|`
462			`Current_state==StateFCS\|\|Current_state==StatePAD\|\|Current_state==StateJam)`
463			`TxEn_tmp =1;`
464			`else`
465			`TxEn_tmp =0;`
466
467			`//gen txd data`
468			`always @(*)`
469			`case (Current_state)`
470			`StatePreamble:`
471			`TxD_tmp =8'h55;`
472			`StateSFD:`
473			`TxD_tmp =8'hd5;`
474			`StateData:`
475			`if (Src_MAC_ptr&&MAC_tx_add_en)`
476			`TxD_tmp =MAC_tx_addr_data;`
477			`else`
478			`TxD_tmp =Fifo_data;`
479			`StateSendPauseFrame:`
480			`if (Src_MAC_ptr&&MAC_tx_add_en)`
481			`TxD_tmp =MAC_tx_addr_data;`
482			`else`
483			`case (IPLengthCounter)`
484			`7'd0: TxD_tmp =8'h01;`
485			`7'd1: TxD_tmp =8'h80;`
486			`7'd2: TxD_tmp =8'hc2;`
487			`7'd3: TxD_tmp =8'h00;`
488			`7'd4: TxD_tmp =8'h00;`
489			`7'd5: TxD_tmp =8'h01;`
490			`7'd12: TxD_tmp =8'h88;//type`
491			`7'd13: TxD_tmp =8'h08;//`
492			`7'd14: TxD_tmp =8'h00;//opcode`
493			`7'd15: TxD_tmp =8'h01;`
494			`7'd16: TxD_tmp =xon_gen?8'b0:pause_quanta_set_dl1[15:8];`
495			`7'd17: TxD_tmp =xon_gen?8'b0:pause_quanta_set_dl1[7:0];`
496			`// 7'd60: TxD_tmp =8'h26;`
497			`// 7'd61: TxD_tmp =8'h6b;`
498			`// 7'd62: TxD_tmp =8'hae;`
499			`// 7'd63: TxD_tmp =8'h0a;`
500			`default:TxD_tmp =0;`
501			`endcase`
502
503			`StatePAD:`
504			`TxD_tmp =8'h00;`
505			`StateJam:`
506			`TxD_tmp =8'h01; //jam sequence`
507			`StateFCS:`
508			`TxD_tmp =CRC_out;`
509			`default:`
510			`TxD_tmp =2'b0;`
511			`endcase`
512			`always @ (posedge Clk or posedge Reset)`
513			`if (Reset)`
514			`begin`
515			`TxD <=0;`
516			`TxEn <=0;`
517			`end`
518			`else`
519			`begin`
520			`TxD <=TxD_tmp;`
521			`TxEn <=TxEn_tmp;`
522			`end`
523			`//RMON`
524
525
526			`always @ (posedge Clk or posedge Reset)`
527			`if (Reset)`
528			`Tx_pkt_length_rmon <=0;`
529			`else if (Current_state==StateSFD)`
530			`Tx_pkt_length_rmon <=0;`
531			`else if (Current_state==StateData\|\|Current_state==StateSendPauseFrame\|\|Current_state==StatePAD\|\|Current_state==StateFCS)`
532			`Tx_pkt_length_rmon <=Tx_pkt_length_rmon+1;`
533
534			`always @ (posedge Clk or posedge Reset)`
535			`if (Reset)`
536			`Tx_apply_rmon_tmp <=0;`
537			`else if ((Fifo_eop&&Current_state==StateJamDrop)\|\|`
538			`(Fifo_eop&&Current_state==StateFFEmptyDrop)\|\|`
539			`CRC_end)`
540			`Tx_apply_rmon_tmp <=1;`
541			`else`
542			`Tx_apply_rmon_tmp <=0;`
543
544			`always @ (posedge Clk or posedge Reset)`
545			`if (Reset)`
546			`Tx_apply_rmon_tmp_pl1 <=0;`
547			`else`
548			`Tx_apply_rmon_tmp_pl1 <=Tx_apply_rmon_tmp;`
549
550			`always @ (posedge Clk or posedge Reset)`
551			`if (Reset)`
552			`Tx_apply_rmon <=0;`
553			`else if ((Fifo_eop&&Current_state==StateJamDrop)\|\|`
554			`(Fifo_eop&&Current_state==StateFFEmptyDrop)\|\|`
555			`CRC_end)`
556			`Tx_apply_rmon <=1;`
557			`else if (Tx_apply_rmon_tmp_pl1)`
558			`Tx_apply_rmon <=0;`
559
560			`always @ (posedge Clk or posedge Reset)`
561			`if (Reset)`
562			`Tx_pkt_err_type_rmon <=0;`
563			`else if(Fifo_eop&&Current_state==StateJamDrop)`
564			`Tx_pkt_err_type_rmon <=3'b001;//`
565			`else if(Fifo_eop&&Current_state==StateFFEmptyDrop)`
566			`Tx_pkt_err_type_rmon <=3'b010;//underflow`
567			`else if(Fifo_eop&&Fifo_data_err_full)`
568			`Tx_pkt_err_type_rmon <=3'b011;//overflow`
569			`else if(CRC_end)`
570			`Tx_pkt_err_type_rmon <=3'b100;//normal`
571
572			`always @ (posedge Clk or posedge Reset)`
573			`if (Reset)`
574			`MAC_header_slot_tmp <=0;`
575			`else if(Current_state==StateSFD&&Next_state==StateData)`
576			`MAC_header_slot_tmp <=1;`
577			`else`
578			`MAC_header_slot_tmp <=0;`
579
580			`always @ (posedge Clk or posedge Reset)`
581			`if (Reset)`
582			`MAC_header_slot <=0;`
583			`else`
584			`MAC_header_slot <=MAC_header_slot_tmp;`
585
586			`always @ (posedge Clk or posedge Reset)`
587			`if (Reset)`
588			`Tx_pkt_type_rmon <=0;`
589			`else if (Current_state==StateSendPauseFrame)`
590			`Tx_pkt_type_rmon <=3'b100;`
591			`else if(MAC_header_slot)`
592			`Tx_pkt_type_rmon <={1'b0,TxD[7:6]};`
593
594
595			`always @(Tx_pkt_length_rmon)`
596			`if (Tx_pkt_length_rmon>=6&&Tx_pkt_length_rmon<=11)`
597			`Src_MAC_ptr =1;`
598			`else`
599			`Src_MAC_ptr =0;`
600
601			`//MAC_tx_addr_add`
602			`always @ (posedge Clk or posedge Reset)`
603			`if (Reset)`
604			`MAC_tx_addr_rd <=0;`
605			`else if ((Tx_pkt_length_rmon>=4&&Tx_pkt_length_rmon<=9)&&(MAC_tx_add_en\|\|Current_state==StateSendPauseFrame))`
606			`MAC_tx_addr_rd <=1;`
607			`else`
608			`MAC_tx_addr_rd <=0;`
609
610			`always @ (Tx_pkt_length_rmon or Fifo_rd)`
611			`if ((Tx_pkt_length_rmon==3)&&Fifo_rd)`
612			`MAC_tx_addr_init=1;`
613			`else`
614			`MAC_tx_addr_init=0;`
615
616			`//flow control`
617			`always @ (posedge Clk or posedge Reset)`
618			`if (Reset)`
619			`pause_quanta_sub <=0;`
620			`else if(pause_counter==512/8)`
621			`pause_quanta_sub <=1;`
622			`else`
623			`pause_quanta_sub <=0;`
624
625
626			`always @ (posedge Clk or posedge Reset)`
627			`if (Reset)`
628			`xoff_gen_complete <=0;`
629			`else if(Current_state==StateDefer&&xoff_gen)`
630			`xoff_gen_complete <=1;`
631			`else`
632			`xoff_gen_complete <=0;`
633
634
635			`always @ (posedge Clk or posedge Reset)`
636			`if (Reset)`
637			`xon_gen_complete <=0;`
638			`else if(Current_state==StateDefer&&xon_gen)`
639			`xon_gen_complete <=1;`
640			`else`
641			`xon_gen_complete <=0;`
642
643			`endmodule`