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[/] [sgmii/] [trunk/] [build/] [OpenCore_MAC/] [Phy_int.v] - Blame information for rev 26

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Phy_int.v                                                   ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
////                                                              ////
////  Author(s):                                                  ////
////      - Jon Gao (gaojon@yahoo.com)                            ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//                                                                    
// CVS Revision History                                               
//                                                                    
// $Log: not supported by cvs2svn $
// Revision 1.3  2005/12/16 06:44:14  Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.2  2005/12/13 12:15:36  Administrator
// no message
//
// Revision 1.1.1.1  2005/12/13 01:51:44  Administrator
// no message
// 
// 2011/04/01 Jeff Changes #1 
 
module Phy_int (
Reset               ,
MAC_rx_clk          ,
MAC_tx_clk          ,
//Rx interface      ,
MCrs_dv             ,
MRxD                ,
MRxErr              ,
//Tx interface      ,
MTxD                ,
MTxEn               ,
MCRS                ,
//Phy interface     ,
Tx_er               ,
Tx_en               ,
Txd                 ,
Rx_er               ,
Rx_dv               ,
Rxd                 ,
Crs                 ,
Col                 ,
//host interface    ,
Line_loop_en        ,
Speed
 
);
input           Reset               ;
input           MAC_rx_clk          ;
input           MAC_tx_clk          ;
                //Rx interface
output          MCrs_dv             ;
output  [7:0]   MRxD                ;
output          MRxErr              ;
                //Tx interface
input   [7:0]   MTxD                ;
input           MTxEn               ;
output          MCRS                ;
                //Phy interface
output          Tx_er               ;
output          Tx_en               ;
output  [7:0]   Txd                 ;
input           Rx_er               ;
input           Rx_dv               ;
input   [7:0]   Rxd                 ;
input           Crs                 ;
input           Col                 ;
                //host interface
input           Line_loop_en        ;
input   [2:0]   Speed               ;
//******************************************************************************
//internal signals                                                              
//******************************************************************************
reg     [7:0]   MTxD_dl1            ;
reg             MTxEn_dl1           ;
reg             Tx_odd_data_ptr     ;
reg             Rx_odd_data_ptr     ;
reg             Tx_en               ;
reg     [7:0]   Txd                 ;
reg             MCrs_dv             ;
reg     [7:0]   MRxD                ;
reg             Rx_er_dl1           ;
reg                              Rx_er_dl3                              ;
reg                              Rx_er_dl2                              ;
reg             Rx_dv_dl1           ;
reg             Rx_dv_dl2           ;
reg     [7:0]   Rxd_dl1             ;
reg     [7:0]   Rxd_dl2             ;
reg             Crs_dl1             ;
reg             Col_dl1             ;
//******************************************************************************
//Tx control                                                              
//******************************************************************************
//reg boundery signals
always @ (posedge MAC_tx_clk or posedge Reset)
    if (Reset)
        begin
        MTxD_dl1            <=0;
        MTxEn_dl1           <=0;
        end
    else
        begin
        MTxD_dl1            <=MTxD  ;
        MTxEn_dl1           <=MTxEn ;
        end
 
always @ (posedge MAC_tx_clk or posedge Reset)
    if (Reset)
        Tx_odd_data_ptr     <=0;
    else if (!MTxD_dl1)
        Tx_odd_data_ptr     <=0;
    else
        Tx_odd_data_ptr     <=!Tx_odd_data_ptr;
 
 
always @ (posedge MAC_tx_clk or posedge Reset)
    if (Reset)
        Txd                 <=0;
    else if(Speed[2]&&MTxEn_dl1)
        Txd                 <=MTxD_dl1;
    else if(MTxEn_dl1&&!Tx_odd_data_ptr)
        Txd                 <={4'b0,MTxD_dl1[3:0]};
    else if(MTxEn_dl1&&Tx_odd_data_ptr)
        Txd                 <={4'b0,MTxD_dl1[7:4]};
    else
        Txd                 <=0;
 
always @ (posedge MAC_tx_clk or posedge Reset)
    if (Reset)
        Tx_en               <=0;
    else if(MTxEn_dl1)
        Tx_en               <=1;
    else
        Tx_en               <=0;
 
assign Tx_er=0;
 
//******************************************************************************
//Rx control                                                              
//******************************************************************************
//reg boundery signals
always @ (posedge MAC_rx_clk or posedge Reset)
    if (Reset)
        begin
        Rx_er_dl1           <=0;
        Rx_dv_dl1           <=0;
        Rx_dv_dl2           <=0 ;
        Rxd_dl1             <=0;
        Rxd_dl2             <=0;
        Crs_dl1             <=0;
        Col_dl1             <=0;
        end
    else
        begin
        Rx_er_dl1           <=Rx_er     ;
                  //Jeff Changes #1
                  Rx_er_dl2           <=Rx_er_dl1;
                  Rx_er_dl3           <=Rx_er_dl2&Rx_dv_dl2;
        Rx_dv_dl1           <=Rx_dv     ;
        Rx_dv_dl2           <=Rx_dv_dl1 ;
        Rxd_dl1             <=Rxd       ;
        Rxd_dl2             <=Rxd_dl1   ;
        Crs_dl1             <=Crs       ;
        Col_dl1             <=Col       ;
        end
 
//assign MRxErr   =Rx_er_dl1      ;
assign MRxErr    = Rx_er_dl3;
assign MCRS     =Crs_dl1        ;
 
always @ (posedge MAC_rx_clk or posedge Reset)
    if (Reset)
        MCrs_dv         <=0;
    else if(Line_loop_en)
        MCrs_dv         <=Tx_en;
    else if(Rx_dv_dl2)
        MCrs_dv         <=1;
    else
        MCrs_dv         <=0;
 
always @ (posedge MAC_rx_clk or posedge Reset)
    if (Reset)
        Rx_odd_data_ptr     <=0;
    else if (!Rx_dv_dl1)
        Rx_odd_data_ptr     <=0;
    else
        Rx_odd_data_ptr     <=!Rx_odd_data_ptr;
 
always @ (posedge MAC_rx_clk or posedge Reset)
    if (Reset)
        MRxD            <=0;
    else if(Line_loop_en)
        MRxD            <=Txd;
    else if(Speed[2]&&Rx_dv_dl2)
        MRxD            <=Rxd_dl2;
    else if(Rx_dv_dl1&&Rx_odd_data_ptr)
        MRxD            <={Rxd_dl1[3:0],Rxd_dl2[3:0]};
 
endmodule

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Subversion Repositories sgmii

[/] [sgmii/] [trunk/] [build/] [OpenCore_MAC/] [Phy_int.v] - Blame information for rev 26

Line No.	Rev	Author	Line
1	26	jefflieu	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Phy_int.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Jon Gao (gaojon@yahoo.com) ////`
10			`//// ////`
11			`//// ////`
12			`//////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Authors ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer. ////`
20			`//// ////`
21			`//// This source file is free software; you can redistribute it ////`
22			`//// and/or modify it under the terms of the GNU Lesser General ////`
23			`//// Public License as published by the Free Software Foundation; ////`
24			`//// either version 2.1 of the License, or (at your option) any ////`
25			`//// later version. ////`
26			`//// ////`
27			`//// This source is distributed in the hope that it will be ////`
28			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
29			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
30			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
31			`//// details. ////`
32			`//// ////`
33			`//// You should have received a copy of the GNU Lesser General ////`
34			`//// Public License along with this source; if not, download it ////`
35			`//// from http://www.opencores.org/lgpl.shtml ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//`
39			`// CVS Revision History`
40			`//`
41			`// $Log: not supported by cvs2svn $`
42			`// Revision 1.3 2005/12/16 06:44:14 Administrator`
43			`// replaced tab with space.`
44			`// passed 9.6k length frame test.`
45			`//`
46			`// Revision 1.2 2005/12/13 12:15:36 Administrator`
47			`// no message`
48			`//`
49			`// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator`
50			`// no message`
51			`//`
52			`// 2011/04/01 Jeff Changes #1`
53
54			`module Phy_int (`
55			`Reset ,`
56			`MAC_rx_clk ,`
57			`MAC_tx_clk ,`
58			`//Rx interface ,`
59			`MCrs_dv ,`
60			`MRxD ,`
61			`MRxErr ,`
62			`//Tx interface ,`
63			`MTxD ,`
64			`MTxEn ,`
65			`MCRS ,`
66			`//Phy interface ,`
67			`Tx_er ,`
68			`Tx_en ,`
69			`Txd ,`
70			`Rx_er ,`
71			`Rx_dv ,`
72			`Rxd ,`
73			`Crs ,`
74			`Col ,`
75			`//host interface ,`
76			`Line_loop_en ,`
77			`Speed`
78
79			`);`
80			`input Reset ;`
81			`input MAC_rx_clk ;`
82			`input MAC_tx_clk ;`
83			`//Rx interface`
84			`output MCrs_dv ;`
85			`output [7:0] MRxD ;`
86			`output MRxErr ;`
87			`//Tx interface`
88			`input [7:0] MTxD ;`
89			`input MTxEn ;`
90			`output MCRS ;`
91			`//Phy interface`
92			`output Tx_er ;`
93			`output Tx_en ;`
94			`output [7:0] Txd ;`
95			`input Rx_er ;`
96			`input Rx_dv ;`
97			`input [7:0] Rxd ;`
98			`input Crs ;`
99			`input Col ;`
100			`//host interface`
101			`input Line_loop_en ;`
102			`input [2:0] Speed ;`
103			`//******************************************************************************`
104			`//internal signals`
105			`//******************************************************************************`
106			`reg [7:0] MTxD_dl1 ;`
107			`reg MTxEn_dl1 ;`
108			`reg Tx_odd_data_ptr ;`
109			`reg Rx_odd_data_ptr ;`
110			`reg Tx_en ;`
111			`reg [7:0] Txd ;`
112			`reg MCrs_dv ;`
113			`reg [7:0] MRxD ;`
114			`reg Rx_er_dl1 ;`
115			`reg Rx_er_dl3 ;`
116			`reg Rx_er_dl2 ;`
117			`reg Rx_dv_dl1 ;`
118			`reg Rx_dv_dl2 ;`
119			`reg [7:0] Rxd_dl1 ;`
120			`reg [7:0] Rxd_dl2 ;`
121			`reg Crs_dl1 ;`
122			`reg Col_dl1 ;`
123			`//******************************************************************************`
124			`//Tx control`
125			`//******************************************************************************`
126			`//reg boundery signals`
127			`always @ (posedge MAC_tx_clk or posedge Reset)`
128			`if (Reset)`
129			`begin`
130			`MTxD_dl1 <=0;`
131			`MTxEn_dl1 <=0;`
132			`end`
133			`else`
134			`begin`
135			`MTxD_dl1 <=MTxD ;`
136			`MTxEn_dl1 <=MTxEn ;`
137			`end`
138
139			`always @ (posedge MAC_tx_clk or posedge Reset)`
140			`if (Reset)`
141			`Tx_odd_data_ptr <=0;`
142			`else if (!MTxD_dl1)`
143			`Tx_odd_data_ptr <=0;`
144			`else`
145			`Tx_odd_data_ptr <=!Tx_odd_data_ptr;`
146
147
148			`always @ (posedge MAC_tx_clk or posedge Reset)`
149			`if (Reset)`
150			`Txd <=0;`
151			`else if(Speed[2]&&MTxEn_dl1)`
152			`Txd <=MTxD_dl1;`
153			`else if(MTxEn_dl1&&!Tx_odd_data_ptr)`
154			`Txd <={4'b0,MTxD_dl1[3:0]};`
155			`else if(MTxEn_dl1&&Tx_odd_data_ptr)`
156			`Txd <={4'b0,MTxD_dl1[7:4]};`
157			`else`
158			`Txd <=0;`
159
160			`always @ (posedge MAC_tx_clk or posedge Reset)`
161			`if (Reset)`
162			`Tx_en <=0;`
163			`else if(MTxEn_dl1)`
164			`Tx_en <=1;`
165			`else`
166			`Tx_en <=0;`
167
168			`assign Tx_er=0;`
169
170			`//******************************************************************************`
171			`//Rx control`
172			`//******************************************************************************`
173			`//reg boundery signals`
174			`always @ (posedge MAC_rx_clk or posedge Reset)`
175			`if (Reset)`
176			`begin`
177			`Rx_er_dl1 <=0;`
178			`Rx_dv_dl1 <=0;`
179			`Rx_dv_dl2 <=0 ;`
180			`Rxd_dl1 <=0;`
181			`Rxd_dl2 <=0;`
182			`Crs_dl1 <=0;`
183			`Col_dl1 <=0;`
184			`end`
185			`else`
186			`begin`
187			`Rx_er_dl1 <=Rx_er ;`
188			`//Jeff Changes #1`
189			`Rx_er_dl2 <=Rx_er_dl1;`
190			`Rx_er_dl3 <=Rx_er_dl2&Rx_dv_dl2;`
191			`Rx_dv_dl1 <=Rx_dv ;`
192			`Rx_dv_dl2 <=Rx_dv_dl1 ;`
193			`Rxd_dl1 <=Rxd ;`
194			`Rxd_dl2 <=Rxd_dl1 ;`
195			`Crs_dl1 <=Crs ;`
196			`Col_dl1 <=Col ;`
197			`end`
198
199			`//assign MRxErr =Rx_er_dl1 ;`
200			`assign MRxErr = Rx_er_dl3;`
201			`assign MCRS =Crs_dl1 ;`
202
203			`always @ (posedge MAC_rx_clk or posedge Reset)`
204			`if (Reset)`
205			`MCrs_dv <=0;`
206			`else if(Line_loop_en)`
207			`MCrs_dv <=Tx_en;`
208			`else if(Rx_dv_dl2)`
209			`MCrs_dv <=1;`
210			`else`
211			`MCrs_dv <=0;`
212
213			`always @ (posedge MAC_rx_clk or posedge Reset)`
214			`if (Reset)`
215			`Rx_odd_data_ptr <=0;`
216			`else if (!Rx_dv_dl1)`
217			`Rx_odd_data_ptr <=0;`
218			`else`
219			`Rx_odd_data_ptr <=!Rx_odd_data_ptr;`
220
221			`always @ (posedge MAC_rx_clk or posedge Reset)`
222			`if (Reset)`
223			`MRxD <=0;`
224			`else if(Line_loop_en)`
225			`MRxD <=Txd;`
226			`else if(Speed[2]&&Rx_dv_dl2)`
227			`MRxD <=Rxd_dl2;`
228			`else if(Rx_dv_dl1&&Rx_odd_data_ptr)`
229			`MRxD <={Rxd_dl1[3:0],Rxd_dl2[3:0]};`
230
231			`endmodule`