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jefflieu |
// megafunction wizard: %ALTDDIO_IN%VBB%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: altddio_in
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// ============================================================
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// File Name: DDR_I.v
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// Megafunction Name(s):
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// altddio_in
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//
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// Simulation Library Files(s):
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// altera_mf
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 9.0 Build 235 06/17/2009 SP 2 SJ Full Version
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// ************************************************************
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//Copyright (C) 1991-2009 Altera Corporation
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//Your use of Altera Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Altera Program License
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//Subscription Agreement, Altera MegaCore Function License
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//Agreement, or other applicable license agreement, including,
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//without limitation, that your use is for the sole purpose of
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//programming logic devices manufactured by Altera and sold by
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//Altera or its authorized distributors. Please refer to the
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//applicable agreement for further details.
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module DDR_I (
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datain,
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inclock,
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dataout_h,
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dataout_l);
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input [4:0] datain;
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input inclock;
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output [4:0] dataout_h;
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output [4:0] dataout_l;
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
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// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
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// Retrieval info: PRIVATE: INVERT_INPUT_CLOCKS NUMERIC "0"
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// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
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// Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: WIDTH NUMERIC "5"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
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// Retrieval info: CONSTANT: INVERT_INPUT_CLOCKS STRING "OFF"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_in"
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// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
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// Retrieval info: CONSTANT: WIDTH NUMERIC "5"
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// Retrieval info: USED_PORT: datain 0 0 5 0 INPUT NODEFVAL datain[4..0]
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// Retrieval info: USED_PORT: dataout_h 0 0 5 0 OUTPUT NODEFVAL dataout_h[4..0]
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// Retrieval info: USED_PORT: dataout_l 0 0 5 0 OUTPUT NODEFVAL dataout_l[4..0]
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// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL inclock
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// Retrieval info: CONNECT: @datain 0 0 5 0 datain 0 0 5 0
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// Retrieval info: CONNECT: dataout_h 0 0 5 0 @dataout_h 0 0 5 0
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// Retrieval info: CONNECT: dataout_l 0 0 5 0 @dataout_l 0 0 5 0
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// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: GEN_FILE: TYPE_NORMAL DDR_I.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL DDR_I.ppf TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL DDR_I.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL DDR_I.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL DDR_I.bsf FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL DDR_I_inst.v FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL DDR_I_bb.v TRUE
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// Retrieval info: LIB_FILE: altera_mf
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