OpenCores
URL https://opencores.org/ocsvn/sgmii/sgmii/trunk

Subversion Repositories sgmii

[/] [sgmii/] [trunk/] [build/] [OpenCore_MAC/] [TECH/] [altera/] [GMII2RGMII.v.bak] - Blame information for rev 26

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 26 jefflieu
`timescale 1ns / 1ps
2
//////////////////////////////////////////////////////////////////////////////////
3
// Company:
4
// Engineer:
5
//
6
// Create Date:    14:57:12 06/01/2010
7
// Design Name:
8
// Module Name:    GMII2RGMII
9
// Project Name:
10
// Target Devices:
11
// Tool versions:
12
// Description:
13
//
14
// Dependencies:
15
//
16
// Revision:
17
// Revision 0.01 - File Created
18
// Additional Comments:
19
//
20
//////////////////////////////////////////////////////////////////////////////////
21
module GMII2RGMII(
22
    input [7:0] TxD,
23
    input TxClk,
24
    input TxEn,
25
    input TxErr,
26
    input TxClk90,
27
    output [3:0] RGMII_TxD,
28
    output RGMII_TxCtl,
29
    output RGMII_TxClk,
30
         input ClkEN,
31
         input rst
32
    );
33
 
34
        reg [3:0] TxHighNib;
35
        reg [3:0] TxHighNib2;
36
        reg [3:0] TxLowNib;
37
        reg     TX_EN1;
38
        wire    EN_xor_ERR1;
39
        reg     EN_xor_ERR2;
40
        reg     EN_xor_ERR3;
41
 
42
        wire    DDR_R;
43
        reg     DDR_S;
44
        wire    DDR_CE;
45
 
46
        wire [5:0] dataout;
47
        wire [5:0] datain_h;
48
        wire [5:0] datain_l;
49
 
50
 
51
        initial
52
        begin
53
        DDR_S <= 0;
54
        end
55
 
56
        assign DDR_CE = ClkEN;
57
        assign DDR_R = rst;
58
 
59
        always@(posedge(TxClk))
60
        begin
61
                        TxLowNib <= TxD[3:0];
62
                        TxHighNib <= TxD[7:4];
63
        end
64
 
65
        always@(posedge(TxClk))
66
        begin
67
                TX_EN1 <= TxEn;
68
                EN_xor_ERR2 <= EN_xor_ERR1;
69
        end
70
 
71
        assign EN_xor_ERR1 = TxEn^TxErr;
72
 
73
        assign datain_h = {1'b1,TX_EN1,TxLowNib};
74
        assign datain_l = {1'b0,EN_xor_ERR2,TxHighNib};
75
 
76
        DDR_O ODDR_inst(        .datain_h       (datain_h),
77
                                                .datain_l       (datain_l),
78
                                                .outclock       (TxClk),
79
                                                .dataout        (dataout));
80
 
81
        assign RGMII_TxD = dataout[3:0];
82
        assign RGMII_TxCtl = dataout[4];
83
        assign RGMII_TxClk = TxClk90;
84
 
85
        DDR_O_CLK ODDRCLK_inst( .datain_h       (1'b1),
86
                                                .datain_l       (1'b0),
87
                                                .outclock       (TxClk90),
88
                                                .dataout        (RGMII_TxClk));
89
 
90
 
91
 
92
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.