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[/] [sgmii/] [trunk/] [build/] [OpenCore_MAC/] [TECH/] [altera/] [clk_buf.v] - Blame information for rev 26

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1 26 jefflieu 
// megafunction wizard: %ALTCLKCTRL%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: altclkctrl
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// ============================================================
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// File Name: clk_buf.v
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// Megafunction Name(s):
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//                      altclkctrl
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//
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// Simulation Library Files(s):
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//                      arriav
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 12.0 Build 263 08/02/2012 SP 2.dp9 SJ Full Version
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// ************************************************************
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//Copyright (C) 1991-2012 Altera Corporation
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//Your use of Altera Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Altera Program License
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//Subscription Agreement, Altera MegaCore Function License
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//Agreement, or other applicable license agreement, including,
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//without limitation, that your use is for the sole purpose of
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//programming logic devices manufactured by Altera and sold by
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//Altera or its authorized distributors.  Please refer to the
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//applicable agreement for further details.
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//altclkctrl CBX_AUTO_BLACKBOX="ALL" CLOCK_TYPE="AUTO" DEVICE_FAMILY="Arria V" ENA_REGISTER_MODE="always enabled" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" ena inclk outclk
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//VERSION_BEGIN 12.0SP2 cbx_altclkbuf 2012:10:19:19:48:16:SJ cbx_cycloneii 2012:10:19:19:48:16:SJ cbx_lpm_add_sub 2012:10:19:19:48:16:SJ cbx_lpm_compare 2012:10:19:19:48:16:SJ cbx_lpm_decode 2012:10:19:19:48:16:SJ cbx_lpm_mux 2012:10:19:19:48:16:SJ cbx_mgl 2012:10:19:19:50:12:SJ cbx_stratix 2012:10:19:19:48:17:SJ cbx_stratixii 2012:10:19:19:48:17:SJ cbx_stratixiii 2012:10:19:19:48:17:SJ cbx_stratixv 2012:10:19:19:48:17:SJ  VERSION_END
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// synthesis VERILOG_INPUT_VERSION VERILOG_2001
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// altera message_off 10463
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//synthesis_resources = arriav_clkena 1
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//synopsys translate_off
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`timescale 1 ps / 1 ps
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//synopsys translate_on
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module  clk_buf_altclkctrl_7mg
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        (
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        ena,
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        inclk,
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        outclk) ;
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        input   ena;
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        input   [3:0]  inclk;
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        output   outclk;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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        tri1   ena;
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        tri0   [3:0]  inclk;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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        wire  wire_sd1_outclk;
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        wire [1:0]  clkselect;
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        arriav_clkena   sd1
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        (
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        .ena(ena),
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        .enaout(),
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        .inclk(inclk[0]),
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        .outclk(wire_sd1_outclk));
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        defparam
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                sd1.clock_type = "Auto",
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                sd1.ena_register_mode = "always enabled",
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                sd1.lpm_type = "arriav_clkena";
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        assign
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                clkselect = {2{1'b0}},
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                outclk = wire_sd1_outclk;
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endmodule //clk_buf_altclkctrl_7mg
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//VALID FILE
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module clk_buf (
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        inclk,
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        outclk);
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        input     inclk;
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        output    outclk;
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        wire  sub_wire0;
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        wire  sub_wire1 = 1'h1;
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        wire [2:0] sub_wire4 = 3'h0;
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        wire  outclk = sub_wire0;
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        wire  sub_wire2 = inclk;
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        wire [3:0] sub_wire3 = {sub_wire4, sub_wire2};
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        clk_buf_altclkctrl_7mg  clk_buf_altclkctrl_7mg_component (
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                                .ena (sub_wire1),
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                                .inclk (sub_wire3),
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                                .outclk (sub_wire0));
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria V"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: clock_inputs NUMERIC "1"
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// Retrieval info: CONSTANT: ENA_REGISTER_MODE STRING "always enabled"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria V"
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// Retrieval info: CONSTANT: USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION STRING "OFF"
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// Retrieval info: CONSTANT: clock_type STRING "AUTO"
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// Retrieval info: USED_PORT: inclk 0 0 0 0 INPUT NODEFVAL "inclk"
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// Retrieval info: USED_PORT: outclk 0 0 0 0 OUTPUT NODEFVAL "outclk"
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// Retrieval info: CONNECT: @ena 0 0 0 0 VCC 0 0 0 0
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// Retrieval info: CONNECT: @inclk 0 0 3 1 GND 0 0 3 0
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// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk 0 0 0 0
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// Retrieval info: CONNECT: outclk 0 0 0 0 @outclk 0 0 0 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL clk_buf.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL clk_buf.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL clk_buf.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL clk_buf.bsf FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL clk_buf_inst.v FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL clk_buf_bb.v FALSE
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// Retrieval info: LIB_FILE: arriav

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