OpenCores
URL https://opencores.org/ocsvn/sgmii/sgmii/trunk

Subversion Repositories sgmii

[/] [sgmii/] [trunk/] [build/] [OpenCore_MAC/] [TECH/] [altera/] [clk_mux.v] - Blame information for rev 26

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 26 jefflieu 
// megafunction wizard: %ALTCLKCTRL%
2 
// GENERATION: STANDARD
3 
// VERSION: WM1.0
4 
// MODULE: altclkctrl
5 
 
6 
// ============================================================
7 
// File Name: clk_mux.v
8 
// Megafunction Name(s):
9 
//                      altclkctrl
10 
//
11 
// Simulation Library Files(s):
12 
//                      arriaii
13 
// ============================================================
14 
// ************************************************************
15 
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
16 
//
17 
// 9.0 Build 235 06/17/2009 SP 2 SJ Full Version
18 
// ************************************************************
19 
 
20 
 
21 
//Copyright (C) 1991-2009 Altera Corporation
22 
//Your use of Altera Corporation's design tools, logic functions
23 
//and other software and tools, and its AMPP partner logic
24 
//functions, and any output files from any of the foregoing
25 
//(including device programming or simulation files), and any
26 
//associated documentation or information are expressly subject
27 
//to the terms and conditions of the Altera Program License
28 
//Subscription Agreement, Altera MegaCore Function License
29 
//Agreement, or other applicable license agreement, including,
30 
//without limitation, that your use is for the sole purpose of
31 
//programming logic devices manufactured by Altera and sold by
32 
//Altera or its authorized distributors.  Please refer to the
33 
//applicable agreement for further details.
34 
 
35 
 
36 
//altclkctrl CBX_AUTO_BLACKBOX="ALL" CLOCK_TYPE="AUTO" DEVICE_FAMILY="Arria II GX" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" clkselect ena inclk outclk
37 
//VERSION_BEGIN 9.0SP2 cbx_altclkbuf 2008:07:07:05:29:15:SJ cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_add_sub 2009:05:07:10:25:28:SJ cbx_lpm_compare 2009:02:03:01:43:16:SJ cbx_lpm_decode 2008:05:19:10:39:27:SJ cbx_lpm_mux 2009:03:31:01:01:28:SJ cbx_mgl 2009:02:26:16:06:21:SJ cbx_stratix 2008:09:18:16:08:35:SJ cbx_stratixii 2008:11:14:16:08:42:SJ cbx_stratixiii 2009:05:12:13:36:56:SJ  VERSION_END
38 
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
39 
// altera message_off 10463
40 
 
41 
 
42 
//synthesis_resources = clkctrl 1
43 
//synopsys translate_off
44 
`timescale 1 ps / 1 ps
45 
//synopsys translate_on
46 
module  clk_mux_altclkctrl_3ne
47 
        (
48 
        clkselect,
49 
        ena,
50 
        inclk,
51 
        outclk) ;
52 
        input   [1:0]  clkselect;
53 
        input   ena;
54 
        input   [3:0]  inclk;
55 
        output   outclk;
56 
`ifndef ALTERA_RESERVED_QIS
57 
// synopsys translate_off
58 
`endif
59 
        tri0   [1:0]  clkselect;
60 
        tri1   ena;
61 
        tri0   [3:0]  inclk;
62 
`ifndef ALTERA_RESERVED_QIS
63 
// synopsys translate_on
64 
`endif
65 
 
66 
        wire  wire_sd1_outclk;
67 
        wire  wire_sd2_outclk;
68 
        wire  [1:0]  clkselect_wire;
69 
        wire  [3:0]  inclk_wire;
70 
 
71 
        arriaii_clkena   sd1
72 
        (
73 
        .ena(ena),
74 
        .enaout(),
75 
        .inclk(wire_sd2_outclk),
76 
        .outclk(wire_sd1_outclk)
77 
        // synopsys translate_off
78 
        ,
79 
        .devclrn(1'b1),
80 
        .devpor(1'b1)
81 
        // synopsys translate_on
82 
        );
83 
        defparam
84 
                sd1.clock_type = "AUTO",
85 
                sd1.ena_register_mode = "falling edge",
86 
                sd1.lpm_type = "arriaii_clkena";
87 
        arriaii_clkselect   sd2
88 
        (
89 
        .clkselect(clkselect_wire),
90 
        .inclk(inclk_wire),
91 
        .outclk(wire_sd2_outclk));
92 
        assign
93 
                clkselect_wire = {clkselect},
94 
                inclk_wire = {inclk},
95 
                outclk = wire_sd1_outclk;
96 
endmodule //clk_mux_altclkctrl_3ne
97 
//VALID FILE
98 
 
99 
 
100 
// synopsys translate_off
101 
`timescale 1 ps / 1 ps
102 
// synopsys translate_on
103 
module clk_mux (
104 
        clkselect,
105 
        inclk0x,
106 
        inclk1x,
107 
        outclk);
108 
 
109 
        input     clkselect;
110 
        input     inclk0x;
111 
        input     inclk1x;
112 
        output    outclk;
113 
`ifndef ALTERA_RESERVED_QIS
114 
// synopsys translate_off
115 
`endif
116 
        tri0      clkselect;
117 
`ifndef ALTERA_RESERVED_QIS
118 
// synopsys translate_on
119 
`endif
120 
 
121 
        wire  sub_wire0;
122 
        wire  sub_wire1 = 1'h1;
123 
        wire [1:0] sub_wire5 = 2'h0;
124 
        wire [0:0] sub_wire8 = 1'h0;
125 
        wire  sub_wire4 = inclk1x;
126 
        wire  outclk = sub_wire0;
127 
        wire  sub_wire2 = inclk0x;
128 
        wire [3:0] sub_wire3 = {sub_wire5, sub_wire4, sub_wire2};
129 
        wire  sub_wire6 = clkselect;
130 
        wire [1:0] sub_wire7 = {sub_wire8, sub_wire6};
131 
 
132 
        clk_mux_altclkctrl_3ne  clk_mux_altclkctrl_3ne_component (
133 
                                .ena (sub_wire1),
134 
                                .inclk (sub_wire3),
135 
                                .clkselect (sub_wire7),
136 
                                .outclk (sub_wire0));
137 
 
138 
endmodule
139 
 
140 
// ============================================================
141 
// CNX file retrieval info
142 
// ============================================================
143 
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
144 
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
145 
// Retrieval info: PRIVATE: clock_inputs NUMERIC "2"
146 
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
147 
// Retrieval info: CONSTANT: USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION STRING "OFF"
148 
// Retrieval info: CONSTANT: clock_type STRING "AUTO"
149 
// Retrieval info: USED_PORT: clkselect 0 0 0 0 INPUT GND "clkselect"
150 
// Retrieval info: USED_PORT: inclk0x 0 0 0 0 INPUT NODEFVAL "inclk0x"
151 
// Retrieval info: USED_PORT: inclk1x 0 0 0 0 INPUT NODEFVAL "inclk1x"
152 
// Retrieval info: USED_PORT: outclk 0 0 0 0 OUTPUT NODEFVAL "outclk"
153 
// Retrieval info: CONNECT: @clkselect 0 0 1 1 GND 0 0 0 0
154 
// Retrieval info: CONNECT: @inclk 0 0 1 1 inclk1x 0 0 0 0
155 
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0x 0 0 0 0
156 
// Retrieval info: CONNECT: @clkselect 0 0 1 0 clkselect 0 0 0 0
157 
// Retrieval info: CONNECT: @inclk 0 0 2 2 GND 0 0 2 0
158 
// Retrieval info: CONNECT: outclk 0 0 0 0 @outclk 0 0 0 0
159 
// Retrieval info: CONNECT: @ena 0 0 0 0 VCC 0 0 0 0
160 
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_mux.v TRUE
161 
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_mux.inc FALSE
162 
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_mux.cmp FALSE
163 
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_mux.bsf TRUE
164 
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_mux_inst.v FALSE
165 
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_mux_bb.v FALSE
166 
// Retrieval info: LIB_FILE: arriaii

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.