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[/] [sgmii/] [trunk/] [build/] [OpenCore_MAC/] [TECH/] [xilinx/] [GMII2RGMII.v] - Blame information for rev 26

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:57:12 06/01/2010 
// Design Name: 
// Module Name:    GMII2RGMII 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module GMII2RGMII(
    input [7:0] TxD,
    input TxClk,
    input TxEn,
    input TxErr,
    output [3:0] RGMII_TxD,
    output RGMII_TxCtl,
    output RGMII_TxClk,
         input ClkEN,
         input rst
    );
 
reg [3:0] TxHighNib;
reg [3:0] TxHighNib2;
reg [3:0] TxLowNib;
reg     TX_EN1;
wire    EN_xor_ERR1;
reg     EN_xor_ERR2;
reg     EN_xor_ERR3;
 
wire    DDR_R;
reg     DDR_S;
wire    DDR_CE;
 
 
 
        initial
        begin
        DDR_S <= 0;
        end
 
        assign DDR_CE = ClkEN;
        assign DDR_R = rst;
 
        always@(posedge(TxClk))
        begin
                        TxLowNib <= TxD[3:0];
        end
 
        always@(negedge(TxClk))
        begin
                        TxHighNib <= TxD[7:4];
                        TxHighNib2      <= TxHighNib;
        end
 
 
        genvar I;
   generate
       for (I=0;I<4;I=I+1)
       begin: gen_ddr
        // ODDR: Output Double Data Rate Output Register with Set, Reset
   //       and Clock Enable.
   //       Virtex-4/5
   // Xilinx HDL Language Template, version 10.1
                        ODDR #(
                                .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" 
                                .INIT(1'b0),    // Initial value of Q: 1'b0 or 1'b1
                                .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" 
                        ) ODDR_inst (
                                .Q(RGMII_TxD[I]),   // 1-bit DDR output
                                .C(TxClk),   // 1-bit clock input
                                .CE(DDR_CE), // 1-bit clock enable input
                                .D1(TxLowNib[I]), // 1-bit data input (positive edge)
                                .D2(TxHighNib2[I]), // 1-bit data input (negative edge)
                                .R(DDR_R),   // 1-bit reset
                                .S(DDR_S)    // 1-bit set
                        );
       end
   endgenerate
 
        always@(posedge(TxClk))
        begin
                TX_EN1 <= TxEn;
                EN_xor_ERR2 <= EN_xor_ERR1;
        end
 
        always@(negedge(TxClk))
        begin
                EN_xor_ERR3 <= EN_xor_ERR2;
        end
 
        assign EN_xor_ERR1 = TxEn^TxErr;
 
        ODDR #(
                                .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" 
                                .INIT(1'b0),    // Initial value of Q: 1'b0 or 1'b1
                                .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" 
                        ) ODDR_inst (
                                .Q(RGMII_TxCtl),   // 1-bit DDR output
                                .C(TxClk),   // 1-bit clock input
                                .CE(DDR_CE), // 1-bit clock enable input
                                .D1(TX_EN1), // 1-bit data input (positive edge)
                                .D2(EN_xor_ERR3), // 1-bit data input (negative edge)
                                .R(DDR_R),   // 1-bit reset
                                .S(DDR_S)    // 1-bit set
                        );
 
        ODDR #(
                                .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" 
                                .INIT(1'b0),    // Initial value of Q: 1'b0 or 1'b1
                                .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" 
                        ) ODDR_clk (
                                .Q(RGMII_TxClk),   // 1-bit DDR output
                                .C(TxClk),   // 1-bit clock input
                                .CE(DDR_CE), // 1-bit clock enable input
                                .D1(1), // 1-bit data input (positive edge)
                                .D2(0), // 1-bit data input (negative edge)
                                .R(DDR_R),   // 1-bit reset
                                .S(DDR_S)    // 1-bit set
                        );
endmodule

Line No.	Rev	Author	Line
1	26	jefflieu	`timescale 1ns / 1ps
2			`//////////////////////////////////////////////////////////////////////////////////`
3			`// Company:`
4			`// Engineer:`
5			`//`
6			`// Create Date: 14:57:12 06/01/2010`
7			`// Design Name:`
8			`// Module Name: GMII2RGMII`
9			`// Project Name:`
10			`// Target Devices:`
11			`// Tool versions:`
12			`// Description:`
13			`//`
14			`// Dependencies:`
15			`//`
16			`// Revision:`
17			`// Revision 0.01 - File Created`
18			`// Additional Comments:`
19			`//`
20			`//////////////////////////////////////////////////////////////////////////////////`
21			`module GMII2RGMII(`
22			`input [7:0] TxD,`
23			`input TxClk,`
24			`input TxEn,`
25			`input TxErr,`
26			`output [3:0] RGMII_TxD,`
27			`output RGMII_TxCtl,`
28			`output RGMII_TxClk,`
29			`input ClkEN,`
30			`input rst`
31			`);`
32
33			`reg [3:0] TxHighNib;`
34			`reg [3:0] TxHighNib2;`
35			`reg [3:0] TxLowNib;`
36			`reg TX_EN1;`
37			`wire EN_xor_ERR1;`
38			`reg EN_xor_ERR2;`
39			`reg EN_xor_ERR3;`
40
41			`wire DDR_R;`
42			`reg DDR_S;`
43			`wire DDR_CE;`
44
45
46
47			`initial`
48			`begin`
49			`DDR_S <= 0;`
50			`end`
51
52			`assign DDR_CE = ClkEN;`
53			`assign DDR_R = rst;`
54
55			`always@(posedge(TxClk))`
56			`begin`
57			`TxLowNib <= TxD[3:0];`
58			`end`
59
60			`always@(negedge(TxClk))`
61			`begin`
62			`TxHighNib <= TxD[7:4];`
63			`TxHighNib2 <= TxHighNib;`
64			`end`
65
66
67			`genvar I;`
68			`generate`
69			`for (I=0;I<4;I=I+1)`
70			`begin: gen_ddr`
71			`// ODDR: Output Double Data Rate Output Register with Set, Reset`
72			`// and Clock Enable.`
73			`// Virtex-4/5`
74			`// Xilinx HDL Language Template, version 10.1`
75			`ODDR #(`
76			`.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"`
77			`.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1`
78			`.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"`
79			`) ODDR_inst (`
80			`.Q(RGMII_TxD[I]), // 1-bit DDR output`
81			`.C(TxClk), // 1-bit clock input`
82			`.CE(DDR_CE), // 1-bit clock enable input`
83			`.D1(TxLowNib[I]), // 1-bit data input (positive edge)`
84			`.D2(TxHighNib2[I]), // 1-bit data input (negative edge)`
85			`.R(DDR_R), // 1-bit reset`
86			`.S(DDR_S) // 1-bit set`
87			`);`
88			`end`
89			`endgenerate`
90
91			`always@(posedge(TxClk))`
92			`begin`
93			`TX_EN1 <= TxEn;`
94			`EN_xor_ERR2 <= EN_xor_ERR1;`
95			`end`
96
97			`always@(negedge(TxClk))`
98			`begin`
99			`EN_xor_ERR3 <= EN_xor_ERR2;`
100			`end`
101
102			`assign EN_xor_ERR1 = TxEn^TxErr;`
103
104			`ODDR #(`
105			`.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"`
106			`.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1`
107			`.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"`
108			`) ODDR_inst (`
109			`.Q(RGMII_TxCtl), // 1-bit DDR output`
110			`.C(TxClk), // 1-bit clock input`
111			`.CE(DDR_CE), // 1-bit clock enable input`
112			`.D1(TX_EN1), // 1-bit data input (positive edge)`
113			`.D2(EN_xor_ERR3), // 1-bit data input (negative edge)`
114			`.R(DDR_R), // 1-bit reset`
115			`.S(DDR_S) // 1-bit set`
116			`);`
117
118			`ODDR #(`
119			`.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"`
120			`.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1`
121			`.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"`
122			`) ODDR_clk (`
123			`.Q(RGMII_TxClk), // 1-bit DDR output`
124			`.C(TxClk), // 1-bit clock input`
125			`.CE(DDR_CE), // 1-bit clock enable input`
126			`.D1(1), // 1-bit data input (positive edge)`
127			`.D2(0), // 1-bit data input (negative edge)`
128			`.R(DDR_R), // 1-bit reset`
129			`.S(DDR_S) // 1-bit set`
130			`);`
131			`endmodule`

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[/] [sgmii/] [trunk/] [build/] [OpenCore_MAC/] [TECH/] [xilinx/] [GMII2RGMII.v] - Blame information for rev 26