URL https://opencores.org/ocsvn/sgmii/sgmii/trunk

Subversion Repositories sgmii

[/] [sgmii/] [trunk/] [build/] [OpenCore_MAC/] [afifo.v] - Blame information for rev 26

Details | Compare with Previous | View Log


module afifo(
din,
wr_en,
wr_clk,
rd_en,
rd_clk,
ainit,
dout,
full,
almost_full,
empty,
wr_count,
rd_count,
rd_ack,
wr_ack);
 
//////////////////////////////////////////////////////
parameter               DATA_WIDTH                      =16;
parameter               ADDR_WIDTH                      =8;
parameter               COUNT_DATA_WIDTH        =8;
parameter               ALMOST_FULL_DEPTH       =8;
//////////////////////////////////////////////////////
input   [DATA_WIDTH-1:0]                         din;
input                                                           wr_en;
input                                                           wr_clk;
input                                                           rd_en;
input                                                           rd_clk;
input                                                           ainit;
output  [DATA_WIDTH-1:0]                         dout;
output                                                          full;
output                                                          almost_full;
output                                                          empty;
output  [COUNT_DATA_WIDTH-1:0]           wr_count /* synthesis syn_keep=1 */;
output  [COUNT_DATA_WIDTH-1:0]           rd_count /* synthesis syn_keep=1 */;
output                                                          rd_ack;
output                                                          wr_ack;
//////////////////////////////////////////////////////  
//local signals
////////////////////////////////////////////////////// 
reg             [ADDR_WIDTH-1:0]                         Add_wr;
reg             [ADDR_WIDTH-1:0]                         Add_wr_ungray;
reg             [ADDR_WIDTH-1:0]                         Add_wr_gray;
reg             [ADDR_WIDTH-1:0]                         Add_wr_gray_dl1;
 
reg             [ADDR_WIDTH-1:0]                         Add_rd;
wire    [ADDR_WIDTH-1:0]                         Add_rd_pluse;
reg             [ADDR_WIDTH-1:0]                         Add_rd_gray;
reg             [ADDR_WIDTH-1:0]                         Add_rd_gray_dl1;
reg             [ADDR_WIDTH-1:0]                         Add_rd_ungray;
wire    [ADDR_WIDTH-1:0]                 Add_wr_pluse;
integer                                                         i;
reg                                                             full /* synthesis syn_keep=1 */;
reg                                                             empty;
wire    [ADDR_WIDTH-1:0]                         ff_used_wr;
wire    [ADDR_WIDTH-1:0]                         ff_used_rd;
reg                                                             rd_ack;
reg                                                             rd_ack_tmp;
reg                                                                     almost_full;
wire    [DATA_WIDTH-1:0]                         dout_tmp;
 
//////////////////////////////////////////////////////  
//Write clock domain
//////////////////////////////////////////////////////
assign wr_ack      =0;
assign ff_used_wr  =Add_wr-Add_rd_ungray;
 
assign wr_count =ff_used_wr[ADDR_WIDTH-1:ADDR_WIDTH-COUNT_DATA_WIDTH];
 
 
 
 
always @ (posedge ainit or posedge wr_clk)
        if (ainit)
                Add_wr_gray                     <=0;
        else
                begin
                Add_wr_gray[ADDR_WIDTH-1]       <=Add_wr[ADDR_WIDTH-1];
                for (i=ADDR_WIDTH-2;i>=0;i=i-1)
                Add_wr_gray[i]                  <=Add_wr[i+1]^Add_wr[i];
                end
 
//����ַ���з�gray����.
 
always @ (posedge wr_clk or posedge ainit)
        if (ainit)
                Add_rd_gray_dl1                 <=0;
        else
                Add_rd_gray_dl1                 <=Add_rd_gray;
 
always @ (posedge wr_clk or posedge ainit)
        if (ainit)
                Add_rd_ungray                   =0;
        else
                begin
                Add_rd_ungray[ADDR_WIDTH-1]     =Add_rd_gray_dl1[ADDR_WIDTH-1];
                for (i=ADDR_WIDTH-2;i>=0;i=i-1)
                        Add_rd_ungray[i]        =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i];
                end
 
assign                  Add_wr_pluse=Add_wr+1;
 
 
/*
always @ (Add_wr_pluse or Add_rd_ungray)
        if (Add_wr_pluse==Add_rd_ungray)
                full    =1;
        else
                full    =0;
 
*/
always @ (posedge wr_clk or posedge ainit)
        if (ainit)
                full    <=0;
        else if(Add_wr_pluse==Add_rd_ungray&&wr_en)
                full    <=1;
        else if(Add_wr!=Add_rd_ungray)
                full    <=0;
 
 
always @ (posedge wr_clk or posedge ainit)
        if (ainit)
                almost_full             <=0;
        else if (wr_count>=ALMOST_FULL_DEPTH)
                almost_full             <=1;
        else
                almost_full             <=0;
 
always @ (posedge wr_clk or posedge ainit)
        if (ainit)
                Add_wr  <=0;
        else if (wr_en&&!full)
                Add_wr  <=Add_wr +1;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//******************************************************************************
//read clock domain
//******************************************************************************
always @ (posedge rd_clk or posedge ainit)
        if (ainit)
                rd_ack          <=0;
        else if (rd_en&&!empty)
                rd_ack          <=1;
        else
                rd_ack          <=0;
 
 
 
assign ff_used_rd       =Add_wr_ungray-Add_rd;
assign rd_count         =ff_used_rd[ADDR_WIDTH-1:ADDR_WIDTH-COUNT_DATA_WIDTH];
assign Add_rd_pluse     =Add_rd+1;
 
 
always @ (posedge rd_clk or posedge ainit)
        if (ainit)
                Add_rd          <=0;
        else if (rd_en&&!empty)  //��EOP��Ͳ����ˡ�
                Add_rd          <=Add_rd + 1;
 
//����ַ����gray��任.
always @ (posedge ainit or posedge rd_clk)
        if (ainit)
                Add_rd_gray                     <=0;
        else
                begin
                Add_rd_gray[ADDR_WIDTH-1]       <=Add_rd[ADDR_WIDTH-1];
                for (i=ADDR_WIDTH-2;i>=0;i=i-1)
                Add_rd_gray[i]                  <=Add_rd[i+1]^Add_rd[i];
                end
/*              Add_rd_gray                     <={     Add_rd[8],
                                                                Add_rd[8]^Add_rd[7],
                                                                Add_rd[7]^Add_rd[6],
                                                                Add_rd[6]^Add_rd[5],
                                                                Add_rd[5]^Add_rd[4],
                                                                Add_rd[4]^Add_rd[3],
                                                                Add_rd[3]^Add_rd[2],
                                                                Add_rd[2]^Add_rd[1],
                                                                Add_rd[1]^Add_rd[0]};
*/
//д��ַ���з�gray����.
 
always @ (posedge rd_clk or posedge ainit)
        if (ainit)
                Add_wr_gray_dl1         <=0;
        else
                Add_wr_gray_dl1         <=Add_wr_gray;
 
always @ (posedge rd_clk or posedge ainit)
        if (ainit)
                Add_wr_ungray           =0;
        else
                begin
                Add_wr_ungray[ADDR_WIDTH-1]     =Add_wr_gray_dl1[ADDR_WIDTH-1];
                for (i=ADDR_WIDTH-2;i>=0;i=i-1)
                        Add_wr_ungray[i]        =Add_wr_ungray[i+1]^Add_wr_gray_dl1[i];
                end
 
/*              Add_wr_ungray   <={
                Add_wr_gray_dl1[8],
                Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7],
                Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6],
                Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5],
                Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4],
                Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3],
                Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2],
                Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2]^Add_wr_gray_dl1[1],
                Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2]^Add_wr_gray_dl1[1]^Add_wr_gray_dl1[0] };
*/
//empty�źŲ��� 
/*
always @ (Add_rd or Add_wr_ungray)
        if (Add_rd==Add_wr_ungray)
                empty   =1;
        else
                empty   =0;
*/
always @ (posedge rd_clk or posedge ainit)
        if (ainit)
                empty   <=1;
        else if (Add_rd_pluse==Add_wr_ungray&&rd_en)
                empty   <=1;
        else if (Add_rd!=Add_wr_ungray)
                empty   <=0;
 
 
 
//////////////////////////////////////////////////////  
//instant need change for your own dpram
////////////////////////////////////////////////////// 
duram #(
DATA_WIDTH,
ADDR_WIDTH
)
U_duram                 (
.data_a     (din                ),
.wren_a     (wr_en          ),
.address_a  (Add_wr         ),
.address_b  (Add_rd         ),
.clock_a    (wr_clk         ),
.clock_b    (rd_clk         ),
.q_b        (dout              ));
 
endmodule

Browse

Tools

Subversion Repositories sgmii

[/] [sgmii/] [trunk/] [build/] [OpenCore_MAC/] [afifo.v] - Blame information for rev 26

Line No.	Rev	Author	Line
1	26	jefflieu	`module afifo(`
2			`din,`
3			`wr_en,`
4			`wr_clk,`
5			`rd_en,`
6			`rd_clk,`
7			`ainit,`
8			`dout,`
9			`full,`
10			`almost_full,`
11			`empty,`
12			`wr_count,`
13			`rd_count,`
14			`rd_ack,`
15			`wr_ack);`
16
17			`//////////////////////////////////////////////////////`
18			`parameter DATA_WIDTH =16;`
19			`parameter ADDR_WIDTH =8;`
20			`parameter COUNT_DATA_WIDTH =8;`
21			`parameter ALMOST_FULL_DEPTH =8;`
22			`//////////////////////////////////////////////////////`
23			`input [DATA_WIDTH-1:0] din;`
24			`input wr_en;`
25			`input wr_clk;`
26			`input rd_en;`
27			`input rd_clk;`
28			`input ainit;`
29			`output [DATA_WIDTH-1:0] dout;`
30			`output full;`
31			`output almost_full;`
32			`output empty;`
33			`output [COUNT_DATA_WIDTH-1:0] wr_count /* synthesis syn_keep=1 */;`
34			`output [COUNT_DATA_WIDTH-1:0] rd_count /* synthesis syn_keep=1 */;`
35			`output rd_ack;`
36			`output wr_ack;`
37			`//////////////////////////////////////////////////////`
38			`//local signals`
39			`//////////////////////////////////////////////////////`
40			`reg [ADDR_WIDTH-1:0] Add_wr;`
41			`reg [ADDR_WIDTH-1:0] Add_wr_ungray;`
42			`reg [ADDR_WIDTH-1:0] Add_wr_gray;`
43			`reg [ADDR_WIDTH-1:0] Add_wr_gray_dl1;`
44
45			`reg [ADDR_WIDTH-1:0] Add_rd;`
46			`wire [ADDR_WIDTH-1:0] Add_rd_pluse;`
47			`reg [ADDR_WIDTH-1:0] Add_rd_gray;`
48			`reg [ADDR_WIDTH-1:0] Add_rd_gray_dl1;`
49			`reg [ADDR_WIDTH-1:0] Add_rd_ungray;`
50			`wire [ADDR_WIDTH-1:0] Add_wr_pluse;`
51			`integer i;`
52			`reg full /* synthesis syn_keep=1 */;`
53			`reg empty;`
54			`wire [ADDR_WIDTH-1:0] ff_used_wr;`
55			`wire [ADDR_WIDTH-1:0] ff_used_rd;`
56			`reg rd_ack;`
57			`reg rd_ack_tmp;`
58			`reg almost_full;`
59			`wire [DATA_WIDTH-1:0] dout_tmp;`
60
61			`//////////////////////////////////////////////////////`
62			`//Write clock domain`
63			`//////////////////////////////////////////////////////`
64			`assign wr_ack =0;`
65			`assign ff_used_wr =Add_wr-Add_rd_ungray;`
66
67			`assign wr_count =ff_used_wr[ADDR_WIDTH-1:ADDR_WIDTH-COUNT_DATA_WIDTH];`
68
69
70
71
72			`always @ (posedge ainit or posedge wr_clk)`
73			`if (ainit)`
74			`Add_wr_gray <=0;`
75			`else`
76			`begin`
77			`Add_wr_gray[ADDR_WIDTH-1] <=Add_wr[ADDR_WIDTH-1];`
78			`for (i=ADDR_WIDTH-2;i>=0;i=i-1)`
79			`Add_wr_gray[i] <=Add_wr[i+1]^Add_wr[i];`
80			`end`
81
82			`//��ַ��з�gray��.`
83
84			`always @ (posedge wr_clk or posedge ainit)`
85			`if (ainit)`
86			`Add_rd_gray_dl1 <=0;`
87			`else`
88			`Add_rd_gray_dl1 <=Add_rd_gray;`
89
90			`always @ (posedge wr_clk or posedge ainit)`
91			`if (ainit)`
92			`Add_rd_ungray =0;`
93			`else`
94			`begin`
95			`Add_rd_ungray[ADDR_WIDTH-1] =Add_rd_gray_dl1[ADDR_WIDTH-1];`
96			`for (i=ADDR_WIDTH-2;i>=0;i=i-1)`
97			`Add_rd_ungray[i] =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i];`
98			`end`
99
100			`assign Add_wr_pluse=Add_wr+1;`
101
102
103			`/*`
104			`always @ (Add_wr_pluse or Add_rd_ungray)`
105			`if (Add_wr_pluse==Add_rd_ungray)`
106			`full =1;`
107			`else`
108			`full =0;`
109
110			`*/`
111			`always @ (posedge wr_clk or posedge ainit)`
112			`if (ainit)`
113			`full <=0;`
114			`else if(Add_wr_pluse==Add_rd_ungray&&wr_en)`
115			`full <=1;`
116			`else if(Add_wr!=Add_rd_ungray)`
117			`full <=0;`
118
119
120			`always @ (posedge wr_clk or posedge ainit)`
121			`if (ainit)`
122			`almost_full <=0;`
123			`else if (wr_count>=ALMOST_FULL_DEPTH)`
124			`almost_full <=1;`
125			`else`
126			`almost_full <=0;`
127
128			`always @ (posedge wr_clk or posedge ainit)`
129			`if (ainit)`
130			`Add_wr <=0;`
131			`else if (wr_en&&!full)`
132			`Add_wr <=Add_wr +1;`
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178			`//******************************************************************************`
179			`//read clock domain`
180			`//******************************************************************************`
181			`always @ (posedge rd_clk or posedge ainit)`
182			`if (ainit)`
183			`rd_ack <=0;`
184			`else if (rd_en&&!empty)`
185			`rd_ack <=1;`
186			`else`
187			`rd_ack <=0;`
188
189
190
191			`assign ff_used_rd =Add_wr_ungray-Add_rd;`
192			`assign rd_count =ff_used_rd[ADDR_WIDTH-1:ADDR_WIDTH-COUNT_DATA_WIDTH];`
193			`assign Add_rd_pluse =Add_rd+1;`
194
195
196			`always @ (posedge rd_clk or posedge ainit)`
197			`if (ainit)`
198			`Add_rd <=0;`
199			`else if (rd_en&&!empty) //��EOP��Ͳ��ˡ�`
200			`Add_rd <=Add_rd + 1;`
201
202			`//��ַ��gray��任.`
203			`always @ (posedge ainit or posedge rd_clk)`
204			`if (ainit)`
205			`Add_rd_gray <=0;`
206			`else`
207			`begin`
208			`Add_rd_gray[ADDR_WIDTH-1] <=Add_rd[ADDR_WIDTH-1];`
209			`for (i=ADDR_WIDTH-2;i>=0;i=i-1)`
210			`Add_rd_gray[i] <=Add_rd[i+1]^Add_rd[i];`
211			`end`
212			`/* Add_rd_gray <={ Add_rd[8],`
213			`Add_rd[8]^Add_rd[7],`
214			`Add_rd[7]^Add_rd[6],`
215			`Add_rd[6]^Add_rd[5],`
216			`Add_rd[5]^Add_rd[4],`
217			`Add_rd[4]^Add_rd[3],`
218			`Add_rd[3]^Add_rd[2],`
219			`Add_rd[2]^Add_rd[1],`
220			`Add_rd[1]^Add_rd[0]};`
221			`*/`
222			`//д��ַ��з�gray��.`
223
224			`always @ (posedge rd_clk or posedge ainit)`
225			`if (ainit)`
226			`Add_wr_gray_dl1 <=0;`
227			`else`
228			`Add_wr_gray_dl1 <=Add_wr_gray;`
229
230			`always @ (posedge rd_clk or posedge ainit)`
231			`if (ainit)`
232			`Add_wr_ungray =0;`
233			`else`
234			`begin`
235			`Add_wr_ungray[ADDR_WIDTH-1] =Add_wr_gray_dl1[ADDR_WIDTH-1];`
236			`for (i=ADDR_WIDTH-2;i>=0;i=i-1)`
237			`Add_wr_ungray[i] =Add_wr_ungray[i+1]^Add_wr_gray_dl1[i];`
238			`end`
239
240			`/* Add_wr_ungray <={`
241			`Add_wr_gray_dl1[8],`
242			`Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7],`
243			`Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6],`
244			`Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5],`
245			`Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4],`
246			`Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3],`
247			`Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2],`
248			`Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2]^Add_wr_gray_dl1[1],`
249			`Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2]^Add_wr_gray_dl1[1]^Add_wr_gray_dl1[0] };`
250			`*/`
251			`//empty�źŲ��`
252			`/*`
253			`always @ (Add_rd or Add_wr_ungray)`
254			`if (Add_rd==Add_wr_ungray)`
255			`empty =1;`
256			`else`
257			`empty =0;`
258			`*/`
259			`always @ (posedge rd_clk or posedge ainit)`
260			`if (ainit)`
261			`empty <=1;`
262			`else if (Add_rd_pluse==Add_wr_ungray&&rd_en)`
263			`empty <=1;`
264			`else if (Add_rd!=Add_wr_ungray)`
265			`empty <=0;`
266
267
268
269			`//////////////////////////////////////////////////////`
270			`//instant need change for your own dpram`
271			`//////////////////////////////////////////////////////`
272			`duram #(`
273			`DATA_WIDTH,`
274			`ADDR_WIDTH`
275			`)`
276			`U_duram (`
277			`.data_a (din ),`
278			`.wren_a (wr_en ),`
279			`.address_a (Add_wr ),`
280			`.address_b (Add_rd ),`
281			`.clock_a (wr_clk ),`
282			`.clock_b (rd_clk ),`
283			`.q_b (dout ));`
284
285			`endmodule`