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[/] [sgmii/] [trunk/] [build/] [OpenCore_MAC/] [icon_xst_example.v] - Blame information for rev 26

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1 26 jefflieu
//-----------------------------------------------------------------------------
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// Copyright (c) 1999-2006 Xilinx Inc.  All rights reserved.
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//-----------------------------------------------------------------------------
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// Title      : ICON Core Xilinx XST Usage Example
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// Project    : ChipScope
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//-----------------------------------------------------------------------------
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// File       : icon_xst_example.v
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// Company    : Xilinx Inc.
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// Created    : 2002/03/27
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//-----------------------------------------------------------------------------
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// Description: Example of how to instantiate the ICON core in a Verilog 
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//              design for use with the Xilinx XST synthesis tool.
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//-----------------------------------------------------------------------------
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module icon_xst_example
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  (
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  );
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  //-----------------------------------------------------------------
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  //
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  //  ICON core wire declarations
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  //
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  //-----------------------------------------------------------------
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  wire [35:0] control0;
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  wire [35:0] control1;
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  //-----------------------------------------------------------------
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  //
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  //  ICON core instance
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  //
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  //-----------------------------------------------------------------
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  icon i_icon
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    (
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      .control0(control0),
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      .control1(control1)
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    );
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endmodule
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//-------------------------------------------------------------------
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//
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//  ICON core module declaration
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//
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//-------------------------------------------------------------------
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module icon
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  (
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      control0,
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      control1
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  );
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  output [35:0] control0;
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  output [35:0] control1;
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endmodule

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