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jefflieu |
// megafunction wizard: %ALTGX%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: alt4gxb
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// ============================================================
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// File Name: altera_tse_alt4gxb_gige.v
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// Megafunction Name(s):
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// alt4gxb
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//
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// Simulation Library Files(s):
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// stratixiv_hssi
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 11.0 Internal Build 133 03/08/2011 PN Full Version
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// ************************************************************
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//Copyright (C) 1991-2011 Altera Corporation
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//Your use of Altera Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Altera Program License
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//Subscription Agreement, Altera MegaCore Function License
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//Agreement, or other applicable license agreement, including,
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//without limitation, that your use is for the sole purpose of
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//programming logic devices manufactured by Altera and sold by
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//Altera or its authorized distributors. Please refer to the
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//applicable agreement for further details.
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//alt4gxb CBX_AUTO_BLACKBOX="ALL" device_family="Stratix IV" effective_data_rate="1250.0 Mbps" enable_lc_tx_pll="false" equalizer_ctrl_a_setting=0 equalizer_ctrl_b_setting=0 equalizer_ctrl_c_setting=0 equalizer_ctrl_d_setting=0 equalizer_ctrl_v_setting=0 equalizer_dcgain_setting=0 gen_reconfig_pll="false" gx_channel_type="auto" gxb_analog_power="AUTO" gxb_powerdown_width=1 input_clock_frequency="125.0 MHz" intended_device_speed_grade="2" intended_device_variant="GX" loopback_mode="slb" number_of_channels=1 number_of_quads=1 operation_mode="duplex" pll_control_width=1 pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=0 preemphasis_ctrl_2ndposttap_inv_setting="false" preemphasis_ctrl_2ndposttap_setting=0 preemphasis_ctrl_pretap_inv_setting="false" preemphasis_ctrl_pretap_setting=0 protocol="gige" receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=1 reconfig_fromgxb_port_width=17 reconfig_togxb_port_width=4 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="false" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_channel_width=8 rx_common_mode="0.82v" rx_cru_bandwidth_type="medium" rx_cru_inclock0_period=8000 rx_cru_m_divider=5 rx_cru_n_divider=1 rx_cru_vco_post_scale_divider=4 rx_data_rate=1250 rx_data_rate_remainder=0 rx_datapath_protocol="basic" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_fifo_mode_manual_control="normal" rx_rate_match_pattern1="10100010010101111100" rx_rate_match_pattern2="10101011011010000011" rx_rate_match_pattern_size=20 rx_run_length=5 rx_run_length_enable="true" rx_signal_detect_loss_threshold=1 rx_signal_detect_threshold=2 rx_signal_detect_valid_threshold=1 rx_use_align_state_machine="true" rx_use_clkout="true" rx_use_coreclk="false" rx_use_cruclk="true" rx_use_deserializer_double_data_mode="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_external_termination="false" rx_use_rate_match_pattern1_only="false" rx_word_aligner_num_byte=1 starting_channel_number=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_analog_power="auto" tx_channel_width=8 tx_clkout_width=1 tx_common_mode="0.65v" tx_data_rate=1250 tx_data_rate_remainder=0 tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_pll_bandwidth_type="high" tx_pll_clock_post_divider=1 tx_pll_inclk0_period=8000 tx_pll_m_divider=5 tx_pll_n_divider=1 tx_pll_type="CMU" tx_pll_vco_post_scale_divider=4 tx_slew_rate="medium" tx_transmit_protocol="basic" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_external_termination="false" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=1 cal_blk_clk fixedclk fixedclk_fast gxb_powerdown pll_inclk pll_locked pll_powerdown reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_clkout rx_cruclk rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_disperr rx_errdetect rx_freqlocked rx_patterndetect rx_recovclkout rx_rlv rx_rmfifodatadeleted rx_rmfifodatainserted rx_runningdisp rx_seriallpbken rx_syncstatus tx_clkout tx_ctrlenable tx_datain tx_dataout tx_digitalreset
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//VERSION_BEGIN 11.0 cbx_alt4gxb 2011:03:08:21:08:40:PN cbx_mgl 2011:03:08:21:43:22:PN cbx_tgx 2011:03:08:21:08:40:PN VERSION_END
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// synthesis VERILOG_INPUT_VERSION VERILOG_2001
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// altera message_off 10463
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//synthesis_resources = reg 8 stratixiv_hssi_calibration_block 1 stratixiv_hssi_clock_divider 1 stratixiv_hssi_cmu 1 stratixiv_hssi_pll 2 stratixiv_hssi_rx_pcs 1 stratixiv_hssi_rx_pma 1 stratixiv_hssi_tx_pcs 1 stratixiv_hssi_tx_pma 1
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//synopsys translate_off
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`timescale 1 ps / 1 ps
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//synopsys translate_on
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(* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF;suppress_da_rule_internal=c104"} *)
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module altera_tse_alt4gxb_gige_alt4gxb_gtca
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(
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cal_blk_clk,
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fixedclk,
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fixedclk_fast,
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gxb_powerdown,
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pll_inclk,
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pll_locked,
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pll_powerdown,
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reconfig_clk,
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reconfig_fromgxb,
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reconfig_togxb,
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rx_analogreset,
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rx_clkout,
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rx_cruclk,
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rx_ctrldetect,
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rx_datain,
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rx_dataout,
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rx_digitalreset,
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rx_disperr,
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rx_errdetect,
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rx_freqlocked,
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rx_patterndetect,
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rx_recovclkout,
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rx_rlv,
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rx_rmfifodatadeleted,
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rx_rmfifodatainserted,
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rx_runningdisp,
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rx_seriallpbken,
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rx_syncstatus,
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tx_clkout,
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tx_ctrlenable,
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tx_datain,
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tx_dataout,
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tx_digitalreset) /* synthesis synthesis_clearbox=2 */;
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input cal_blk_clk;
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input fixedclk;
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input [5:0] fixedclk_fast;
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input [0:0] gxb_powerdown;
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input pll_inclk;
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output [0:0] pll_locked;
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input [0:0] pll_powerdown;
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input reconfig_clk;
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output [16:0] reconfig_fromgxb;
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input [3:0] reconfig_togxb;
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input [0:0] rx_analogreset;
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output [0:0] rx_clkout;
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input [0:0] rx_cruclk;
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output [0:0] rx_ctrldetect;
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input [0:0] rx_datain;
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output [7:0] rx_dataout;
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input [0:0] rx_digitalreset;
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output [0:0] rx_disperr;
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output [0:0] rx_errdetect;
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output [0:0] rx_freqlocked;
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output [0:0] rx_patterndetect;
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output [0:0] rx_recovclkout;
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output [0:0] rx_rlv;
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output [0:0] rx_rmfifodatadeleted;
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output [0:0] rx_rmfifodatainserted;
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output [0:0] rx_runningdisp;
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input [0:0] rx_seriallpbken;
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output [0:0] rx_syncstatus;
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output [0:0] tx_clkout;
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input [0:0] tx_ctrlenable;
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input [7:0] tx_datain;
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output [0:0] tx_dataout;
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input [0:0] tx_digitalreset;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri0 cal_blk_clk;
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tri0 fixedclk;
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tri1 [5:0] fixedclk_fast;
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tri0 [0:0] gxb_powerdown;
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tri0 pll_inclk;
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tri0 [0:0] pll_powerdown;
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tri0 reconfig_clk;
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tri0 [0:0] rx_analogreset;
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tri0 [0:0] rx_cruclk;
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tri0 [0:0] rx_digitalreset;
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tri0 [0:0] rx_seriallpbken;
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tri0 [0:0] tx_ctrlenable;
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tri0 [7:0] tx_datain;
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tri0 [0:0] tx_digitalreset;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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parameter starting_channel_number = 0;
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reg fixedclk_div0quad0c;
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wire wire_fixedclk_div0quad0c_clk;
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reg fixedclk_div1quad0c;
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wire wire_fixedclk_div1quad0c_clk;
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reg fixedclk_div2quad0c;
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wire wire_fixedclk_div2quad0c_clk;
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reg fixedclk_div3quad0c;
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wire wire_fixedclk_div3quad0c_clk;
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reg fixedclk_div4quad0c;
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wire wire_fixedclk_div4quad0c_clk;
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reg fixedclk_div5quad0c;
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wire wire_fixedclk_div5quad0c_clk;
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reg [1:0] reconfig_togxb_busy_reg;
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wire wire_cal_blk0_nonusertocmu;
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wire [1:0] wire_ch_clk_div0_analogfastrefclkout;
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wire [1:0] wire_ch_clk_div0_analogrefclkout;
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wire wire_ch_clk_div0_analogrefclkpulse;
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wire [99:0] wire_ch_clk_div0_dprioout;
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wire [599:0] wire_cent_unit0_cmudividerdprioout;
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wire [1799:0] wire_cent_unit0_cmuplldprioout;
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wire wire_cent_unit0_dpriodisableout;
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wire wire_cent_unit0_dprioout;
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wire [1:0] wire_cent_unit0_pllpowerdn;
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wire [1:0] wire_cent_unit0_pllresetout;
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wire wire_cent_unit0_quadresetout;
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wire [5:0] wire_cent_unit0_rxanalogresetout;
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wire [5:0] wire_cent_unit0_rxcrupowerdown;
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wire [5:0] wire_cent_unit0_rxcruresetout;
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wire [3:0] wire_cent_unit0_rxdigitalresetout;
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wire [5:0] wire_cent_unit0_rxibpowerdown;
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wire [1599:0] wire_cent_unit0_rxpcsdprioout;
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wire [1799:0] wire_cent_unit0_rxpmadprioout;
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wire [5:0] wire_cent_unit0_txanalogresetout;
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wire [3:0] wire_cent_unit0_txctrlout;
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wire [31:0] wire_cent_unit0_txdataout;
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wire [5:0] wire_cent_unit0_txdetectrxpowerdown;
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wire [3:0] wire_cent_unit0_txdigitalresetout;
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wire [5:0] wire_cent_unit0_txobpowerdown;
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wire [599:0] wire_cent_unit0_txpcsdprioout;
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wire [1799:0] wire_cent_unit0_txpmadprioout;
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wire [3:0] wire_rx_cdr_pll0_clk;
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wire [1:0] wire_rx_cdr_pll0_dataout;
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wire [299:0] wire_rx_cdr_pll0_dprioout;
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wire wire_rx_cdr_pll0_freqlocked;
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wire wire_rx_cdr_pll0_locked;
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wire wire_rx_cdr_pll0_pfdrefclkout;
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wire [3:0] wire_tx_pll0_clk;
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wire [299:0] wire_tx_pll0_dprioout;
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wire wire_tx_pll0_locked;
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wire wire_receive_pcs0_cdrctrllocktorefclkout;
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wire wire_receive_pcs0_clkout;
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wire [3:0] wire_receive_pcs0_ctrldetect;
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wire [39:0] wire_receive_pcs0_dataout;
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wire [3:0] wire_receive_pcs0_disperr;
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wire [399:0] wire_receive_pcs0_dprioout;
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wire [3:0] wire_receive_pcs0_errdetect;
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wire [3:0] wire_receive_pcs0_patterndetect;
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wire wire_receive_pcs0_rlv;
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wire [3:0] wire_receive_pcs0_rmfifodatadeleted;
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wire [3:0] wire_receive_pcs0_rmfifodatainserted;
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wire [3:0] wire_receive_pcs0_runningdisp;
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wire [3:0] wire_receive_pcs0_syncstatus;
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wire [7:0] wire_receive_pma0_analogtestbus;
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wire wire_receive_pma0_clockout;
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wire wire_receive_pma0_dataout;
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wire [299:0] wire_receive_pma0_dprioout;
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wire wire_receive_pma0_locktorefout;
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wire [63:0] wire_receive_pma0_recoverdataout;
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wire wire_receive_pma0_signaldetect;
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wire wire_transmit_pcs0_clkout;
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wire [19:0] wire_transmit_pcs0_dataout;
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wire [149:0] wire_transmit_pcs0_dprioout;
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wire wire_transmit_pcs0_forceelecidleout;
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wire wire_transmit_pcs0_txdetectrx;
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wire wire_transmit_pma0_clockout;
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wire wire_transmit_pma0_dataout;
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wire [299:0] wire_transmit_pma0_dprioout;
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wire wire_transmit_pma0_seriallpbkout;
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wire [1:0] analogfastrefclkout;
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wire [1:0] analogrefclkout;
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wire [0:0] analogrefclkpulse;
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wire cal_blk_powerdown;
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wire [599:0] cent_unit_cmudividerdprioout;
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wire [1799:0] cent_unit_cmuplldprioout;
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wire [1:0] cent_unit_pllpowerdn;
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wire [1:0] cent_unit_pllresetout;
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wire [0:0] cent_unit_quadresetout;
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wire [5:0] cent_unit_rxcrupowerdn;
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wire [5:0] cent_unit_rxibpowerdn;
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wire [1599:0] cent_unit_rxpcsdprioin;
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wire [1599:0] cent_unit_rxpcsdprioout;
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wire [1799:0] cent_unit_rxpmadprioin;
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wire [1799:0] cent_unit_rxpmadprioout;
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wire [1199:0] cent_unit_tx_dprioin;
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wire [31:0] cent_unit_tx_xgmdataout;
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wire [3:0] cent_unit_txctrlout;
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wire [5:0] cent_unit_txdetectrxpowerdn;
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wire [599:0] cent_unit_txdprioout;
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wire [5:0] cent_unit_txobpowerdn;
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wire [1799:0] cent_unit_txpmadprioin;
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wire [1799:0] cent_unit_txpmadprioout;
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wire [599:0] clk_div_cmudividerdprioin;
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wire [5:0] fixedclk_div_in;
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wire [0:0] fixedclk_enable;
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wire [5:0] fixedclk_in;
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wire [0:0] fixedclk_sel;
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wire [5:0] fixedclk_to_cmu;
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wire [0:0] nonusertocmu_out;
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wire [9:0] pll0_clkin;
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wire [299:0] pll0_dprioin;
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wire [299:0] pll0_dprioout;
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wire [3:0] pll0_out;
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|
|
wire [1:0] pll_ch_dataout_wire;
|
253 |
|
|
wire [299:0] pll_ch_dprioout;
|
254 |
|
|
wire [1799:0] pll_cmuplldprioout;
|
255 |
|
|
wire [0:0] pll_inclk_wire;
|
256 |
|
|
wire [0:0] pll_locked_out;
|
257 |
|
|
wire [1:0] pllpowerdn_in;
|
258 |
|
|
wire [1:0] pllreset_in;
|
259 |
|
|
wire [0:0] reconfig_togxb_busy;
|
260 |
|
|
wire [0:0] reconfig_togxb_disable;
|
261 |
|
|
wire [0:0] reconfig_togxb_in;
|
262 |
|
|
wire [0:0] reconfig_togxb_load;
|
263 |
|
|
wire [5:0] rx_analogreset_in;
|
264 |
|
|
wire [5:0] rx_analogreset_out;
|
265 |
|
|
wire [0:0] rx_clkout_wire;
|
266 |
|
|
wire [0:0] rx_coreclk_in;
|
267 |
|
|
wire [9:0] rx_cruclk_in;
|
268 |
|
|
wire [3:0] rx_deserclock_in;
|
269 |
|
|
wire [3:0] rx_digitalreset_in;
|
270 |
|
|
wire [3:0] rx_digitalreset_out;
|
271 |
|
|
wire [0:0] rx_enapatternalign;
|
272 |
|
|
wire [0:0] rx_freqlocked_wire;
|
273 |
|
|
wire [0:0] rx_locktodata;
|
274 |
|
|
wire [0:0] rx_locktodata_wire;
|
275 |
|
|
wire [0:0] rx_locktorefclk;
|
276 |
|
|
wire [0:0] rx_locktorefclk_wire;
|
277 |
|
|
wire [7:0] rx_out_wire;
|
278 |
|
|
wire [1599:0] rx_pcsdprioin_wire;
|
279 |
|
|
wire [1599:0] rx_pcsdprioout;
|
280 |
|
|
wire [0:0] rx_phfifordenable;
|
281 |
|
|
wire [0:0] rx_phfiforeset;
|
282 |
|
|
wire [0:0] rx_phfifowrdisable;
|
283 |
|
|
wire [0:0] rx_pldcruclk_in;
|
284 |
|
|
wire [3:0] rx_pll_clkout;
|
285 |
|
|
wire [0:0] rx_pll_pfdrefclkout_wire;
|
286 |
|
|
wire [0:0] rx_plllocked_wire;
|
287 |
|
|
wire [16:0] rx_pma_analogtestbus;
|
288 |
|
|
wire [0:0] rx_pma_clockout;
|
289 |
|
|
wire [0:0] rx_pma_dataout;
|
290 |
|
|
wire [0:0] rx_pma_locktorefout;
|
291 |
|
|
wire [19:0] rx_pma_recoverdataout_wire;
|
292 |
|
|
wire [1799:0] rx_pmadprioin_wire;
|
293 |
|
|
wire [1799:0] rx_pmadprioout;
|
294 |
|
|
wire [0:0] rx_powerdown;
|
295 |
|
|
wire [5:0] rx_powerdown_in;
|
296 |
|
|
wire [0:0] rx_prbscidenable;
|
297 |
|
|
wire [0:0] rx_rmfiforeset;
|
298 |
|
|
wire [5:0] rx_rxcruresetout;
|
299 |
|
|
wire [1799:0] rxpll_dprioin;
|
300 |
|
|
wire [5:0] tx_analogreset_out;
|
301 |
|
|
wire [0:0] tx_clkout_int_wire;
|
302 |
|
|
wire [0:0] tx_core_clkout_wire;
|
303 |
|
|
wire [0:0] tx_coreclk_in;
|
304 |
|
|
wire [7:0] tx_datain_wire;
|
305 |
|
|
wire [19:0] tx_dataout_pcs_to_pma;
|
306 |
|
|
wire [3:0] tx_digitalreset_in;
|
307 |
|
|
wire [3:0] tx_digitalreset_out;
|
308 |
|
|
wire [1199:0] tx_dprioin_wire;
|
309 |
|
|
wire [0:0] tx_forcedisp_wire;
|
310 |
|
|
wire [0:0] tx_invpolarity;
|
311 |
|
|
wire [0:0] tx_localrefclk;
|
312 |
|
|
wire [0:0] tx_phfiforeset;
|
313 |
|
|
wire [1799:0] tx_pmadprioin_wire;
|
314 |
|
|
wire [1799:0] tx_pmadprioout;
|
315 |
|
|
wire [0:0] tx_serialloopbackout;
|
316 |
|
|
wire [599:0] tx_txdprioout;
|
317 |
|
|
wire [0:0] txdetectrxout;
|
318 |
|
|
wire [0:0] w_cent_unit_dpriodisableout1w;
|
319 |
|
|
|
320 |
|
|
// synopsys translate_off
|
321 |
|
|
initial
|
322 |
|
|
fixedclk_div0quad0c = 0;
|
323 |
|
|
// synopsys translate_on
|
324 |
|
|
always @ ( posedge wire_fixedclk_div0quad0c_clk)
|
325 |
|
|
fixedclk_div0quad0c <= (~ fixedclk_div_in[0]);
|
326 |
|
|
assign
|
327 |
|
|
wire_fixedclk_div0quad0c_clk = fixedclk_in[0];
|
328 |
|
|
// synopsys translate_off
|
329 |
|
|
initial
|
330 |
|
|
fixedclk_div1quad0c = 0;
|
331 |
|
|
// synopsys translate_on
|
332 |
|
|
always @ ( posedge wire_fixedclk_div1quad0c_clk)
|
333 |
|
|
fixedclk_div1quad0c <= (~ fixedclk_div_in[1]);
|
334 |
|
|
assign
|
335 |
|
|
wire_fixedclk_div1quad0c_clk = fixedclk_in[1];
|
336 |
|
|
// synopsys translate_off
|
337 |
|
|
initial
|
338 |
|
|
fixedclk_div2quad0c = 0;
|
339 |
|
|
// synopsys translate_on
|
340 |
|
|
always @ ( posedge wire_fixedclk_div2quad0c_clk)
|
341 |
|
|
fixedclk_div2quad0c <= (~ fixedclk_div_in[2]);
|
342 |
|
|
assign
|
343 |
|
|
wire_fixedclk_div2quad0c_clk = fixedclk_in[2];
|
344 |
|
|
// synopsys translate_off
|
345 |
|
|
initial
|
346 |
|
|
fixedclk_div3quad0c = 0;
|
347 |
|
|
// synopsys translate_on
|
348 |
|
|
always @ ( posedge wire_fixedclk_div3quad0c_clk)
|
349 |
|
|
fixedclk_div3quad0c <= (~ fixedclk_div_in[3]);
|
350 |
|
|
assign
|
351 |
|
|
wire_fixedclk_div3quad0c_clk = fixedclk_in[3];
|
352 |
|
|
// synopsys translate_off
|
353 |
|
|
initial
|
354 |
|
|
fixedclk_div4quad0c = 0;
|
355 |
|
|
// synopsys translate_on
|
356 |
|
|
always @ ( posedge wire_fixedclk_div4quad0c_clk)
|
357 |
|
|
fixedclk_div4quad0c <= (~ fixedclk_div_in[4]);
|
358 |
|
|
assign
|
359 |
|
|
wire_fixedclk_div4quad0c_clk = fixedclk_in[4];
|
360 |
|
|
// synopsys translate_off
|
361 |
|
|
initial
|
362 |
|
|
fixedclk_div5quad0c = 0;
|
363 |
|
|
// synopsys translate_on
|
364 |
|
|
always @ ( posedge wire_fixedclk_div5quad0c_clk)
|
365 |
|
|
fixedclk_div5quad0c <= (~ fixedclk_div_in[5]);
|
366 |
|
|
assign
|
367 |
|
|
wire_fixedclk_div5quad0c_clk = fixedclk_in[5];
|
368 |
|
|
// synopsys translate_off
|
369 |
|
|
initial
|
370 |
|
|
reconfig_togxb_busy_reg = 0;
|
371 |
|
|
// synopsys translate_on
|
372 |
|
|
always @ ( negedge fixedclk)
|
373 |
|
|
reconfig_togxb_busy_reg <= {reconfig_togxb_busy_reg[0], reconfig_togxb_busy};
|
374 |
|
|
stratixiv_hssi_calibration_block cal_blk0
|
375 |
|
|
(
|
376 |
|
|
.calibrationstatus(),
|
377 |
|
|
.clk(cal_blk_clk),
|
378 |
|
|
.enabletestbus(1'b1),
|
379 |
|
|
.nonusertocmu(wire_cal_blk0_nonusertocmu),
|
380 |
|
|
.powerdn(cal_blk_powerdown)
|
381 |
|
|
`ifndef FORMAL_VERIFICATION
|
382 |
|
|
// synopsys translate_off
|
383 |
|
|
`endif
|
384 |
|
|
,
|
385 |
|
|
.testctrl(1'b0)
|
386 |
|
|
`ifndef FORMAL_VERIFICATION
|
387 |
|
|
// synopsys translate_on
|
388 |
|
|
`endif
|
389 |
|
|
);
|
390 |
|
|
stratixiv_hssi_clock_divider ch_clk_div0
|
391 |
|
|
(
|
392 |
|
|
.analogfastrefclkout(wire_ch_clk_div0_analogfastrefclkout),
|
393 |
|
|
.analogfastrefclkoutshifted(),
|
394 |
|
|
.analogrefclkout(wire_ch_clk_div0_analogrefclkout),
|
395 |
|
|
.analogrefclkoutshifted(),
|
396 |
|
|
.analogrefclkpulse(wire_ch_clk_div0_analogrefclkpulse),
|
397 |
|
|
.analogrefclkpulseshifted(),
|
398 |
|
|
.clk0in(pll0_out[3:0]),
|
399 |
|
|
.coreclkout(),
|
400 |
|
|
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
|
401 |
|
|
.dprioin(cent_unit_cmudividerdprioout[99:0]),
|
402 |
|
|
.dprioout(wire_ch_clk_div0_dprioout),
|
403 |
|
|
.quadreset(cent_unit_quadresetout[0]),
|
404 |
|
|
.rateswitchbaseclock(),
|
405 |
|
|
.rateswitchdone(),
|
406 |
|
|
.rateswitchout(),
|
407 |
|
|
.refclkout()
|
408 |
|
|
`ifndef FORMAL_VERIFICATION
|
409 |
|
|
// synopsys translate_off
|
410 |
|
|
`endif
|
411 |
|
|
,
|
412 |
|
|
.clk1in({4{1'b0}}),
|
413 |
|
|
.powerdn(1'b0),
|
414 |
|
|
.rateswitch(1'b0),
|
415 |
|
|
.rateswitchbaseclkin({2{1'b0}}),
|
416 |
|
|
.rateswitchdonein({2{1'b0}}),
|
417 |
|
|
.refclkdig(1'b0),
|
418 |
|
|
.refclkin({2{1'b0}}),
|
419 |
|
|
.vcobypassin(1'b0)
|
420 |
|
|
`ifndef FORMAL_VERIFICATION
|
421 |
|
|
// synopsys translate_on
|
422 |
|
|
`endif
|
423 |
|
|
);
|
424 |
|
|
defparam
|
425 |
|
|
ch_clk_div0.channel_num = ((starting_channel_number + 0) % 4),
|
426 |
|
|
ch_clk_div0.divide_by = 5,
|
427 |
|
|
ch_clk_div0.divider_type = "CHANNEL_REGULAR",
|
428 |
|
|
ch_clk_div0.effective_data_rate = "1250.0 Mbps",
|
429 |
|
|
ch_clk_div0.enable_dynamic_divider = "false",
|
430 |
|
|
ch_clk_div0.enable_refclk_out = "false",
|
431 |
|
|
ch_clk_div0.inclk_select = 0,
|
432 |
|
|
ch_clk_div0.logical_channel_address = (starting_channel_number + 0),
|
433 |
|
|
ch_clk_div0.pre_divide_by = 1,
|
434 |
|
|
ch_clk_div0.select_local_rate_switch_done = "false",
|
435 |
|
|
ch_clk_div0.sim_analogfastrefclkout_phase_shift = 0,
|
436 |
|
|
ch_clk_div0.sim_analogrefclkout_phase_shift = 0,
|
437 |
|
|
ch_clk_div0.sim_coreclkout_phase_shift = 0,
|
438 |
|
|
ch_clk_div0.sim_refclkout_phase_shift = 0,
|
439 |
|
|
ch_clk_div0.use_coreclk_out_post_divider = "false",
|
440 |
|
|
ch_clk_div0.use_refclk_post_divider = "false",
|
441 |
|
|
ch_clk_div0.use_vco_bypass = "false",
|
442 |
|
|
ch_clk_div0.lpm_type = "stratixiv_hssi_clock_divider";
|
443 |
|
|
stratixiv_hssi_cmu cent_unit0
|
444 |
|
|
(
|
445 |
|
|
.adet({4{1'b0}}),
|
446 |
|
|
.alignstatus(),
|
447 |
|
|
.autospdx4configsel(),
|
448 |
|
|
.autospdx4rateswitchout(),
|
449 |
|
|
.autospdx4spdchg(),
|
450 |
|
|
.clkdivpowerdn(),
|
451 |
|
|
.cmudividerdprioin({clk_div_cmudividerdprioin[599:0]}),
|
452 |
|
|
.cmudividerdprioout(wire_cent_unit0_cmudividerdprioout),
|
453 |
|
|
.cmuplldprioin(pll_cmuplldprioout[1799:0]),
|
454 |
|
|
.cmuplldprioout(wire_cent_unit0_cmuplldprioout),
|
455 |
|
|
.digitaltestout(),
|
456 |
|
|
.dpclk(reconfig_clk),
|
457 |
|
|
.dpriodisable(reconfig_togxb_disable),
|
458 |
|
|
.dpriodisableout(wire_cent_unit0_dpriodisableout),
|
459 |
|
|
.dprioin(reconfig_togxb_in),
|
460 |
|
|
.dprioload(reconfig_togxb_load),
|
461 |
|
|
.dpriooe(),
|
462 |
|
|
.dprioout(wire_cent_unit0_dprioout),
|
463 |
|
|
.enabledeskew(),
|
464 |
|
|
.extra10gout(),
|
465 |
|
|
.fiforesetrd(),
|
466 |
|
|
.fixedclk({{5{1'b0}}, fixedclk_to_cmu[0]}),
|
467 |
|
|
.lccmutestbus(),
|
468 |
|
|
.nonuserfromcal(nonusertocmu_out[0]),
|
469 |
|
|
.phfifiox4ptrsreset(),
|
470 |
|
|
.pllpowerdn(wire_cent_unit0_pllpowerdn),
|
471 |
|
|
.pllresetout(wire_cent_unit0_pllresetout),
|
472 |
|
|
.quadreset(gxb_powerdown[0]),
|
473 |
|
|
.quadresetout(wire_cent_unit0_quadresetout),
|
474 |
|
|
.rdalign({4{1'b0}}),
|
475 |
|
|
.rdenablesync(1'b0),
|
476 |
|
|
.recovclk(1'b0),
|
477 |
|
|
.refclkdividerdprioin({2{1'b0}}),
|
478 |
|
|
.refclkdividerdprioout(),
|
479 |
|
|
.rxadcepowerdown(),
|
480 |
|
|
.rxadceresetout(),
|
481 |
|
|
.rxanalogreset({{2{1'b0}}, rx_analogreset_in[3:0]}),
|
482 |
|
|
.rxanalogresetout(wire_cent_unit0_rxanalogresetout),
|
483 |
|
|
.rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
|
484 |
|
|
.rxcruresetout(wire_cent_unit0_rxcruresetout),
|
485 |
|
|
.rxctrl({4{1'b0}}),
|
486 |
|
|
.rxctrlout(),
|
487 |
|
|
.rxdatain({32{1'b0}}),
|
488 |
|
|
.rxdataout(),
|
489 |
|
|
.rxdatavalid({4{1'b0}}),
|
490 |
|
|
.rxdigitalreset({rx_digitalreset_in[3:0]}),
|
491 |
|
|
.rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
|
492 |
|
|
.rxibpowerdown(wire_cent_unit0_rxibpowerdown),
|
493 |
|
|
.rxpcsdprioin({cent_unit_rxpcsdprioin[1599:0]}),
|
494 |
|
|
.rxpcsdprioout(wire_cent_unit0_rxpcsdprioout),
|
495 |
|
|
.rxphfifox4byteselout(),
|
496 |
|
|
.rxphfifox4rdenableout(),
|
497 |
|
|
.rxphfifox4wrclkout(),
|
498 |
|
|
.rxphfifox4wrenableout(),
|
499 |
|
|
.rxpmadprioin({cent_unit_rxpmadprioin[1799:0]}),
|
500 |
|
|
.rxpmadprioout(wire_cent_unit0_rxpmadprioout),
|
501 |
|
|
.rxpowerdown({{2{1'b0}}, rx_powerdown_in[3:0]}),
|
502 |
|
|
.rxrunningdisp({4{1'b0}}),
|
503 |
|
|
.scanout(),
|
504 |
|
|
.syncstatus({4{1'b0}}),
|
505 |
|
|
.testout(),
|
506 |
|
|
.txanalogresetout(wire_cent_unit0_txanalogresetout),
|
507 |
|
|
.txctrl({4{1'b0}}),
|
508 |
|
|
.txctrlout(wire_cent_unit0_txctrlout),
|
509 |
|
|
.txdatain({32{1'b0}}),
|
510 |
|
|
.txdataout(wire_cent_unit0_txdataout),
|
511 |
|
|
.txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
|
512 |
|
|
.txdigitalreset({tx_digitalreset_in[3:0]}),
|
513 |
|
|
.txdigitalresetout(wire_cent_unit0_txdigitalresetout),
|
514 |
|
|
.txdividerpowerdown(),
|
515 |
|
|
.txobpowerdown(wire_cent_unit0_txobpowerdown),
|
516 |
|
|
.txpcsdprioin({cent_unit_tx_dprioin[599:0]}),
|
517 |
|
|
.txpcsdprioout(wire_cent_unit0_txpcsdprioout),
|
518 |
|
|
.txphfifox4byteselout(),
|
519 |
|
|
.txphfifox4rdclkout(),
|
520 |
|
|
.txphfifox4rdenableout(),
|
521 |
|
|
.txphfifox4wrenableout(),
|
522 |
|
|
.txpllreset({{1{1'b0}}, pll_powerdown[0]}),
|
523 |
|
|
.txpmadprioin({cent_unit_txpmadprioin[1799:0]}),
|
524 |
|
|
.txpmadprioout(wire_cent_unit0_txpmadprioout)
|
525 |
|
|
`ifndef FORMAL_VERIFICATION
|
526 |
|
|
// synopsys translate_off
|
527 |
|
|
`endif
|
528 |
|
|
,
|
529 |
|
|
.extra10gin({7{1'b0}}),
|
530 |
|
|
.lccmurtestbussel({3{1'b0}}),
|
531 |
|
|
.pmacramtest(1'b0),
|
532 |
|
|
.rateswitch(1'b0),
|
533 |
|
|
.rateswitchdonein(1'b0),
|
534 |
|
|
.rxclk(1'b0),
|
535 |
|
|
.rxcoreclk(1'b0),
|
536 |
|
|
.rxphfifordenable(1'b1),
|
537 |
|
|
.rxphfiforeset(1'b0),
|
538 |
|
|
.rxphfifowrdisable(1'b0),
|
539 |
|
|
.scanclk(1'b0),
|
540 |
|
|
.scanin({23{1'b0}}),
|
541 |
|
|
.scanmode(1'b0),
|
542 |
|
|
.scanshift(1'b0),
|
543 |
|
|
.testin({10000{1'b0}}),
|
544 |
|
|
.txclk(1'b0),
|
545 |
|
|
.txcoreclk(1'b0),
|
546 |
|
|
.txphfiforddisable(1'b0),
|
547 |
|
|
.txphfiforeset(1'b0),
|
548 |
|
|
.txphfifowrenable(1'b0)
|
549 |
|
|
`ifndef FORMAL_VERIFICATION
|
550 |
|
|
// synopsys translate_on
|
551 |
|
|
`endif
|
552 |
|
|
);
|
553 |
|
|
defparam
|
554 |
|
|
cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
|
555 |
|
|
cent_unit0.auto_spd_phystatus_notify_count = 0,
|
556 |
|
|
cent_unit0.bonded_quad_mode = "none",
|
557 |
|
|
cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
|
558 |
|
|
cent_unit0.in_xaui_mode = "false",
|
559 |
|
|
cent_unit0.offset_all_errors_align = "false",
|
560 |
|
|
cent_unit0.pipe_auto_speed_nego_enable = "false",
|
561 |
|
|
cent_unit0.pipe_freq_scale_mode = "Frequency",
|
562 |
|
|
cent_unit0.pma_done_count = 249950,
|
563 |
|
|
cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
|
564 |
|
|
cent_unit0.rx0_auto_spd_self_switch_enable = "false",
|
565 |
|
|
cent_unit0.rx0_channel_bonding = "none",
|
566 |
|
|
cent_unit0.rx0_clk1_mux_select = "recovered clock",
|
567 |
|
|
cent_unit0.rx0_clk2_mux_select = "local reference clock",
|
568 |
|
|
cent_unit0.rx0_ph_fifo_reg_mode = "false",
|
569 |
|
|
cent_unit0.rx0_rd_clk_mux_select = "core clock",
|
570 |
|
|
cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
|
571 |
|
|
cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
|
572 |
|
|
cent_unit0.rx0_use_double_data_mode = "false",
|
573 |
|
|
cent_unit0.tx0_auto_spd_self_switch_enable = "false",
|
574 |
|
|
cent_unit0.tx0_channel_bonding = "none",
|
575 |
|
|
cent_unit0.tx0_ph_fifo_reg_mode = "false",
|
576 |
|
|
cent_unit0.tx0_rd_clk_mux_select = "cmu_clock_divider",
|
577 |
|
|
cent_unit0.tx0_use_double_data_mode = "false",
|
578 |
|
|
cent_unit0.tx0_wr_clk_mux_select = "core_clk",
|
579 |
|
|
cent_unit0.use_deskew_fifo = "false",
|
580 |
|
|
cent_unit0.vcceh_voltage = "Auto",
|
581 |
|
|
cent_unit0.lpm_type = "stratixiv_hssi_cmu";
|
582 |
|
|
stratixiv_hssi_pll rx_cdr_pll0
|
583 |
|
|
(
|
584 |
|
|
.areset(rx_rxcruresetout[0]),
|
585 |
|
|
.clk(wire_rx_cdr_pll0_clk),
|
586 |
|
|
.datain(rx_pma_dataout[0]),
|
587 |
|
|
.dataout(wire_rx_cdr_pll0_dataout),
|
588 |
|
|
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
|
589 |
|
|
.dprioin(rxpll_dprioin[299:0]),
|
590 |
|
|
.dprioout(wire_rx_cdr_pll0_dprioout),
|
591 |
|
|
.freqlocked(wire_rx_cdr_pll0_freqlocked),
|
592 |
|
|
.inclk({rx_cruclk_in[9:0]}),
|
593 |
|
|
.locked(wire_rx_cdr_pll0_locked),
|
594 |
|
|
.locktorefclk(rx_pma_locktorefout[0]),
|
595 |
|
|
.pfdfbclkout(),
|
596 |
|
|
.pfdrefclkout(wire_rx_cdr_pll0_pfdrefclkout),
|
597 |
|
|
.powerdown(cent_unit_rxcrupowerdn[0]),
|
598 |
|
|
.vcobypassout()
|
599 |
|
|
`ifndef FORMAL_VERIFICATION
|
600 |
|
|
// synopsys translate_off
|
601 |
|
|
`endif
|
602 |
|
|
,
|
603 |
|
|
.earlyeios(1'b0),
|
604 |
|
|
.extra10gin({6{1'b0}}),
|
605 |
|
|
.pfdfbclk(1'b0),
|
606 |
|
|
.rateswitch(1'b0)
|
607 |
|
|
`ifndef FORMAL_VERIFICATION
|
608 |
|
|
// synopsys translate_on
|
609 |
|
|
`endif
|
610 |
|
|
);
|
611 |
|
|
defparam
|
612 |
|
|
rx_cdr_pll0.bandwidth_type = "Medium",
|
613 |
|
|
rx_cdr_pll0.channel_num = ((starting_channel_number + 0) % 4),
|
614 |
|
|
rx_cdr_pll0.dprio_config_mode = 6'h00,
|
615 |
|
|
rx_cdr_pll0.effective_data_rate = "1250.0 Mbps",
|
616 |
|
|
rx_cdr_pll0.enable_dynamic_divider = "false",
|
617 |
|
|
rx_cdr_pll0.fast_lock_control = "false",
|
618 |
|
|
rx_cdr_pll0.inclk0_input_period = 8000,
|
619 |
|
|
rx_cdr_pll0.input_clock_frequency = "125.0 MHz",
|
620 |
|
|
rx_cdr_pll0.m = 5,
|
621 |
|
|
rx_cdr_pll0.n = 1,
|
622 |
|
|
rx_cdr_pll0.pfd_clk_select = 0,
|
623 |
|
|
rx_cdr_pll0.pll_type = "RX CDR",
|
624 |
|
|
rx_cdr_pll0.use_refclk_pin = "false",
|
625 |
|
|
rx_cdr_pll0.vco_post_scale = 4,
|
626 |
|
|
rx_cdr_pll0.lpm_type = "stratixiv_hssi_pll";
|
627 |
|
|
stratixiv_hssi_pll tx_pll0
|
628 |
|
|
(
|
629 |
|
|
.areset(pllreset_in[0]),
|
630 |
|
|
.clk(wire_tx_pll0_clk),
|
631 |
|
|
.dataout(),
|
632 |
|
|
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
|
633 |
|
|
.dprioin(pll0_dprioin[299:0]),
|
634 |
|
|
.dprioout(wire_tx_pll0_dprioout),
|
635 |
|
|
.freqlocked(),
|
636 |
|
|
.inclk({pll0_clkin[9:0]}),
|
637 |
|
|
.locked(wire_tx_pll0_locked),
|
638 |
|
|
.pfdfbclkout(),
|
639 |
|
|
.pfdrefclkout(),
|
640 |
|
|
.powerdown(pllpowerdn_in[0]),
|
641 |
|
|
.vcobypassout()
|
642 |
|
|
`ifndef FORMAL_VERIFICATION
|
643 |
|
|
// synopsys translate_off
|
644 |
|
|
`endif
|
645 |
|
|
,
|
646 |
|
|
.datain(1'b0),
|
647 |
|
|
.earlyeios(1'b0),
|
648 |
|
|
.extra10gin({6{1'b0}}),
|
649 |
|
|
.locktorefclk(1'b1),
|
650 |
|
|
.pfdfbclk(1'b0),
|
651 |
|
|
.rateswitch(1'b0)
|
652 |
|
|
`ifndef FORMAL_VERIFICATION
|
653 |
|
|
// synopsys translate_on
|
654 |
|
|
`endif
|
655 |
|
|
);
|
656 |
|
|
defparam
|
657 |
|
|
tx_pll0.bandwidth_type = "High",
|
658 |
|
|
tx_pll0.channel_num = 4,
|
659 |
|
|
tx_pll0.dprio_config_mode = 6'h00,
|
660 |
|
|
tx_pll0.inclk0_input_period = 8000,
|
661 |
|
|
tx_pll0.input_clock_frequency = "125.0 MHz",
|
662 |
|
|
tx_pll0.logical_tx_pll_number = 0,
|
663 |
|
|
tx_pll0.m = 5,
|
664 |
|
|
tx_pll0.n = 1,
|
665 |
|
|
tx_pll0.pfd_clk_select = 0,
|
666 |
|
|
tx_pll0.pfd_fb_select = "internal",
|
667 |
|
|
tx_pll0.pll_type = "CMU",
|
668 |
|
|
tx_pll0.use_refclk_pin = "false",
|
669 |
|
|
tx_pll0.vco_post_scale = 4,
|
670 |
|
|
tx_pll0.lpm_type = "stratixiv_hssi_pll";
|
671 |
|
|
stratixiv_hssi_rx_pcs receive_pcs0
|
672 |
|
|
(
|
673 |
|
|
.a1a2size(1'b0),
|
674 |
|
|
.a1a2sizeout(),
|
675 |
|
|
.a1detect(),
|
676 |
|
|
.a2detect(),
|
677 |
|
|
.adetectdeskew(),
|
678 |
|
|
.alignstatus(1'b0),
|
679 |
|
|
.alignstatussync(1'b0),
|
680 |
|
|
.alignstatussyncout(),
|
681 |
|
|
.autospdrateswitchout(),
|
682 |
|
|
.autospdspdchgout(),
|
683 |
|
|
.bistdone(),
|
684 |
|
|
.bisterr(),
|
685 |
|
|
.bitslipboundaryselectout(),
|
686 |
|
|
.byteorderalignstatus(),
|
687 |
|
|
.cdrctrlearlyeios(),
|
688 |
|
|
.cdrctrllocktorefcl((reconfig_togxb_busy | rx_locktorefclk[0])),
|
689 |
|
|
.cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
|
690 |
|
|
.clkout(wire_receive_pcs0_clkout),
|
691 |
|
|
.coreclk(rx_coreclk_in[0]),
|
692 |
|
|
.coreclkout(),
|
693 |
|
|
.ctrldetect(wire_receive_pcs0_ctrldetect),
|
694 |
|
|
.datain(rx_pma_recoverdataout_wire[19:0]),
|
695 |
|
|
.dataout(wire_receive_pcs0_dataout),
|
696 |
|
|
.dataoutfull(),
|
697 |
|
|
.digitalreset(rx_digitalreset_out[0]),
|
698 |
|
|
.digitaltestout(),
|
699 |
|
|
.disablefifordin(1'b0),
|
700 |
|
|
.disablefifordout(),
|
701 |
|
|
.disablefifowrin(1'b0),
|
702 |
|
|
.disablefifowrout(),
|
703 |
|
|
.disperr(wire_receive_pcs0_disperr),
|
704 |
|
|
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
|
705 |
|
|
.dprioin(rx_pcsdprioin_wire[399:0]),
|
706 |
|
|
.dprioout(wire_receive_pcs0_dprioout),
|
707 |
|
|
.enabledeskew(1'b0),
|
708 |
|
|
.enabyteord(1'b0),
|
709 |
|
|
.enapatternalign(rx_enapatternalign[0]),
|
710 |
|
|
.errdetect(wire_receive_pcs0_errdetect),
|
711 |
|
|
.fifordin(1'b0),
|
712 |
|
|
.fifordout(),
|
713 |
|
|
.fiforesetrd(1'b0),
|
714 |
|
|
.hipdataout(),
|
715 |
|
|
.hipdatavalid(),
|
716 |
|
|
.hipelecidle(),
|
717 |
|
|
.hipphydonestatus(),
|
718 |
|
|
.hipstatus(),
|
719 |
|
|
.invpol(1'b0),
|
720 |
|
|
.iqpphfifobyteselout(),
|
721 |
|
|
.iqpphfifoptrsresetout(),
|
722 |
|
|
.iqpphfifordenableout(),
|
723 |
|
|
.iqpphfifowrclkout(),
|
724 |
|
|
.iqpphfifowrenableout(),
|
725 |
|
|
.k1detect(),
|
726 |
|
|
.k2detect(),
|
727 |
|
|
.localrefclk(tx_localrefclk[0]),
|
728 |
|
|
.masterclk(1'b0),
|
729 |
|
|
.parallelfdbk({20{1'b0}}),
|
730 |
|
|
.patterndetect(wire_receive_pcs0_patterndetect),
|
731 |
|
|
.phfifobyteselout(),
|
732 |
|
|
.phfifobyteserdisableout(),
|
733 |
|
|
.phfifooverflow(),
|
734 |
|
|
.phfifoptrsresetout(),
|
735 |
|
|
.phfifordenable(rx_phfifordenable[0]),
|
736 |
|
|
.phfifordenableout(),
|
737 |
|
|
.phfiforeset(rx_phfiforeset[0]),
|
738 |
|
|
.phfiforesetout(),
|
739 |
|
|
.phfifounderflow(),
|
740 |
|
|
.phfifowrclkout(),
|
741 |
|
|
.phfifowrdisable(rx_phfifowrdisable[0]),
|
742 |
|
|
.phfifowrdisableout(),
|
743 |
|
|
.phfifowrenableout(),
|
744 |
|
|
.pipebufferstat(),
|
745 |
|
|
.pipedatavalid(),
|
746 |
|
|
.pipeelecidle(),
|
747 |
|
|
.pipephydonestatus(),
|
748 |
|
|
.pipepowerdown({2{1'b0}}),
|
749 |
|
|
.pipepowerstate({4{1'b0}}),
|
750 |
|
|
.pipestatetransdoneout(),
|
751 |
|
|
.pipestatus(),
|
752 |
|
|
.prbscidenable(rx_prbscidenable[0]),
|
753 |
|
|
.quadreset(cent_unit_quadresetout[0]),
|
754 |
|
|
.rateswitchout(),
|
755 |
|
|
.rdalign(),
|
756 |
|
|
.recoveredclk(rx_pma_clockout[0]),
|
757 |
|
|
.revbitorderwa(1'b0),
|
758 |
|
|
.revbyteorderwa(1'b0),
|
759 |
|
|
.revparallelfdbkdata(),
|
760 |
|
|
.rlv(wire_receive_pcs0_rlv),
|
761 |
|
|
.rmfifoalmostempty(),
|
762 |
|
|
.rmfifoalmostfull(),
|
763 |
|
|
.rmfifodatadeleted(wire_receive_pcs0_rmfifodatadeleted),
|
764 |
|
|
.rmfifodatainserted(wire_receive_pcs0_rmfifodatainserted),
|
765 |
|
|
.rmfifoempty(),
|
766 |
|
|
.rmfifofull(),
|
767 |
|
|
.rmfifordena(1'b0),
|
768 |
|
|
.rmfiforeset(rx_rmfiforeset[0]),
|
769 |
|
|
.rmfifowrena(1'b0),
|
770 |
|
|
.runningdisp(wire_receive_pcs0_runningdisp),
|
771 |
|
|
.rxdetectvalid(1'b0),
|
772 |
|
|
.rxfound({2{1'b0}}),
|
773 |
|
|
.signaldetect(),
|
774 |
|
|
.syncstatus(wire_receive_pcs0_syncstatus),
|
775 |
|
|
.syncstatusdeskew(),
|
776 |
|
|
.xauidelcondmetout(),
|
777 |
|
|
.xauififoovrout(),
|
778 |
|
|
.xauiinsertincompleteout(),
|
779 |
|
|
.xauilatencycompout(),
|
780 |
|
|
.xgmctrldet(),
|
781 |
|
|
.xgmctrlin(1'b0),
|
782 |
|
|
.xgmdatain({8{1'b0}}),
|
783 |
|
|
.xgmdataout(),
|
784 |
|
|
.xgmdatavalid(),
|
785 |
|
|
.xgmrunningdisp()
|
786 |
|
|
`ifndef FORMAL_VERIFICATION
|
787 |
|
|
// synopsys translate_off
|
788 |
|
|
`endif
|
789 |
|
|
,
|
790 |
|
|
.autospdxnconfigsel({3{1'b0}}),
|
791 |
|
|
.autospdxnspdchg({3{1'b0}}),
|
792 |
|
|
.bitslip(1'b0),
|
793 |
|
|
.elecidleinfersel({3{1'b0}}),
|
794 |
|
|
.grayelecidleinferselfromtx({3{1'b0}}),
|
795 |
|
|
.hip8b10binvpolarity(1'b0),
|
796 |
|
|
.hipelecidleinfersel({3{1'b0}}),
|
797 |
|
|
.hippowerdown({2{1'b0}}),
|
798 |
|
|
.hiprateswitch(1'b0),
|
799 |
|
|
.iqpautospdxnspgchg({2{1'b0}}),
|
800 |
|
|
.iqpphfifoxnbytesel({2{1'b0}}),
|
801 |
|
|
.iqpphfifoxnptrsreset({2{1'b0}}),
|
802 |
|
|
.iqpphfifoxnrdenable({2{1'b0}}),
|
803 |
|
|
.iqpphfifoxnwrclk({2{1'b0}}),
|
804 |
|
|
.iqpphfifoxnwrenable({2{1'b0}}),
|
805 |
|
|
.phfifox4bytesel(1'b0),
|
806 |
|
|
.phfifox4rdenable(1'b0),
|
807 |
|
|
.phfifox4wrclk(1'b0),
|
808 |
|
|
.phfifox4wrenable(1'b0),
|
809 |
|
|
.phfifox8bytesel(1'b0),
|
810 |
|
|
.phfifox8rdenable(1'b0),
|
811 |
|
|
.phfifox8wrclk(1'b0),
|
812 |
|
|
.phfifox8wrenable(1'b0),
|
813 |
|
|
.phfifoxnbytesel({3{1'b0}}),
|
814 |
|
|
.phfifoxnptrsreset({3{1'b0}}),
|
815 |
|
|
.phfifoxnrdenable({3{1'b0}}),
|
816 |
|
|
.phfifoxnwrclk({3{1'b0}}),
|
817 |
|
|
.phfifoxnwrenable({3{1'b0}}),
|
818 |
|
|
.pipe8b10binvpolarity(1'b0),
|
819 |
|
|
.pipeenrevparallellpbkfromtx(1'b0),
|
820 |
|
|
.pmatestbusin({8{1'b0}}),
|
821 |
|
|
.powerdn({2{1'b0}}),
|
822 |
|
|
.ppmdetectdividedclk(1'b0),
|
823 |
|
|
.ppmdetectrefclk(1'b0),
|
824 |
|
|
.rateswitch(1'b0),
|
825 |
|
|
.rateswitchisdone(1'b0),
|
826 |
|
|
.rateswitchxndone(1'b0),
|
827 |
|
|
.refclk(1'b0),
|
828 |
|
|
.rxelecidlerateswitch(1'b0),
|
829 |
|
|
.signaldetected(1'b0),
|
830 |
|
|
.wareset(1'b0),
|
831 |
|
|
.xauidelcondmet(1'b0),
|
832 |
|
|
.xauififoovr(1'b0),
|
833 |
|
|
.xauiinsertincomplete(1'b0),
|
834 |
|
|
.xauilatencycomp(1'b0)
|
835 |
|
|
`ifndef FORMAL_VERIFICATION
|
836 |
|
|
// synopsys translate_on
|
837 |
|
|
`endif
|
838 |
|
|
);
|
839 |
|
|
defparam
|
840 |
|
|
receive_pcs0.align_pattern = "0101111100",
|
841 |
|
|
receive_pcs0.align_pattern_length = 10,
|
842 |
|
|
receive_pcs0.align_to_deskew_pattern_pos_disp_only = "false",
|
843 |
|
|
receive_pcs0.allow_align_polarity_inversion = "false",
|
844 |
|
|
receive_pcs0.allow_pipe_polarity_inversion = "false",
|
845 |
|
|
receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
|
846 |
|
|
receive_pcs0.auto_spd_phystatus_notify_count = 0,
|
847 |
|
|
receive_pcs0.auto_spd_self_switch_enable = "false",
|
848 |
|
|
receive_pcs0.bit_slip_enable = "false",
|
849 |
|
|
receive_pcs0.byte_order_double_data_mode_mask_enable = "false",
|
850 |
|
|
receive_pcs0.byte_order_mode = "none",
|
851 |
|
|
receive_pcs0.byte_order_pad_pattern = "0",
|
852 |
|
|
receive_pcs0.byte_order_pattern = "0",
|
853 |
|
|
receive_pcs0.byte_order_pld_ctrl_enable = "false",
|
854 |
|
|
receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
|
855 |
|
|
receive_pcs0.cdrctrl_enable = "false",
|
856 |
|
|
receive_pcs0.cdrctrl_rxvalid_mask = "false",
|
857 |
|
|
receive_pcs0.channel_bonding = "none",
|
858 |
|
|
receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
|
859 |
|
|
receive_pcs0.channel_width = 8,
|
860 |
|
|
receive_pcs0.clk1_mux_select = "recovered clock",
|
861 |
|
|
receive_pcs0.clk2_mux_select = "local reference clock",
|
862 |
|
|
receive_pcs0.core_clock_0ppm = "false",
|
863 |
|
|
receive_pcs0.datapath_low_latency_mode = "false",
|
864 |
|
|
receive_pcs0.datapath_protocol = "basic",
|
865 |
|
|
receive_pcs0.dec_8b_10b_compatibility_mode = "true",
|
866 |
|
|
receive_pcs0.dec_8b_10b_mode = "normal",
|
867 |
|
|
receive_pcs0.dec_8b_10b_polarity_inv_enable = "false",
|
868 |
|
|
receive_pcs0.deskew_pattern = "0",
|
869 |
|
|
receive_pcs0.disable_auto_idle_insertion = "true",
|
870 |
|
|
receive_pcs0.disable_running_disp_in_word_align = "false",
|
871 |
|
|
receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
|
872 |
|
|
receive_pcs0.dprio_config_mode = 6'h01,
|
873 |
|
|
receive_pcs0.elec_idle_infer_enable = "false",
|
874 |
|
|
receive_pcs0.elec_idle_num_com_detect = 3,
|
875 |
|
|
receive_pcs0.enable_bit_reversal = "false",
|
876 |
|
|
receive_pcs0.enable_deep_align = "false",
|
877 |
|
|
receive_pcs0.enable_deep_align_byte_swap = "false",
|
878 |
|
|
receive_pcs0.enable_self_test_mode = "false",
|
879 |
|
|
receive_pcs0.enable_true_complement_match_in_word_align = "false",
|
880 |
|
|
receive_pcs0.force_signal_detect_dig = "true",
|
881 |
|
|
receive_pcs0.hip_enable = "false",
|
882 |
|
|
receive_pcs0.infiniband_invalid_code = 0,
|
883 |
|
|
receive_pcs0.insert_pad_on_underflow = "false",
|
884 |
|
|
receive_pcs0.logical_channel_address = (starting_channel_number + 0),
|
885 |
|
|
receive_pcs0.num_align_code_groups_in_ordered_set = 1,
|
886 |
|
|
receive_pcs0.num_align_cons_good_data = 4,
|
887 |
|
|
receive_pcs0.num_align_cons_pat = 3,
|
888 |
|
|
receive_pcs0.num_align_loss_sync_error = 4,
|
889 |
|
|
receive_pcs0.ph_fifo_low_latency_enable = "true",
|
890 |
|
|
receive_pcs0.ph_fifo_reg_mode = "false",
|
891 |
|
|
receive_pcs0.ph_fifo_xn_mapping0 = "none",
|
892 |
|
|
receive_pcs0.ph_fifo_xn_mapping1 = "none",
|
893 |
|
|
receive_pcs0.ph_fifo_xn_mapping2 = "none",
|
894 |
|
|
receive_pcs0.ph_fifo_xn_select = 1,
|
895 |
|
|
receive_pcs0.pipe_auto_speed_nego_enable = "false",
|
896 |
|
|
receive_pcs0.pipe_freq_scale_mode = "Frequency",
|
897 |
|
|
receive_pcs0.pma_done_count = 249950,
|
898 |
|
|
receive_pcs0.protocol_hint = "gige",
|
899 |
|
|
receive_pcs0.rate_match_almost_empty_threshold = 11,
|
900 |
|
|
receive_pcs0.rate_match_almost_full_threshold = 13,
|
901 |
|
|
receive_pcs0.rate_match_back_to_back = "true",
|
902 |
|
|
receive_pcs0.rate_match_delete_threshold = 13,
|
903 |
|
|
receive_pcs0.rate_match_empty_threshold = 5,
|
904 |
|
|
receive_pcs0.rate_match_fifo_mode = "true",
|
905 |
|
|
receive_pcs0.rate_match_full_threshold = 20,
|
906 |
|
|
receive_pcs0.rate_match_insert_threshold = 11,
|
907 |
|
|
receive_pcs0.rate_match_ordered_set_based = "true",
|
908 |
|
|
receive_pcs0.rate_match_pattern1 = "10100010010101111100",
|
909 |
|
|
receive_pcs0.rate_match_pattern2 = "10101011011010000011",
|
910 |
|
|
receive_pcs0.rate_match_pattern_size = 20,
|
911 |
|
|
receive_pcs0.rate_match_reset_enable = "false",
|
912 |
|
|
receive_pcs0.rate_match_skip_set_based = "false",
|
913 |
|
|
receive_pcs0.rate_match_start_threshold = 7,
|
914 |
|
|
receive_pcs0.rd_clk_mux_select = "core clock",
|
915 |
|
|
receive_pcs0.recovered_clk_mux_select = "recovered clock",
|
916 |
|
|
receive_pcs0.run_length = 5,
|
917 |
|
|
receive_pcs0.run_length_enable = "true",
|
918 |
|
|
receive_pcs0.rx_detect_bypass = "false",
|
919 |
|
|
receive_pcs0.rx_phfifo_wait_cnt = 15,
|
920 |
|
|
receive_pcs0.rxstatus_error_report_mode = 0,
|
921 |
|
|
receive_pcs0.self_test_mode = "incremental",
|
922 |
|
|
receive_pcs0.use_alignment_state_machine = "true",
|
923 |
|
|
receive_pcs0.use_deserializer_double_data_mode = "false",
|
924 |
|
|
receive_pcs0.use_deskew_fifo = "false",
|
925 |
|
|
receive_pcs0.use_double_data_mode = "false",
|
926 |
|
|
receive_pcs0.use_parallel_loopback = "false",
|
927 |
|
|
receive_pcs0.use_rising_edge_triggered_pattern_align = "false",
|
928 |
|
|
receive_pcs0.lpm_type = "stratixiv_hssi_rx_pcs";
|
929 |
|
|
stratixiv_hssi_rx_pma receive_pma0
|
930 |
|
|
(
|
931 |
|
|
.adaptdone(),
|
932 |
|
|
.analogtestbus(wire_receive_pma0_analogtestbus),
|
933 |
|
|
.clockout(wire_receive_pma0_clockout),
|
934 |
|
|
.datain(rx_datain[0]),
|
935 |
|
|
.dataout(wire_receive_pma0_dataout),
|
936 |
|
|
.dataoutfull(),
|
937 |
|
|
.deserclock(rx_deserclock_in[3:0]),
|
938 |
|
|
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
|
939 |
|
|
.dprioin(rx_pmadprioin_wire[299:0]),
|
940 |
|
|
.dprioout(wire_receive_pma0_dprioout),
|
941 |
|
|
.freqlock(1'b0),
|
942 |
|
|
.ignorephslck(1'b0),
|
943 |
|
|
.locktodata(rx_locktodata_wire[0]),
|
944 |
|
|
.locktoref(rx_locktorefclk_wire[0]),
|
945 |
|
|
.locktorefout(wire_receive_pma0_locktorefout),
|
946 |
|
|
.offsetcancellationen(1'b0),
|
947 |
|
|
.plllocked(rx_plllocked_wire[0]),
|
948 |
|
|
.powerdn(cent_unit_rxibpowerdn[0]),
|
949 |
|
|
.ppmdetectclkrel(),
|
950 |
|
|
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
|
951 |
|
|
.recoverdatain(pll_ch_dataout_wire[1:0]),
|
952 |
|
|
.recoverdataout(wire_receive_pma0_recoverdataout),
|
953 |
|
|
.reverselpbkout(),
|
954 |
|
|
.revserialfdbkout(),
|
955 |
|
|
.rxpmareset(rx_analogreset_out[0]),
|
956 |
|
|
.seriallpbken(rx_seriallpbken[0]),
|
957 |
|
|
.seriallpbkin(tx_serialloopbackout[0]),
|
958 |
|
|
.signaldetect(wire_receive_pma0_signaldetect),
|
959 |
|
|
.testbussel(4'b0110)
|
960 |
|
|
`ifndef FORMAL_VERIFICATION
|
961 |
|
|
// synopsys translate_off
|
962 |
|
|
`endif
|
963 |
|
|
,
|
964 |
|
|
.adaptcapture(1'b0),
|
965 |
|
|
.adcepowerdn(1'b0),
|
966 |
|
|
.adcereset(1'b0),
|
967 |
|
|
.adcestandby(1'b0),
|
968 |
|
|
.extra10gin({38{1'b0}}),
|
969 |
|
|
.ppmdetectdividedclk(1'b0)
|
970 |
|
|
`ifndef FORMAL_VERIFICATION
|
971 |
|
|
// synopsys translate_on
|
972 |
|
|
`endif
|
973 |
|
|
);
|
974 |
|
|
defparam
|
975 |
|
|
receive_pma0.adaptive_equalization_mode = "none",
|
976 |
|
|
receive_pma0.allow_serial_loopback = "true",
|
977 |
|
|
receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
|
978 |
|
|
receive_pma0.channel_type = "auto",
|
979 |
|
|
receive_pma0.common_mode = "0.82V",
|
980 |
|
|
receive_pma0.deserialization_factor = 10,
|
981 |
|
|
receive_pma0.dprio_config_mode = 6'h01,
|
982 |
|
|
receive_pma0.enable_ltd = "false",
|
983 |
|
|
receive_pma0.enable_ltr = "false",
|
984 |
|
|
receive_pma0.eq_dc_gain = 0,
|
985 |
|
|
receive_pma0.eqa_ctrl = 0,
|
986 |
|
|
receive_pma0.eqb_ctrl = 0,
|
987 |
|
|
receive_pma0.eqc_ctrl = 0,
|
988 |
|
|
receive_pma0.eqd_ctrl = 0,
|
989 |
|
|
receive_pma0.eqv_ctrl = 0,
|
990 |
|
|
receive_pma0.eyemon_bandwidth = 0,
|
991 |
|
|
receive_pma0.force_signal_detect = "true",
|
992 |
|
|
receive_pma0.logical_channel_address = (starting_channel_number + 0),
|
993 |
|
|
receive_pma0.low_speed_test_select = 0,
|
994 |
|
|
receive_pma0.offset_cancellation = 1,
|
995 |
|
|
receive_pma0.ppmselect = 32,
|
996 |
|
|
receive_pma0.protocol_hint = "gige",
|
997 |
|
|
receive_pma0.send_direct_reverse_serial_loopback = "None",
|
998 |
|
|
receive_pma0.signal_detect_hysteresis = 2,
|
999 |
|
|
receive_pma0.signal_detect_hysteresis_valid_threshold = 1,
|
1000 |
|
|
receive_pma0.signal_detect_loss_threshold = 1,
|
1001 |
|
|
receive_pma0.termination = "OCT 100 Ohms",
|
1002 |
|
|
receive_pma0.use_deser_double_data_width = "false",
|
1003 |
|
|
receive_pma0.use_external_termination = "false",
|
1004 |
|
|
receive_pma0.use_pma_direct = "false",
|
1005 |
|
|
receive_pma0.lpm_type = "stratixiv_hssi_rx_pma";
|
1006 |
|
|
stratixiv_hssi_tx_pcs transmit_pcs0
|
1007 |
|
|
(
|
1008 |
|
|
.clkout(wire_transmit_pcs0_clkout),
|
1009 |
|
|
.coreclk(tx_coreclk_in[0]),
|
1010 |
|
|
.coreclkout(),
|
1011 |
|
|
.ctrlenable({{3{1'b0}}, tx_ctrlenable[0]}),
|
1012 |
|
|
.datain({{32{1'b0}}, tx_datain_wire[7:0]}),
|
1013 |
|
|
.datainfull({44{1'b0}}),
|
1014 |
|
|
.dataout(wire_transmit_pcs0_dataout),
|
1015 |
|
|
.detectrxloop(1'b0),
|
1016 |
|
|
.digitalreset(tx_digitalreset_out[0]),
|
1017 |
|
|
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
|
1018 |
|
|
.dprioin(tx_dprioin_wire[149:0]),
|
1019 |
|
|
.dprioout(wire_transmit_pcs0_dprioout),
|
1020 |
|
|
.enrevparallellpbk(1'b0),
|
1021 |
|
|
.forcedisp({{3{1'b0}}, tx_forcedisp_wire[0]}),
|
1022 |
|
|
.forcedispcompliance(1'b0),
|
1023 |
|
|
.forceelecidleout(wire_transmit_pcs0_forceelecidleout),
|
1024 |
|
|
.grayelecidleinferselout(),
|
1025 |
|
|
.hiptxclkout(),
|
1026 |
|
|
.invpol(tx_invpolarity[0]),
|
1027 |
|
|
.iqpphfifobyteselout(),
|
1028 |
|
|
.iqpphfifordclkout(),
|
1029 |
|
|
.iqpphfifordenableout(),
|
1030 |
|
|
.iqpphfifowrenableout(),
|
1031 |
|
|
.localrefclk(tx_localrefclk[0]),
|
1032 |
|
|
.parallelfdbkout(),
|
1033 |
|
|
.phfifobyteselout(),
|
1034 |
|
|
.phfifooverflow(),
|
1035 |
|
|
.phfifordclkout(),
|
1036 |
|
|
.phfiforddisable(1'b0),
|
1037 |
|
|
.phfiforddisableout(),
|
1038 |
|
|
.phfifordenableout(),
|
1039 |
|
|
.phfiforeset(tx_phfiforeset[0]),
|
1040 |
|
|
.phfiforesetout(),
|
1041 |
|
|
.phfifounderflow(),
|
1042 |
|
|
.phfifowrenable(1'b1),
|
1043 |
|
|
.phfifowrenableout(),
|
1044 |
|
|
.pipeenrevparallellpbkout(),
|
1045 |
|
|
.pipepowerdownout(),
|
1046 |
|
|
.pipepowerstateout(),
|
1047 |
|
|
.pipestatetransdone(1'b0),
|
1048 |
|
|
.powerdn({2{1'b0}}),
|
1049 |
|
|
.quadreset(cent_unit_quadresetout[0]),
|
1050 |
|
|
.rateswitchout(),
|
1051 |
|
|
.rdenablesync(),
|
1052 |
|
|
.revparallelfdbk({20{1'b0}}),
|
1053 |
|
|
.txdetectrx(wire_transmit_pcs0_txdetectrx),
|
1054 |
|
|
.xgmctrl(cent_unit_txctrlout[0]),
|
1055 |
|
|
.xgmctrlenable(),
|
1056 |
|
|
.xgmdatain(cent_unit_tx_xgmdataout[7:0]),
|
1057 |
|
|
.xgmdataout()
|
1058 |
|
|
`ifndef FORMAL_VERIFICATION
|
1059 |
|
|
// synopsys translate_off
|
1060 |
|
|
`endif
|
1061 |
|
|
,
|
1062 |
|
|
.bitslipboundaryselect({5{1'b0}}),
|
1063 |
|
|
.dispval({4{1'b0}}),
|
1064 |
|
|
.elecidleinfersel({3{1'b0}}),
|
1065 |
|
|
.forceelecidle(1'b0),
|
1066 |
|
|
.freezptr(1'b0),
|
1067 |
|
|
.hipdatain({10{1'b0}}),
|
1068 |
|
|
.hipdetectrxloop(1'b0),
|
1069 |
|
|
.hipelecidleinfersel({3{1'b0}}),
|
1070 |
|
|
.hipforceelecidle(1'b0),
|
1071 |
|
|
.hippowerdn({2{1'b0}}),
|
1072 |
|
|
.hiptxdeemph(1'b0),
|
1073 |
|
|
.hiptxmargin({3{1'b0}}),
|
1074 |
|
|
.iqpphfifoxnbytesel({2{1'b0}}),
|
1075 |
|
|
.iqpphfifoxnrdclk({2{1'b0}}),
|
1076 |
|
|
.iqpphfifoxnrdenable({2{1'b0}}),
|
1077 |
|
|
.iqpphfifoxnwrenable({2{1'b0}}),
|
1078 |
|
|
.phfifobyteserdisable(1'b0),
|
1079 |
|
|
.phfifoptrsreset(1'b0),
|
1080 |
|
|
.phfifox4bytesel(1'b0),
|
1081 |
|
|
.phfifox4rdclk(1'b0),
|
1082 |
|
|
.phfifox4rdenable(1'b0),
|
1083 |
|
|
.phfifox4wrenable(1'b0),
|
1084 |
|
|
.phfifoxnbottombytesel(1'b0),
|
1085 |
|
|
.phfifoxnbottomrdclk(1'b0),
|
1086 |
|
|
.phfifoxnbottomrdenable(1'b0),
|
1087 |
|
|
.phfifoxnbottomwrenable(1'b0),
|
1088 |
|
|
.phfifoxnbytesel({3{1'b0}}),
|
1089 |
|
|
.phfifoxnptrsreset({3{1'b0}}),
|
1090 |
|
|
.phfifoxnrdclk({3{1'b0}}),
|
1091 |
|
|
.phfifoxnrdenable({3{1'b0}}),
|
1092 |
|
|
.phfifoxntopbytesel(1'b0),
|
1093 |
|
|
.phfifoxntoprdclk(1'b0),
|
1094 |
|
|
.phfifoxntoprdenable(1'b0),
|
1095 |
|
|
.phfifoxntopwrenable(1'b0),
|
1096 |
|
|
.phfifoxnwrenable({3{1'b0}}),
|
1097 |
|
|
.pipetxdeemph(1'b0),
|
1098 |
|
|
.pipetxmargin({3{1'b0}}),
|
1099 |
|
|
.pipetxswing(1'b0),
|
1100 |
|
|
.prbscidenable(1'b0),
|
1101 |
|
|
.rateswitch(1'b0),
|
1102 |
|
|
.rateswitchisdone(1'b0),
|
1103 |
|
|
.rateswitchxndone(1'b0),
|
1104 |
|
|
.refclk(1'b0)
|
1105 |
|
|
`ifndef FORMAL_VERIFICATION
|
1106 |
|
|
// synopsys translate_on
|
1107 |
|
|
`endif
|
1108 |
|
|
);
|
1109 |
|
|
defparam
|
1110 |
|
|
transmit_pcs0.allow_polarity_inversion = "false",
|
1111 |
|
|
transmit_pcs0.auto_spd_self_switch_enable = "false",
|
1112 |
|
|
transmit_pcs0.bitslip_enable = "false",
|
1113 |
|
|
transmit_pcs0.channel_bonding = "none",
|
1114 |
|
|
transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
|
1115 |
|
|
transmit_pcs0.channel_width = 8,
|
1116 |
|
|
transmit_pcs0.core_clock_0ppm = "false",
|
1117 |
|
|
transmit_pcs0.datapath_low_latency_mode = "false",
|
1118 |
|
|
transmit_pcs0.datapath_protocol = "basic",
|
1119 |
|
|
transmit_pcs0.disable_ph_low_latency_mode = "false",
|
1120 |
|
|
transmit_pcs0.disparity_mode = "none",
|
1121 |
|
|
transmit_pcs0.dprio_config_mode = 6'h01,
|
1122 |
|
|
transmit_pcs0.elec_idle_delay = 6,
|
1123 |
|
|
transmit_pcs0.enable_bit_reversal = "false",
|
1124 |
|
|
transmit_pcs0.enable_idle_selection = "true",
|
1125 |
|
|
transmit_pcs0.enable_reverse_parallel_loopback = "false",
|
1126 |
|
|
transmit_pcs0.enable_self_test_mode = "false",
|
1127 |
|
|
transmit_pcs0.enable_symbol_swap = "false",
|
1128 |
|
|
transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
|
1129 |
|
|
transmit_pcs0.enc_8b_10b_mode = "normal",
|
1130 |
|
|
transmit_pcs0.force_echar = "false",
|
1131 |
|
|
transmit_pcs0.force_kchar = "false",
|
1132 |
|
|
transmit_pcs0.hip_enable = "false",
|
1133 |
|
|
transmit_pcs0.logical_channel_address = (starting_channel_number + 0),
|
1134 |
|
|
transmit_pcs0.ph_fifo_reg_mode = "false",
|
1135 |
|
|
transmit_pcs0.ph_fifo_xn_mapping0 = "none",
|
1136 |
|
|
transmit_pcs0.ph_fifo_xn_mapping1 = "none",
|
1137 |
|
|
transmit_pcs0.ph_fifo_xn_mapping2 = "none",
|
1138 |
|
|
transmit_pcs0.ph_fifo_xn_select = 1,
|
1139 |
|
|
transmit_pcs0.pipe_auto_speed_nego_enable = "false",
|
1140 |
|
|
transmit_pcs0.pipe_freq_scale_mode = "Frequency",
|
1141 |
|
|
transmit_pcs0.prbs_cid_pattern = "false",
|
1142 |
|
|
transmit_pcs0.protocol_hint = "gige",
|
1143 |
|
|
transmit_pcs0.refclk_select = "local",
|
1144 |
|
|
transmit_pcs0.self_test_mode = "incremental",
|
1145 |
|
|
transmit_pcs0.use_double_data_mode = "false",
|
1146 |
|
|
transmit_pcs0.use_serializer_double_data_mode = "false",
|
1147 |
|
|
transmit_pcs0.wr_clk_mux_select = "core_clk",
|
1148 |
|
|
transmit_pcs0.lpm_type = "stratixiv_hssi_tx_pcs";
|
1149 |
|
|
stratixiv_hssi_tx_pma transmit_pma0
|
1150 |
|
|
(
|
1151 |
|
|
.clockout(wire_transmit_pma0_clockout),
|
1152 |
|
|
.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[19:0]}),
|
1153 |
|
|
.dataout(wire_transmit_pma0_dataout),
|
1154 |
|
|
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
|
1155 |
|
|
.dftout(),
|
1156 |
|
|
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
|
1157 |
|
|
.dprioin(tx_pmadprioin_wire[299:0]),
|
1158 |
|
|
.dprioout(wire_transmit_pma0_dprioout),
|
1159 |
|
|
.fastrefclk0in(analogfastrefclkout[1:0]),
|
1160 |
|
|
.fastrefclk1in({2{1'b0}}),
|
1161 |
|
|
.fastrefclk2in({2{1'b0}}),
|
1162 |
|
|
.fastrefclk4in({2{1'b0}}),
|
1163 |
|
|
.forceelecidle(1'b0),
|
1164 |
|
|
.powerdn(cent_unit_txobpowerdn[0]),
|
1165 |
|
|
.refclk0in({analogrefclkout[1:0]}),
|
1166 |
|
|
.refclk0inpulse(analogrefclkpulse[0]),
|
1167 |
|
|
.refclk1in({2{1'b0}}),
|
1168 |
|
|
.refclk1inpulse(1'b0),
|
1169 |
|
|
.refclk2in({2{1'b0}}),
|
1170 |
|
|
.refclk2inpulse(1'b0),
|
1171 |
|
|
.refclk4in({2{1'b0}}),
|
1172 |
|
|
.refclk4inpulse(1'b0),
|
1173 |
|
|
.revserialfdbk(1'b0),
|
1174 |
|
|
.rxdetecten(txdetectrxout[0]),
|
1175 |
|
|
.rxdetectvalidout(),
|
1176 |
|
|
.rxfoundout(),
|
1177 |
|
|
.seriallpbkout(wire_transmit_pma0_seriallpbkout),
|
1178 |
|
|
.txpmareset(tx_analogreset_out[0])
|
1179 |
|
|
`ifndef FORMAL_VERIFICATION
|
1180 |
|
|
// synopsys translate_off
|
1181 |
|
|
`endif
|
1182 |
|
|
,
|
1183 |
|
|
.datainfull({20{1'b0}}),
|
1184 |
|
|
.extra10gin({11{1'b0}}),
|
1185 |
|
|
.fastrefclk3in({2{1'b0}}),
|
1186 |
|
|
.pclk({5{1'b0}}),
|
1187 |
|
|
.refclk3in({2{1'b0}}),
|
1188 |
|
|
.refclk3inpulse(1'b0),
|
1189 |
|
|
.rxdetectclk(1'b0)
|
1190 |
|
|
`ifndef FORMAL_VERIFICATION
|
1191 |
|
|
// synopsys translate_on
|
1192 |
|
|
`endif
|
1193 |
|
|
);
|
1194 |
|
|
defparam
|
1195 |
|
|
transmit_pma0.analog_power = "auto",
|
1196 |
|
|
transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
|
1197 |
|
|
transmit_pma0.channel_type = "auto",
|
1198 |
|
|
transmit_pma0.clkin_select = 0,
|
1199 |
|
|
transmit_pma0.clkmux_delay = "false",
|
1200 |
|
|
transmit_pma0.common_mode = "0.65V",
|
1201 |
|
|
transmit_pma0.dprio_config_mode = 6'h01,
|
1202 |
|
|
transmit_pma0.enable_reverse_serial_loopback = "false",
|
1203 |
|
|
transmit_pma0.logical_channel_address = (starting_channel_number + 0),
|
1204 |
|
|
transmit_pma0.logical_protocol_hint_0 = "gige",
|
1205 |
|
|
transmit_pma0.low_speed_test_select = 0,
|
1206 |
|
|
transmit_pma0.physical_clkin0_mapping = "x1",
|
1207 |
|
|
transmit_pma0.preemp_pretap = 0,
|
1208 |
|
|
transmit_pma0.preemp_pretap_inv = "false",
|
1209 |
|
|
transmit_pma0.preemp_tap_1 = 0,
|
1210 |
|
|
transmit_pma0.preemp_tap_2 = 0,
|
1211 |
|
|
transmit_pma0.preemp_tap_2_inv = "false",
|
1212 |
|
|
transmit_pma0.protocol_hint = "gige",
|
1213 |
|
|
transmit_pma0.rx_detect = 0,
|
1214 |
|
|
transmit_pma0.serialization_factor = 10,
|
1215 |
|
|
transmit_pma0.slew_rate = "medium",
|
1216 |
|
|
transmit_pma0.termination = "OCT 100 Ohms",
|
1217 |
|
|
transmit_pma0.use_external_termination = "false",
|
1218 |
|
|
transmit_pma0.use_pma_direct = "false",
|
1219 |
|
|
transmit_pma0.use_ser_double_data_mode = "false",
|
1220 |
|
|
transmit_pma0.vod_selection = 1,
|
1221 |
|
|
transmit_pma0.lpm_type = "stratixiv_hssi_tx_pma";
|
1222 |
|
|
assign
|
1223 |
|
|
analogfastrefclkout = {wire_ch_clk_div0_analogfastrefclkout},
|
1224 |
|
|
analogrefclkout = {wire_ch_clk_div0_analogrefclkout},
|
1225 |
|
|
analogrefclkpulse = {wire_ch_clk_div0_analogrefclkpulse},
|
1226 |
|
|
cal_blk_powerdown = 1'b0,
|
1227 |
|
|
cent_unit_cmudividerdprioout = {wire_cent_unit0_cmudividerdprioout},
|
1228 |
|
|
cent_unit_cmuplldprioout = {wire_cent_unit0_cmuplldprioout},
|
1229 |
|
|
cent_unit_pllpowerdn = {wire_cent_unit0_pllpowerdn[1:0]},
|
1230 |
|
|
cent_unit_pllresetout = {wire_cent_unit0_pllresetout[1:0]},
|
1231 |
|
|
cent_unit_quadresetout = {wire_cent_unit0_quadresetout},
|
1232 |
|
|
cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[5:0]},
|
1233 |
|
|
cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[5:0]},
|
1234 |
|
|
cent_unit_rxpcsdprioin = {{1200{1'b0}}, rx_pcsdprioout[399:0]},
|
1235 |
|
|
cent_unit_rxpcsdprioout = {wire_cent_unit0_rxpcsdprioout[1599:0]},
|
1236 |
|
|
cent_unit_rxpmadprioin = {{1500{1'b0}}, rx_pmadprioout[299:0]},
|
1237 |
|
|
cent_unit_rxpmadprioout = {wire_cent_unit0_rxpmadprioout[1799:0]},
|
1238 |
|
|
cent_unit_tx_dprioin = {{1050{1'b0}}, tx_txdprioout[149:0]},
|
1239 |
|
|
cent_unit_tx_xgmdataout = {wire_cent_unit0_txdataout[31:0]},
|
1240 |
|
|
cent_unit_txctrlout = {wire_cent_unit0_txctrlout},
|
1241 |
|
|
cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[5:0]},
|
1242 |
|
|
cent_unit_txdprioout = {wire_cent_unit0_txpcsdprioout[599:0]},
|
1243 |
|
|
cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[5:0]},
|
1244 |
|
|
cent_unit_txpmadprioin = {{1500{1'b0}}, tx_pmadprioout[299:0]},
|
1245 |
|
|
cent_unit_txpmadprioout = {wire_cent_unit0_txpmadprioout[1799:0]},
|
1246 |
|
|
clk_div_cmudividerdprioin = {{500{1'b0}}, wire_ch_clk_div0_dprioout},
|
1247 |
|
|
fixedclk_div_in = {fixedclk_div5quad0c, fixedclk_div4quad0c, fixedclk_div3quad0c, fixedclk_div2quad0c, fixedclk_div1quad0c, fixedclk_div0quad0c},
|
1248 |
|
|
fixedclk_enable = reconfig_togxb_busy_reg[0],
|
1249 |
|
|
fixedclk_in = {{5{1'b0}}, fixedclk},
|
1250 |
|
|
fixedclk_sel = reconfig_togxb_busy_reg[1],
|
1251 |
|
|
fixedclk_to_cmu = {((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[5]) & fixedclk_div_in[5]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[5])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[4]) & fixedclk_div_in[4]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[4])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[3]) & fixedclk_div_in[3]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[3])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[2]) & fixedclk_div_in[2]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[2])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[1]) & fixedclk_div_in[1]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[1])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[0]) & fixedclk_div_in[0]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[0]))},
|
1252 |
|
|
nonusertocmu_out = {wire_cal_blk0_nonusertocmu},
|
1253 |
|
|
pll0_clkin = {{9{1'b0}}, pll_inclk_wire[0]},
|
1254 |
|
|
pll0_dprioin = {cent_unit_cmuplldprioout[1499:1200]},
|
1255 |
|
|
pll0_dprioout = {wire_tx_pll0_dprioout},
|
1256 |
|
|
pll0_out = {wire_tx_pll0_clk[3:0]},
|
1257 |
|
|
pll_ch_dataout_wire = {wire_rx_cdr_pll0_dataout},
|
1258 |
|
|
pll_ch_dprioout = {wire_rx_cdr_pll0_dprioout},
|
1259 |
|
|
pll_cmuplldprioout = {{300{1'b0}}, pll0_dprioout[299:0], {900{1'b0}}, pll_ch_dprioout[299:0]},
|
1260 |
|
|
pll_inclk_wire = {pll_inclk},
|
1261 |
|
|
pll_locked = {pll_locked_out[0]},
|
1262 |
|
|
pll_locked_out = {wire_tx_pll0_locked},
|
1263 |
|
|
pllpowerdn_in = {1'b0, cent_unit_pllpowerdn[0]},
|
1264 |
|
|
pllreset_in = {1'b0, cent_unit_pllresetout[0]},
|
1265 |
|
|
reconfig_fromgxb = {rx_pma_analogtestbus[16:1], wire_cent_unit0_dprioout},
|
1266 |
|
|
reconfig_togxb_busy = reconfig_togxb[3],
|
1267 |
|
|
reconfig_togxb_disable = reconfig_togxb[1],
|
1268 |
|
|
reconfig_togxb_in = reconfig_togxb[0],
|
1269 |
|
|
reconfig_togxb_load = reconfig_togxb[2],
|
1270 |
|
|
rx_analogreset_in = {{5{1'b0}}, ((~ reconfig_togxb_busy) & rx_analogreset[0])},
|
1271 |
|
|
rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[5:0]},
|
1272 |
|
|
rx_clkout = {rx_clkout_wire[0]},
|
1273 |
|
|
rx_clkout_wire = {wire_receive_pcs0_clkout},
|
1274 |
|
|
rx_coreclk_in = {tx_core_clkout_wire[0]},
|
1275 |
|
|
rx_cruclk_in = {{9{1'b0}}, rx_pldcruclk_in[0]},
|
1276 |
|
|
rx_ctrldetect = {wire_receive_pcs0_ctrldetect[0]},
|
1277 |
|
|
rx_dataout = {rx_out_wire[7:0]},
|
1278 |
|
|
rx_deserclock_in = {rx_pll_clkout[3:0]},
|
1279 |
|
|
rx_digitalreset_in = {{3{1'b0}}, rx_digitalreset[0]},
|
1280 |
|
|
rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout[3:0]},
|
1281 |
|
|
rx_disperr = {wire_receive_pcs0_disperr[0]},
|
1282 |
|
|
rx_enapatternalign = 1'b0,
|
1283 |
|
|
rx_errdetect = {wire_receive_pcs0_errdetect[0]},
|
1284 |
|
|
rx_freqlocked = {(rx_freqlocked_wire[0] & (~ rx_analogreset[0]))},
|
1285 |
|
|
rx_freqlocked_wire = {wire_rx_cdr_pll0_freqlocked},
|
1286 |
|
|
rx_locktodata = 1'b0,
|
1287 |
|
|
rx_locktodata_wire = {((~ reconfig_togxb_busy) & rx_locktodata[0])},
|
1288 |
|
|
rx_locktorefclk = 1'b0,
|
1289 |
|
|
rx_locktorefclk_wire = {wire_receive_pcs0_cdrctrllocktorefclkout},
|
1290 |
|
|
rx_out_wire = {wire_receive_pcs0_dataout[7:0]},
|
1291 |
|
|
rx_patterndetect = {wire_receive_pcs0_patterndetect[0]},
|
1292 |
|
|
rx_pcsdprioin_wire = {{1200{1'b0}}, cent_unit_rxpcsdprioout[399:0]},
|
1293 |
|
|
rx_pcsdprioout = {{1200{1'b0}}, wire_receive_pcs0_dprioout},
|
1294 |
|
|
rx_phfifordenable = 1'b1,
|
1295 |
|
|
rx_phfiforeset = 1'b0,
|
1296 |
|
|
rx_phfifowrdisable = 1'b0,
|
1297 |
|
|
rx_pldcruclk_in = {rx_cruclk[0]},
|
1298 |
|
|
rx_pll_clkout = {wire_rx_cdr_pll0_clk},
|
1299 |
|
|
rx_pll_pfdrefclkout_wire = {wire_rx_cdr_pll0_pfdrefclkout},
|
1300 |
|
|
rx_plllocked_wire = {wire_rx_cdr_pll0_locked},
|
1301 |
|
|
rx_pma_analogtestbus = {{12{1'b0}}, wire_receive_pma0_analogtestbus[5:2], 1'b0},
|
1302 |
|
|
rx_pma_clockout = {wire_receive_pma0_clockout},
|
1303 |
|
|
rx_pma_dataout = {wire_receive_pma0_dataout},
|
1304 |
|
|
rx_pma_locktorefout = {wire_receive_pma0_locktorefout},
|
1305 |
|
|
rx_pma_recoverdataout_wire = {wire_receive_pma0_recoverdataout[19:0]},
|
1306 |
|
|
rx_pmadprioin_wire = {{1500{1'b0}}, cent_unit_rxpmadprioout[299:0]},
|
1307 |
|
|
rx_pmadprioout = {{1500{1'b0}}, wire_receive_pma0_dprioout},
|
1308 |
|
|
rx_powerdown = 1'b0,
|
1309 |
|
|
rx_powerdown_in = {{5{1'b0}}, rx_powerdown[0]},
|
1310 |
|
|
rx_prbscidenable = 1'b0,
|
1311 |
|
|
rx_recovclkout = {rx_pma_clockout[0]},
|
1312 |
|
|
rx_rlv = {wire_receive_pcs0_rlv},
|
1313 |
|
|
rx_rmfifodatadeleted = {wire_receive_pcs0_rmfifodatadeleted[0]},
|
1314 |
|
|
rx_rmfifodatainserted = {wire_receive_pcs0_rmfifodatainserted[0]},
|
1315 |
|
|
rx_rmfiforeset = 1'b0,
|
1316 |
|
|
rx_runningdisp = {wire_receive_pcs0_runningdisp[0]},
|
1317 |
|
|
rx_rxcruresetout = {wire_cent_unit0_rxcruresetout[5:0]},
|
1318 |
|
|
rx_syncstatus = {wire_receive_pcs0_syncstatus[0]},
|
1319 |
|
|
rxpll_dprioin = {{1500{1'b0}}, cent_unit_cmuplldprioout[299:0]},
|
1320 |
|
|
tx_analogreset_out = {wire_cent_unit0_txanalogresetout[5:0]},
|
1321 |
|
|
tx_clkout = {tx_core_clkout_wire[0]},
|
1322 |
|
|
tx_clkout_int_wire = {wire_transmit_pcs0_clkout},
|
1323 |
|
|
tx_core_clkout_wire = {tx_clkout_int_wire[0]},
|
1324 |
|
|
tx_coreclk_in = {tx_core_clkout_wire[0]},
|
1325 |
|
|
tx_datain_wire = {tx_datain[7:0]},
|
1326 |
|
|
tx_dataout = {wire_transmit_pma0_dataout},
|
1327 |
|
|
tx_dataout_pcs_to_pma = {wire_transmit_pcs0_dataout},
|
1328 |
|
|
tx_digitalreset_in = {{3{1'b0}}, tx_digitalreset[0]},
|
1329 |
|
|
tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout[3:0]},
|
1330 |
|
|
tx_dprioin_wire = {{1050{1'b0}}, cent_unit_txdprioout[149:0]},
|
1331 |
|
|
tx_forcedisp_wire = {1'b0},
|
1332 |
|
|
tx_invpolarity = 1'b0,
|
1333 |
|
|
tx_localrefclk = {wire_transmit_pma0_clockout},
|
1334 |
|
|
tx_phfiforeset = 1'b0,
|
1335 |
|
|
tx_pmadprioin_wire = {{1500{1'b0}}, cent_unit_txpmadprioout[299:0]},
|
1336 |
|
|
tx_pmadprioout = {{1500{1'b0}}, wire_transmit_pma0_dprioout},
|
1337 |
|
|
tx_serialloopbackout = {wire_transmit_pma0_seriallpbkout},
|
1338 |
|
|
tx_txdprioout = {{450{1'b0}}, wire_transmit_pcs0_dprioout},
|
1339 |
|
|
txdetectrxout = {wire_transmit_pcs0_txdetectrx},
|
1340 |
|
|
w_cent_unit_dpriodisableout1w = {wire_cent_unit0_dpriodisableout};
|
1341 |
|
|
endmodule //altera_tse_alt4gxb_gige_alt4gxb_gtca
|
1342 |
|
|
//VALID FILE
|
1343 |
|
|
|
1344 |
|
|
|
1345 |
|
|
// synopsys translate_off
|
1346 |
|
|
`timescale 1 ps / 1 ps
|
1347 |
|
|
// synopsys translate_on
|
1348 |
|
|
module altera_tse_alt4gxb_gige (
|
1349 |
|
|
cal_blk_clk,
|
1350 |
|
|
fixedclk,
|
1351 |
|
|
fixedclk_fast,
|
1352 |
|
|
gxb_powerdown,
|
1353 |
|
|
pll_inclk,
|
1354 |
|
|
pll_powerdown,
|
1355 |
|
|
reconfig_clk,
|
1356 |
|
|
reconfig_togxb,
|
1357 |
|
|
rx_analogreset,
|
1358 |
|
|
rx_cruclk,
|
1359 |
|
|
rx_datain,
|
1360 |
|
|
rx_digitalreset,
|
1361 |
|
|
rx_seriallpbken,
|
1362 |
|
|
tx_ctrlenable,
|
1363 |
|
|
tx_datain,
|
1364 |
|
|
tx_digitalreset,
|
1365 |
|
|
pll_locked,
|
1366 |
|
|
reconfig_fromgxb,
|
1367 |
|
|
rx_clkout,
|
1368 |
|
|
rx_ctrldetect,
|
1369 |
|
|
rx_dataout,
|
1370 |
|
|
rx_disperr,
|
1371 |
|
|
rx_errdetect,
|
1372 |
|
|
rx_freqlocked,
|
1373 |
|
|
rx_patterndetect,
|
1374 |
|
|
rx_recovclkout,
|
1375 |
|
|
rx_rlv,
|
1376 |
|
|
rx_rmfifodatadeleted,
|
1377 |
|
|
rx_rmfifodatainserted,
|
1378 |
|
|
rx_runningdisp,
|
1379 |
|
|
rx_syncstatus,
|
1380 |
|
|
tx_clkout,
|
1381 |
|
|
tx_dataout)/* synthesis synthesis_clearbox = 2 */;
|
1382 |
|
|
|
1383 |
|
|
input cal_blk_clk;
|
1384 |
|
|
input fixedclk;
|
1385 |
|
|
input [5:0] fixedclk_fast;
|
1386 |
|
|
input [0:0] gxb_powerdown;
|
1387 |
|
|
input pll_inclk;
|
1388 |
|
|
input [0:0] pll_powerdown;
|
1389 |
|
|
input reconfig_clk;
|
1390 |
|
|
input [3:0] reconfig_togxb;
|
1391 |
|
|
input [0:0] rx_analogreset;
|
1392 |
|
|
input [0:0] rx_cruclk;
|
1393 |
|
|
input [0:0] rx_datain;
|
1394 |
|
|
input [0:0] rx_digitalreset;
|
1395 |
|
|
input [0:0] rx_seriallpbken;
|
1396 |
|
|
input [0:0] tx_ctrlenable;
|
1397 |
|
|
input [7:0] tx_datain;
|
1398 |
|
|
input [0:0] tx_digitalreset;
|
1399 |
|
|
output [0:0] pll_locked;
|
1400 |
|
|
output [16:0] reconfig_fromgxb;
|
1401 |
|
|
output rx_clkout;
|
1402 |
|
|
output [0:0] rx_ctrldetect;
|
1403 |
|
|
output [7:0] rx_dataout;
|
1404 |
|
|
output [0:0] rx_disperr;
|
1405 |
|
|
output [0:0] rx_errdetect;
|
1406 |
|
|
output [0:0] rx_freqlocked;
|
1407 |
|
|
output [0:0] rx_patterndetect;
|
1408 |
|
|
output [0:0] rx_recovclkout;
|
1409 |
|
|
output [0:0] rx_rlv;
|
1410 |
|
|
output [0:0] rx_rmfifodatadeleted;
|
1411 |
|
|
output [0:0] rx_rmfifodatainserted;
|
1412 |
|
|
output [0:0] rx_runningdisp;
|
1413 |
|
|
output [0:0] rx_syncstatus;
|
1414 |
|
|
output [0:0] tx_clkout;
|
1415 |
|
|
output [0:0] tx_dataout;
|
1416 |
|
|
`ifndef ALTERA_RESERVED_QIS
|
1417 |
|
|
// synopsys translate_off
|
1418 |
|
|
`endif
|
1419 |
|
|
tri0 [0:0] rx_cruclk;
|
1420 |
|
|
`ifndef ALTERA_RESERVED_QIS
|
1421 |
|
|
// synopsys translate_on
|
1422 |
|
|
`endif
|
1423 |
|
|
|
1424 |
|
|
parameter starting_channel_number = 0;
|
1425 |
|
|
|
1426 |
|
|
|
1427 |
|
|
wire [0:0] sub_wire0;
|
1428 |
|
|
wire [0:0] sub_wire1;
|
1429 |
|
|
wire [16:0] sub_wire2;
|
1430 |
|
|
wire [0:0] sub_wire3;
|
1431 |
|
|
wire [0:0] sub_wire4;
|
1432 |
|
|
wire [0:0] sub_wire5;
|
1433 |
|
|
wire [0:0] sub_wire6;
|
1434 |
|
|
wire [0:0] sub_wire7;
|
1435 |
|
|
wire sub_wire8;
|
1436 |
|
|
wire [7:0] sub_wire9;
|
1437 |
|
|
wire [0:0] sub_wire10;
|
1438 |
|
|
wire [0:0] sub_wire11;
|
1439 |
|
|
wire [0:0] sub_wire12;
|
1440 |
|
|
wire [0:0] sub_wire13;
|
1441 |
|
|
wire [0:0] sub_wire14;
|
1442 |
|
|
wire [0:0] sub_wire15;
|
1443 |
|
|
wire [0:0] sub_wire16;
|
1444 |
|
|
wire [0:0] rx_patterndetect = sub_wire0[0:0];
|
1445 |
|
|
wire [0:0] pll_locked = sub_wire1[0:0];
|
1446 |
|
|
wire [16:0] reconfig_fromgxb = sub_wire2[16:0];
|
1447 |
|
|
wire [0:0] rx_freqlocked = sub_wire3[0:0];
|
1448 |
|
|
wire [0:0] rx_disperr = sub_wire4[0:0];
|
1449 |
|
|
wire [0:0] rx_recovclkout = sub_wire5[0:0];
|
1450 |
|
|
wire [0:0] rx_runningdisp = sub_wire6[0:0];
|
1451 |
|
|
wire [0:0] rx_syncstatus = sub_wire7[0:0];
|
1452 |
|
|
wire rx_clkout = sub_wire8;
|
1453 |
|
|
wire [7:0] rx_dataout = sub_wire9[7:0];
|
1454 |
|
|
wire [0:0] rx_errdetect = sub_wire10[0:0];
|
1455 |
|
|
wire [0:0] rx_rmfifodatainserted = sub_wire11[0:0];
|
1456 |
|
|
wire [0:0] rx_rlv = sub_wire12[0:0];
|
1457 |
|
|
wire [0:0] rx_rmfifodatadeleted = sub_wire13[0:0];
|
1458 |
|
|
wire [0:0] tx_clkout = sub_wire14[0:0];
|
1459 |
|
|
wire [0:0] tx_dataout = sub_wire15[0:0];
|
1460 |
|
|
wire [0:0] rx_ctrldetect = sub_wire16[0:0];
|
1461 |
|
|
|
1462 |
|
|
altera_tse_alt4gxb_gige_alt4gxb_gtca altera_tse_alt4gxb_gige_alt4gxb_gtca_component (
|
1463 |
|
|
.reconfig_togxb (reconfig_togxb),
|
1464 |
|
|
.cal_blk_clk (cal_blk_clk),
|
1465 |
|
|
.fixedclk (fixedclk),
|
1466 |
|
|
.rx_datain (rx_datain),
|
1467 |
|
|
.rx_digitalreset (rx_digitalreset),
|
1468 |
|
|
.pll_powerdown (pll_powerdown),
|
1469 |
|
|
.tx_datain (tx_datain),
|
1470 |
|
|
.tx_digitalreset (tx_digitalreset),
|
1471 |
|
|
.gxb_powerdown (gxb_powerdown),
|
1472 |
|
|
.rx_cruclk (rx_cruclk),
|
1473 |
|
|
.rx_seriallpbken (rx_seriallpbken),
|
1474 |
|
|
.reconfig_clk (reconfig_clk),
|
1475 |
|
|
.rx_analogreset (rx_analogreset),
|
1476 |
|
|
.fixedclk_fast (fixedclk_fast),
|
1477 |
|
|
.tx_ctrlenable (tx_ctrlenable),
|
1478 |
|
|
.pll_inclk (pll_inclk),
|
1479 |
|
|
.rx_patterndetect (sub_wire0),
|
1480 |
|
|
.pll_locked (sub_wire1),
|
1481 |
|
|
.reconfig_fromgxb (sub_wire2),
|
1482 |
|
|
.rx_freqlocked (sub_wire3),
|
1483 |
|
|
.rx_disperr (sub_wire4),
|
1484 |
|
|
.rx_recovclkout (sub_wire5),
|
1485 |
|
|
.rx_runningdisp (sub_wire6),
|
1486 |
|
|
.rx_syncstatus (sub_wire7),
|
1487 |
|
|
.rx_clkout (sub_wire8),
|
1488 |
|
|
.rx_dataout (sub_wire9),
|
1489 |
|
|
.rx_errdetect (sub_wire10),
|
1490 |
|
|
.rx_rmfifodatainserted (sub_wire11),
|
1491 |
|
|
.rx_rlv (sub_wire12),
|
1492 |
|
|
.rx_rmfifodatadeleted (sub_wire13),
|
1493 |
|
|
.tx_clkout (sub_wire14),
|
1494 |
|
|
.tx_dataout (sub_wire15),
|
1495 |
|
|
.rx_ctrldetect (sub_wire16))/* synthesis synthesis_clearbox=2
|
1496 |
|
|
clearbox_macroname = alt4gxb
|
1497 |
|
|
clearbox_defparam = "effective_data_rate=1250.0 Mbps;enable_lc_tx_pll=false;equalizer_ctrl_a_setting=0;equalizer_ctrl_b_setting=0;equalizer_ctrl_c_setting=0;equalizer_ctrl_d_setting=0;equalizer_ctrl_v_setting=0;equalizer_dcgain_setting=0;gen_reconfig_pll=false;gxb_analog_power=AUTO;gx_channel_type=AUTO;input_clock_frequency=125.0 MHz;intended_device_family=Stratix IV;intended_device_speed_grade=2;intended_device_variant=GX;loopback_mode=slb;lpm_type=alt4gxb;number_of_channels=1;operation_mode=duplex;pll_control_width=1;pll_pfd_fb_mode=internal;preemphasis_ctrl_1stposttap_setting=0;preemphasis_ctrl_2ndposttap_inv_setting=false;preemphasis_ctrl_2ndposttap_setting=0;preemphasis_ctrl_pretap_inv_setting=false;preemphasis_ctrl_pretap_setting=0;protocol=gige;receiver_termination=oct_100_ohms;reconfig_dprio_mode=1;rx_8b_10b_mode=normal;rx_align_pattern=0101111100;rx_align_pattern_length=10;rx_allow_align_polarity_inversion=false;rx_allow_pipe_polarity_inversion=false;rx_bitslip_enable=false;rx_byte_ordering_mode=NONE;rx_channel_width=8;rx_common_mode=0.82v;rx_cru_bandwidth_type=Medium;rx_cru_inclock0_period=8000;rx_datapath_protocol=basic;rx_data_rate=1250;rx_data_rate_remainder=0;rx_digitalreset_port_width=1;rx_enable_bit_reversal=false;rx_enable_lock_to_data_sig=false;rx_enable_lock_to_refclk_sig=false;rx_enable_self_test_mode=false;rx_force_signal_detect=true;rx_ppmselect=32;rx_rate_match_fifo_mode=normal;rx_rate_match_fifo_mode_manual_control=normal;rx_rate_match_pattern1=10100010010101111100;
|
1498 |
|
|
rx_rate_match_pattern2=10101011011010000011;rx_rate_match_pattern_size=20;rx_run_length=5;rx_run_length_enable=true;rx_signal_detect_threshold=2;rx_use_align_state_machine=true;rx_use_clkout=true;rx_use_coreclk=false;rx_use_cruclk=true;rx_use_deserializer_double_data_mode=false;rx_use_deskew_fifo=false;rx_use_double_data_mode=false;rx_use_rate_match_pattern1_only=false;transmitter_termination=oct_100_ohms;tx_8b_10b_mode=normal;tx_allow_polarity_inversion=false;tx_analog_power=AUTO;tx_channel_width=8;tx_clkout_width=1;tx_common_mode=0.65v;tx_data_rate=1250;tx_data_rate_remainder=0;tx_digitalreset_port_width=1;tx_enable_bit_reversal=false;tx_enable_self_test_mode=false;tx_pll_bandwidth_type=High;tx_pll_inclk0_period=8000;tx_pll_type=CMU;tx_slew_rate=medium;tx_transmit_protocol=basic;tx_use_coreclk=false;tx_use_double_data_mode=false;tx_use_serializer_double_data_mode=false;use_calibration_block=true;vod_ctrl_setting=1;gxb_powerdown_width=1;number_of_quads=1;reconfig_calibration=true;reconfig_fromgxb_port_width=17;reconfig_togxb_port_width=4;rx_cru_m_divider=5;rx_cru_n_divider=1;rx_cru_vco_post_scale_divider=4;rx_dwidth_factor=1;rx_signal_detect_loss_threshold=1;rx_signal_detect_valid_threshold=1;rx_use_external_termination=false;rx_word_aligner_num_byte=1;tx_dwidth_factor=1;tx_pll_clock_post_divider=1;tx_pll_m_divider=5;tx_pll_n_divider=1;tx_pll_vco_post_scale_divider=4;tx_use_external_termination=false;" */;
|
1499 |
|
|
defparam
|
1500 |
|
|
altera_tse_alt4gxb_gige_alt4gxb_gtca_component.starting_channel_number = starting_channel_number;
|
1501 |
|
|
|
1502 |
|
|
|
1503 |
|
|
endmodule
|
1504 |
|
|
|
1505 |
|
|
// ============================================================
|
1506 |
|
|
// CNX file retrieval info
|
1507 |
|
|
// ============================================================
|
1508 |
|
|
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
|
1509 |
|
|
// Retrieval info: PRIVATE: IP_MODE STRING "TSE"
|
1510 |
|
|
// Retrieval info: PRIVATE: LOCKDOWN_EXCL STRING "TSE"
|
1511 |
|
|
// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
|
1512 |
|
|
// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
|
1513 |
|
|
// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
|
1514 |
|
|
// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
|
1515 |
|
|
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
1516 |
|
|
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "1250.0"
|
1517 |
|
|
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
|
1518 |
|
|
// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "1250.0"
|
1519 |
|
|
// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100"
|
1520 |
|
|
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
|
1521 |
|
|
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
|
1522 |
|
|
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
|
1523 |
|
|
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
|
1524 |
|
|
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
|
1525 |
|
|
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "125"
|
1526 |
|
|
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "GIGE"
|
1527 |
|
|
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
|
1528 |
|
|
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
|
1529 |
|
|
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
|
1530 |
|
|
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
|
1531 |
|
|
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
|
1532 |
|
|
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
|
1533 |
|
|
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
|
1534 |
|
|
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
|
1535 |
|
|
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
|
1536 |
|
|
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
|
1537 |
|
|
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
|
1538 |
|
|
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
|
1539 |
|
|
// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
|
1540 |
|
|
// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
|
1541 |
|
|
// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
|
1542 |
|
|
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "125.0"
|
1543 |
|
|
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "62.5 125.0"
|
1544 |
|
|
// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "1250.0"
|
1545 |
|
|
// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
|
1546 |
|
|
// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "125.0"
|
1547 |
|
|
// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
|
1548 |
|
|
// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
|
1549 |
|
|
// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "GIGE"
|
1550 |
|
|
// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "None"
|
1551 |
|
|
// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
|
1552 |
|
|
// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
|
1553 |
|
|
// Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "1250.0 Mbps"
|
1554 |
|
|
// Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false"
|
1555 |
|
|
// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
|
1556 |
|
|
// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
|
1557 |
|
|
// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
|
1558 |
|
|
// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0"
|
1559 |
|
|
// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "0"
|
1560 |
|
|
// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "0"
|
1561 |
|
|
// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
|
1562 |
|
|
// Retrieval info: CONSTANT: GXB_ANALOG_POWER STRING "AUTO"
|
1563 |
|
|
// Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING "AUTO"
|
1564 |
|
|
// Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "125.0 MHz"
|
1565 |
|
|
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
|
1566 |
|
|
// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "2"
|
1567 |
|
|
// Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "GX"
|
1568 |
|
|
// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "slb"
|
1569 |
|
|
// Retrieval info: CONSTANT: LPM_TYPE STRING "alt4gxb"
|
1570 |
|
|
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
|
1571 |
|
|
// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
|
1572 |
|
|
// Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1"
|
1573 |
|
|
// Retrieval info: CONSTANT: PLL_PFD_FB_MODE STRING "internal"
|
1574 |
|
|
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "0"
|
1575 |
|
|
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_INV_SETTING STRING "false"
|
1576 |
|
|
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_SETTING NUMERIC "0"
|
1577 |
|
|
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_INV_SETTING STRING "false"
|
1578 |
|
|
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_SETTING NUMERIC "0"
|
1579 |
|
|
// Retrieval info: CONSTANT: PROTOCOL STRING "gige"
|
1580 |
|
|
// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
|
1581 |
|
|
// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "1"
|
1582 |
|
|
// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
|
1583 |
|
|
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
|
1584 |
|
|
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
|
1585 |
|
|
// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
|
1586 |
|
|
// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "false"
|
1587 |
|
|
// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
|
1588 |
|
|
// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
|
1589 |
|
|
// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "8"
|
1590 |
|
|
// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
|
1591 |
|
|
// Retrieval info: CONSTANT: RX_CRU_BANDWIDTH_TYPE STRING "Medium"
|
1592 |
|
|
// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "8000"
|
1593 |
|
|
// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "basic"
|
1594 |
|
|
// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "1250"
|
1595 |
|
|
// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
|
1596 |
|
|
// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
|
1597 |
|
|
// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
|
1598 |
|
|
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
|
1599 |
|
|
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
|
1600 |
|
|
// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
|
1601 |
|
|
// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
|
1602 |
|
|
// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32"
|
1603 |
|
|
// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
|
1604 |
|
|
// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE_MANUAL_CONTROL STRING "normal"
|
1605 |
|
|
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "10100010010101111100"
|
1606 |
|
|
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "10101011011010000011"
|
1607 |
|
|
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
|
1608 |
|
|
// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "5"
|
1609 |
|
|
// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
|
1610 |
|
|
// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "2"
|
1611 |
|
|
// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
|
1612 |
|
|
// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "true"
|
1613 |
|
|
// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
|
1614 |
|
|
// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
|
1615 |
|
|
// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
|
1616 |
|
|
// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
|
1617 |
|
|
// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "false"
|
1618 |
|
|
// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
|
1619 |
|
|
// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
|
1620 |
|
|
// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
|
1621 |
|
|
// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
|
1622 |
|
|
// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "AUTO"
|
1623 |
|
|
// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "8"
|
1624 |
|
|
// Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "1"
|
1625 |
|
|
// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
|
1626 |
|
|
// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "1250"
|
1627 |
|
|
// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
|
1628 |
|
|
// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
|
1629 |
|
|
// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
|
1630 |
|
|
// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
|
1631 |
|
|
// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "High"
|
1632 |
|
|
// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "8000"
|
1633 |
|
|
// Retrieval info: CONSTANT: TX_PLL_TYPE STRING "CMU"
|
1634 |
|
|
// Retrieval info: CONSTANT: TX_SLEW_RATE STRING "medium"
|
1635 |
|
|
// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "basic"
|
1636 |
|
|
// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
|
1637 |
|
|
// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "false"
|
1638 |
|
|
// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
|
1639 |
|
|
// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
|
1640 |
|
|
// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "1"
|
1641 |
|
|
// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
|
1642 |
|
|
// Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
|
1643 |
|
|
// Retrieval info: CONSTANT: reconfig_calibration STRING "true"
|
1644 |
|
|
// Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "17"
|
1645 |
|
|
// Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4"
|
1646 |
|
|
// Retrieval info: CONSTANT: rx_cru_m_divider NUMERIC "5"
|
1647 |
|
|
// Retrieval info: CONSTANT: rx_cru_n_divider NUMERIC "1"
|
1648 |
|
|
// Retrieval info: CONSTANT: rx_cru_vco_post_scale_divider NUMERIC "4"
|
1649 |
|
|
// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "1"
|
1650 |
|
|
// Retrieval info: CONSTANT: rx_signal_detect_loss_threshold STRING "1"
|
1651 |
|
|
// Retrieval info: CONSTANT: rx_signal_detect_valid_threshold STRING "1"
|
1652 |
|
|
// Retrieval info: CONSTANT: rx_use_external_termination STRING "false"
|
1653 |
|
|
// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
|
1654 |
|
|
// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "1"
|
1655 |
|
|
// Retrieval info: CONSTANT: tx_pll_clock_post_divider NUMERIC "1"
|
1656 |
|
|
// Retrieval info: CONSTANT: tx_pll_m_divider NUMERIC "5"
|
1657 |
|
|
// Retrieval info: CONSTANT: tx_pll_n_divider NUMERIC "1"
|
1658 |
|
|
// Retrieval info: CONSTANT: tx_pll_vco_post_scale_divider NUMERIC "4"
|
1659 |
|
|
// Retrieval info: CONSTANT: tx_use_external_termination STRING "false"
|
1660 |
|
|
// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
|
1661 |
|
|
// Retrieval info: USED_PORT: fixedclk 0 0 0 0 INPUT NODEFVAL "fixedclk"
|
1662 |
|
|
// Retrieval info: USED_PORT: fixedclk_fast 0 0 0 0 INPUT NODEFVAL "fixedclk_fast"
|
1663 |
|
|
// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
|
1664 |
|
|
// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
|
1665 |
|
|
// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
|
1666 |
|
|
// Retrieval info: USED_PORT: pll_powerdown 0 0 1 0 INPUT NODEFVAL "pll_powerdown[0..0]"
|
1667 |
|
|
// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
|
1668 |
|
|
// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 17 0 OUTPUT NODEFVAL "reconfig_fromgxb[16..0]"
|
1669 |
|
|
// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]"
|
1670 |
|
|
// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
|
1671 |
|
|
// Retrieval info: USED_PORT: rx_clkout 0 0 0 0 OUTPUT NODEFVAL "rx_clkout"
|
1672 |
|
|
// Retrieval info: USED_PORT: rx_cruclk 0 0 1 0 INPUT GND "rx_cruclk[0..0]"
|
1673 |
|
|
// Retrieval info: USED_PORT: rx_ctrldetect 0 0 1 0 OUTPUT NODEFVAL "rx_ctrldetect[0..0]"
|
1674 |
|
|
// Retrieval info: USED_PORT: rx_datain 0 0 1 0 INPUT NODEFVAL "rx_datain[0..0]"
|
1675 |
|
|
// Retrieval info: USED_PORT: rx_dataout 0 0 8 0 OUTPUT NODEFVAL "rx_dataout[7..0]"
|
1676 |
|
|
// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
|
1677 |
|
|
// Retrieval info: USED_PORT: rx_disperr 0 0 1 0 OUTPUT NODEFVAL "rx_disperr[0..0]"
|
1678 |
|
|
// Retrieval info: USED_PORT: rx_errdetect 0 0 1 0 OUTPUT NODEFVAL "rx_errdetect[0..0]"
|
1679 |
|
|
// Retrieval info: USED_PORT: rx_freqlocked 0 0 1 0 OUTPUT NODEFVAL "rx_freqlocked[0..0]"
|
1680 |
|
|
// Retrieval info: USED_PORT: rx_patterndetect 0 0 1 0 OUTPUT NODEFVAL "rx_patterndetect[0..0]"
|
1681 |
|
|
// Retrieval info: USED_PORT: rx_recovclkout 0 0 1 0 OUTPUT NODEFVAL "rx_recovclkout[0..0]"
|
1682 |
|
|
// Retrieval info: USED_PORT: rx_rlv 0 0 1 0 OUTPUT NODEFVAL "rx_rlv[0..0]"
|
1683 |
|
|
// Retrieval info: USED_PORT: rx_rmfifodatadeleted 0 0 1 0 OUTPUT NODEFVAL "rx_rmfifodatadeleted[0..0]"
|
1684 |
|
|
// Retrieval info: USED_PORT: rx_rmfifodatainserted 0 0 1 0 OUTPUT NODEFVAL "rx_rmfifodatainserted[0..0]"
|
1685 |
|
|
// Retrieval info: USED_PORT: rx_runningdisp 0 0 1 0 OUTPUT NODEFVAL "rx_runningdisp[0..0]"
|
1686 |
|
|
// Retrieval info: USED_PORT: rx_seriallpbken 0 0 1 0 INPUT NODEFVAL "rx_seriallpbken[0..0]"
|
1687 |
|
|
// Retrieval info: USED_PORT: rx_syncstatus 0 0 1 0 OUTPUT NODEFVAL "rx_syncstatus[0..0]"
|
1688 |
|
|
// Retrieval info: USED_PORT: tx_clkout 0 0 1 0 OUTPUT NODEFVAL "tx_clkout[0..0]"
|
1689 |
|
|
// Retrieval info: USED_PORT: tx_ctrlenable 0 0 1 0 INPUT NODEFVAL "tx_ctrlenable[0..0]"
|
1690 |
|
|
// Retrieval info: USED_PORT: tx_datain 0 0 8 0 INPUT NODEFVAL "tx_datain[7..0]"
|
1691 |
|
|
// Retrieval info: USED_PORT: tx_dataout 0 0 1 0 OUTPUT NODEFVAL "tx_dataout[0..0]"
|
1692 |
|
|
// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
|
1693 |
|
|
// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
|
1694 |
|
|
// Retrieval info: CONNECT: @fixedclk 0 0 0 0 fixedclk 0 0 0 0
|
1695 |
|
|
// Retrieval info: CONNECT: @fixedclk_fast 0 0 0 0 fixedclk_fast 0 0 0 0
|
1696 |
|
|
// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
|
1697 |
|
|
// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
|
1698 |
|
|
// Retrieval info: CONNECT: @pll_powerdown 0 0 1 0 pll_powerdown 0 0 1 0
|
1699 |
|
|
// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
|
1700 |
|
|
// Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
|
1701 |
|
|
// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
|
1702 |
|
|
// Retrieval info: CONNECT: @rx_cruclk 0 0 1 0 rx_cruclk 0 0 1 0
|
1703 |
|
|
// Retrieval info: CONNECT: @rx_datain 0 0 1 0 rx_datain 0 0 1 0
|
1704 |
|
|
// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
|
1705 |
|
|
// Retrieval info: CONNECT: @rx_seriallpbken 0 0 1 0 rx_seriallpbken 0 0 1 0
|
1706 |
|
|
// Retrieval info: CONNECT: @tx_ctrlenable 0 0 1 0 tx_ctrlenable 0 0 1 0
|
1707 |
|
|
// Retrieval info: CONNECT: @tx_datain 0 0 8 0 tx_datain 0 0 8 0
|
1708 |
|
|
// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
|
1709 |
|
|
// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
|
1710 |
|
|
// Retrieval info: CONNECT: reconfig_fromgxb 0 0 17 0 @reconfig_fromgxb 0 0 17 0
|
1711 |
|
|
// Retrieval info: CONNECT: rx_clkout 0 0 0 0 @rx_clkout 0 0 0 0
|
1712 |
|
|
// Retrieval info: CONNECT: rx_ctrldetect 0 0 1 0 @rx_ctrldetect 0 0 1 0
|
1713 |
|
|
// Retrieval info: CONNECT: rx_dataout 0 0 8 0 @rx_dataout 0 0 8 0
|
1714 |
|
|
// Retrieval info: CONNECT: rx_disperr 0 0 1 0 @rx_disperr 0 0 1 0
|
1715 |
|
|
// Retrieval info: CONNECT: rx_errdetect 0 0 1 0 @rx_errdetect 0 0 1 0
|
1716 |
|
|
// Retrieval info: CONNECT: rx_freqlocked 0 0 1 0 @rx_freqlocked 0 0 1 0
|
1717 |
|
|
// Retrieval info: CONNECT: rx_patterndetect 0 0 1 0 @rx_patterndetect 0 0 1 0
|
1718 |
|
|
// Retrieval info: CONNECT: rx_recovclkout 0 0 1 0 @rx_recovclkout 0 0 1 0
|
1719 |
|
|
// Retrieval info: CONNECT: rx_rlv 0 0 1 0 @rx_rlv 0 0 1 0
|
1720 |
|
|
// Retrieval info: CONNECT: rx_rmfifodatadeleted 0 0 1 0 @rx_rmfifodatadeleted 0 0 1 0
|
1721 |
|
|
// Retrieval info: CONNECT: rx_rmfifodatainserted 0 0 1 0 @rx_rmfifodatainserted 0 0 1 0
|
1722 |
|
|
// Retrieval info: CONNECT: rx_runningdisp 0 0 1 0 @rx_runningdisp 0 0 1 0
|
1723 |
|
|
// Retrieval info: CONNECT: rx_syncstatus 0 0 1 0 @rx_syncstatus 0 0 1 0
|
1724 |
|
|
// Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0
|
1725 |
|
|
// Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0
|
1726 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige.v TRUE
|
1727 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige.ppf TRUE
|
1728 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige.inc FALSE
|
1729 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige.cmp FALSE
|
1730 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige.bsf FALSE
|
1731 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige_inst.v FALSE
|
1732 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_alt4gxb_gige_bb.v TRUE
|
1733 |
|
|
// Retrieval info: LIB_FILE: stratixiv_hssi
|