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https://opencores.org/ocsvn/sgmii/sgmii/trunk
[/] [sgmii/] [trunk/] [sim/] [Sim_SGMII1000Mblvds.do] - Blame information for rev 18
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jefflieu |
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set incDir {../src+../src/mAltGX}
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set srcDir {../src}
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jefflieu |
set SrcFiles {mANCtrl.v mReceive.v mTransmit.v mSyncCtrl.v mSGMII.v mXcver.v mSyncFifo.v mRegisters.v mClkBuf.v mRateAdapter.v mEnc8b10bMem.v mDec8b10bMem.v}
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jefflieu |
set BfmDir {./BFMs}
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set BfmFiles {mWishboneMstr.v}
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foreach src $SrcFiles {
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vlog +incdir+$incDir $srcDir/$src
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}
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foreach bfm $BfmFiles {
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vlog +incdir+$BfmDir $BfmDir/$bfm
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}
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#core files
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#library
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set AltLibDir {C:/altera/12.0full/quartus/eda/sim_lib}
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vlog $AltLibDir/altera_mf.v
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vlog $AltLibDir/220model.v
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vlog $AltLibDir/sgate.v
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vlog $AltLibDir/altera_primitives.v
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vlog $AltLibDir/arriav_atoms.v
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vlog $AltLibDir/arriav_hssi_atoms.v
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vlog +incdir+$incDir ../src/mAltGX/mAltGX.v
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vlog +incdir+$incDir ../src/mAltGX/mAltGXReconfig.v
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vlog +incdir+$incDir ../src/mAltGX/mAltRateAdapter.v
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vlog +incdir+$incDir ../src/mAltGX/mAltArriaVlvdsRx.v
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vlog +incdir+$incDir ../src/mAltGX/mAltArriaVlvdsTx.v
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vlog +incdir+$incDir ../src/mAltGX/mAltA5GXlvds.v
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vlog +incdir+$incDir ../src/mAltGX/mAlt8b10benc.vo
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vlog +incdir+$incDir ../src/mAltGX/mAlt8b10bdec.vo
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vlog mMACEmulator.sv
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vlog Testbench_AltGXB_SGMII1000Mbps.sv +incdir+../src/+./
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#vlog Testbench_AltGXB_SGMII1000Mbps.sv +incdir+../src/+./
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#vlog Testbench_1000Mb.v +incdir+../src/+./
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set AltModel BFMs/SGMII_altera/testbench/sgmii
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vlog -work work $AltModel/../../sgmii.vo
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vlog -work work $AltModel/../model/*.v
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vlog -work work $AltModel/*.v
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vsim mSGMIITestbench
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