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jefflieu |
/*
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Developed by Jeff Lieu (lieumychuong@gmail.com)
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File :
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Description :
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In this test, we use Altera Tranceiver as Link Partner
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Configure bothside to be 1000BaseX Mode
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Remarks :
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There seems to be a bug in Altera's core, tx path
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- The Tx Path sometime omits 1 pre-ample octet depending on the cycle that TxEN is aserted.
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- At the transmit task, the #8 delay will have effect on the Altera's core. Without delay,
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the first packet is transmitted with the first octet somehow removed (you can confirm this
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by looking at the Codegroup that is input of u0SGMII/u0Receive/
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- With the delay on, the first packet is fine, but the second packet has some problem.
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- This has something todo with the alignment of the TxEN,
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I'm not sure whether the MAC layer is responsible for aligning TxEN's assertion or not.
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- This test only Transmits normal frame, i.e no Carrier Extension or Error Propagation
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- The Path of U0 --> U1 is ok.
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- Testing with Version 11.1sp2 core seems to be ok, this problem is not found
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Revision :
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Date Author Description
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*/
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`timescale 1ns/1ps
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`include "SGMIIDefs.v"
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module mSGMIITestbench();
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`include "Veritil.v"
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reg r_Reset_L;
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reg r_Clk125M;
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reg r_Clk50M;
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wire w_u1RxClk;
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wire w_u1TxClk;
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wire w_u1RxDV;
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wire w_u1RxER;
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wire [07:00] w8_u1RxD;
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wire [07:00] w8_u1TxD;
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wire w_u1TxEN;
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wire w_u1TxER;
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wire w_u0RxDV;
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wire w_u0RxER;
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wire [07:00] w8_u0RxD;
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wire [07:00] w8_u0TxD;
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wire w_u0TxEN;
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wire w_u0TxER;
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wire w_u0WbCyc, w_u0WbAck, w_u0WbStb, w_u0WbWEn;
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wire [31:00] w32_u0WbAddr, w32_u0WbWrData, w32_u0WbRdData;
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wire w_u1WbCyc, w_u1WbAck, w_u1WbStb, w_u1WbWEn;
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wire [31:00] w32_u1WbAddr, w32_u1WbWrData, w32_u1WbRdData;
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wire w_u0ANDone,w_u1ANDone;
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`define tstcfg_Normal 0
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`define tstcfg_CarrierExt 1
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`define tstcfg_BurstTrans 2
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`define tstcfg_ErrorProp1 3
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`define tstcfg_ErrorProp2 4
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`define tstcfg_SizeXShort 0
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`define tstcfg_SizeShort 1
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`define tstcfg_SizeMedium 2
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`define tstcfg_SizeLarge 3
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`define tstcfg_SizeXLarge 4
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`define tstcfg_1000X 0
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`define tstcfg_SGMII1G 1
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`define tstcfg_SGMII100M 2
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integer tstcfg_Standard;
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integer tstcfg_PktSize;
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integer tstcfg_Type;
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integer tstcfg_Seed;
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integer tstcfg_TxPktCnt;
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integer tstcfg_RxPktCnt;
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reg [15:00] r16_CoreVersion;
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wire [01:00] w2_u0Speed;
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initial r_Clk125M <= 1'b0;
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initial r_Clk50M <= 1'b0;
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always@*
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#4 r_Clk125M <= ~r_Clk125M;
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always@*
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#10 r_Clk50M <= ~r_Clk50M;
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wire w_u0Rx,w_u0Tx;
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wire w_u1Rx,w_u1Tx;
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initial
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begin
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$display("------------------------------------");
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$display("-------Subtleware Ltd Pte 2012------");
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$display("--Testing SGMII in SGMII 1000Gb Mode------");
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15 |
jefflieu |
$display("------------------------------------");
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10 |
jefflieu |
tstcfg_TxPktCnt = 0;
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tstcfg_RxPktCnt = 0;
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r_Reset_L <= 1'b0;
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#1000;
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r_Reset_L <= 1'b1;
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15 |
jefflieu |
#1000;
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u0WishboneMstr.tsk_Read((10<<2),r16_CoreVersion);
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$display("---Core Version : %x", r16_CoreVersion);
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10 |
jefflieu |
tsk_Setup();
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end
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mWishboneMstr u0WishboneMstr(
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.o_WbCyc (w_u0WbCyc),
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.o_WbStb (w_u0WbStb),
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.o_WbWEn (w_u0WbWEn),
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.ov_WbAddr (w32_u0WbAddr),
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.ov_WbWrData(w32_u0WbWrData),
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.iv_WbRdData(w32_u0WbRdData),
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.i_Ack (w_u0WbAck),
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.i_Stall (1'b0),
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.i_Rty (1'b0),
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.i_Clk (w_u0GMIIClk));
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mWishboneMstr u1WishboneMstr(
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.o_WbCyc (w_u1WbCyc),
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.o_WbStb (w_u1WbStb),
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.o_WbWEn (w_u1WbWEn),
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.ov_WbAddr (w32_u1WbAddr),
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.ov_WbWrData(w32_u1WbWrData),
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.iv_WbRdData(w32_u1WbRdData),
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.i_Ack (w_u1WbAck),
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.i_Stall (1'b0),
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.i_Rty (1'b0),
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.i_Clk (w_u1RxClk));
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//Tranceiver Interface
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mSGMII u0SGMII (
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.i_SerRx (w_u0Rx),
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.o_SerTx (w_u0Tx),
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.i_CalClk (r_Clk50M),
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.i_RefClk125M (r_Clk125M),
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.i_ARstHardware_L (r_Reset_L),
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//Local BUS interface
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//Wishbonebus, single transaction mode (non-pipeline slave)
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.i_Cyc (w_u0WbCyc),
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.i_Stb (w_u0WbStb),
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.i_WEn (w_u0WbWEn),
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.i32_WrData (w32_u0WbWrData),
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.iv_Addr (w32_u0WbAddr[7:0]),
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.o32_RdData (w32_u0WbRdData),
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.o_Ack (w_u0WbAck),
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.i_Mdc (1'b0),
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.io_Mdio (),
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.i_PhyLink (1'b1),
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.i2_PhySpeed(2'b00),
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.i_PhyDuplex(1'b0),
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//Status
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.o_ANDone (w_u0ANDone),
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.o_Linkup (w_u0LinkUp),
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.o2_SGMIISpeed (w2_u0Speed),
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.o_SGMIIDuplex (w_u0Duplex),
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//GMII Interface
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.i8_TxD (w8_u0TxD),
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.i_TxEN (w_u0TxEN),
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.i_TxER (w_u0TxER),
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.o8_RxD (w8_u0RxD),
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.o_RxDV (w_u0RxDV),
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.o_RxER (w_u0RxER),
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.o_GMIIClk (w_u0GMIIClk),
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.o_Col (),
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.o_Crs ());
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sgmii u1SGMII (
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.gmii_rx_d (w8_u1RxD),
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.gmii_rx_dv (w_u1RxDV),
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.gmii_rx_err (w_u1RxER),
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.gmii_tx_d (w8_u1TxD),
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.gmii_tx_en (w_u1TxEN),
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.gmii_tx_err (w_u1TxER),
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.tx_clk (w_u1TxClk),//output,
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.rx_clk (w_u1RxClk),
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.led_an (w_u1ANDone),
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.led_disp_err (),
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.led_char_err (),
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.led_link (w_led_link),
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.rx_recovclkout (),
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.rxp (w_u1Rx),
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.txp (w_u1Tx),
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.pcs_pwrdn_out (),
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.reconfig_fromgxb (),
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.reset_tx_clk (~r_Reset_L),
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.reset_rx_clk (~r_Reset_L),
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.readdata (w32_u1WbRdData[15:00]),
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.waitrequest (w_AvlWaitReq),
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.address (w32_u1WbAddr[6:2]),
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.read (w_AvlRd),
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.writedata (w32_u1WbWrData[15:00]),
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.write (w_AvlWr),
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.clk (w_u1RxClk),
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.reset (~r_Reset_L),
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.ref_clk (r_Clk125M),
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.gxb_pwrdn_in (1'b0),
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.gxb_cal_blk_clk (r_Clk50M),
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.reconfig_clk (r_Clk50M),
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.reconfig_togxb (5'b0),
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.reconfig_busy ());
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//MacEmulation
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mMACEmulator u0MacEmulator(
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.i_RxClk (w_u0GMIIClk),
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.i_TxClk (w_u0GMIIClk),
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.i8_RxD (w8_u0RxD),
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.i_RxDV (w_u0RxDV),
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.i_RxER (w_u0RxER),
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.o8_TxD (w8_u0TxD),
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.o_TxEN (w_u0TxEN),
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.o_TxER (w_u0TxER),
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.i_Reset_L(r_Reset_L));
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mMACEmulator u1MacEmulator(
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.i_RxClk (w_u1RxClk),
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.i_TxClk (w_u1TxClk),
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.i8_RxD (w8_u1RxD),
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.i_RxDV (w_u1RxDV),
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.i_RxER (w_u1RxER),
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.o8_TxD (w8_u1TxD),
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.o_TxEN (w_u1TxEN),
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.o_TxER (w_u1TxER),
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.i_Reset_L(r_Reset_L));
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//This portion translate Wishbone Signal to Avalon Signal
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assign w_AvlWr = w_u1WbStb & w_u1WbCyc & w_u1WbWEn;
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assign w_AvlRd = w_u1WbStb & w_u1WbCyc & (~w_u1WbWEn);
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assign w_u1WbAck = ~w_AvlWaitReq;
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assign w_u0Rx = w_u1Tx;
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assign w_u1Rx = w_u0Tx;
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reg [7:0] r8_TxBuffer[0:1023][0:10000];
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integer s32_TxCarrierExtCycles[0:1023];
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integer s32_TxCarrierErrCycles[0:1023];
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reg [7:0] r8_u0RxBuffer[0:1023][0:10000];
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reg [7:0] r8_u1RxBuffer[0:1023][0:10000];
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reg [15:00] r16_u0Ability;
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reg [15:00] r16_u1Ability;
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reg [31:00] r32_ReadData;
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integer I;
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integer length;
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integer u0RxPktCnt,u1RxPktCnt;
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integer u0ExtCycles,u1ExtCycles;
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integer u0ErrCycles,u1ErrCycles;
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integer u0FrameSize,u1FrameSize;
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initial
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begin
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length = 100;
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#100;
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$display("Waiting for Auto Negotiation Done");
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#100;
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while(w_u0ANDone==1'b0)
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begin
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@(posedge w_u0GMIIClk);#1;
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end
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//Verify link partner ability
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u0WishboneMstr.tsk_Read(16'h14,r32_ReadData);
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`CheckE(r32_ReadData[15:00],r16_u1Ability,"Link Partner Advertised Ability")
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u1WishboneMstr.tsk_Read(16'h14,r32_ReadData);
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`CheckE(r32_ReadData[15:00],r16_u0Ability,"Link Partner Advertised Ability")
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#1000;
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$display("Start Generating Scenarios");
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for(I=0;I<1000;I=I+1)
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tsk_ScenariosGenerator();
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$display("Test Result: %s (Error Count = %d)",ErrorCnt>0?"FAILED":"PASSED",ErrorCnt);
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#3000;
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end
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initial
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begin:u1Receiving
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u1RxPktCnt=0;
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$display("Waiting for Auto Negotiation Done");
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#100;
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while(w_u1ANDone==1'b0)
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begin
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@(posedge w_u1RxClk);#1;
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end
|
| 319 |
|
|
forever
|
| 320 |
|
|
begin
|
| 321 |
|
|
u1MacEmulator.tsk_ReceivePkt(r8_u1RxBuffer[u1RxPktCnt],u1FrameSize,u1ExtCycles,u1ErrCycles);
|
| 322 |
|
|
u1FrameSize--;
|
| 323 |
|
|
while(u1FrameSize>=0)
|
| 324 |
|
|
begin
|
| 325 |
|
|
`CheckF(r8_u1RxBuffer[u1RxPktCnt][u1FrameSize],r8_TxBuffer[u1RxPktCnt][u1FrameSize],"Received byte")
|
| 326 |
|
|
u1FrameSize--;
|
| 327 |
|
|
end
|
| 328 |
|
|
u1RxPktCnt=u1RxPktCnt+1;
|
| 329 |
|
|
$display("u1: Checked Pkt %d",u1RxPktCnt);
|
| 330 |
|
|
end
|
| 331 |
|
|
|
| 332 |
|
|
end
|
| 333 |
|
|
|
| 334 |
|
|
initial
|
| 335 |
|
|
begin:u0Receiving
|
| 336 |
|
|
u0RxPktCnt=0;
|
| 337 |
|
|
$display("Waiting for Auto Negotiation Done");
|
| 338 |
|
|
#100;
|
| 339 |
|
|
while(w_u0ANDone==1'b0)
|
| 340 |
|
|
begin
|
| 341 |
|
|
@(posedge w_u0GMIIClk);#1;
|
| 342 |
|
|
end
|
| 343 |
|
|
forever
|
| 344 |
|
|
begin
|
| 345 |
|
|
u0MacEmulator.tsk_ReceivePkt(r8_u0RxBuffer[u0RxPktCnt],u0FrameSize,u0ExtCycles,u0ErrCycles);
|
| 346 |
|
|
u0FrameSize--;
|
| 347 |
|
|
while(u0FrameSize>=0)
|
| 348 |
|
|
begin
|
| 349 |
|
|
`CheckF(r8_u0RxBuffer[u0RxPktCnt][u0FrameSize],r8_TxBuffer[u0RxPktCnt][u0FrameSize],"Received byte")
|
| 350 |
|
|
u0FrameSize--;
|
| 351 |
|
|
end
|
| 352 |
|
|
u0RxPktCnt=u0RxPktCnt+1;
|
| 353 |
|
|
$display("u0: Checked Pkt %d",u0RxPktCnt);
|
| 354 |
|
|
end
|
| 355 |
|
|
|
| 356 |
|
|
end
|
| 357 |
|
|
|
| 358 |
|
|
|
| 359 |
|
|
|
| 360 |
|
|
task tsk_Setup;
|
| 361 |
|
|
begin
|
| 362 |
|
|
//U1 is ALTERA's
|
| 363 |
|
|
u1WishboneMstr.tsk_Read(7'b10001_00,r16_CoreVersion);
|
| 364 |
|
|
$display("Altera SGMII Core Version %x",r16_CoreVersion);
|
| 365 |
|
|
|
| 366 |
|
|
u1WishboneMstr.tsk_Write(0,32'h0000_1000); //Enable Auto-Negotiation
|
| 367 |
|
|
r16_u1Ability=16'h1400;
|
| 368 |
|
|
u1WishboneMstr.tsk_Write(7'b00100_00,r16_u1Ability); //Set Dev Ability
|
| 369 |
|
|
|
| 370 |
|
|
u1WishboneMstr.tsk_Write(7'b10010_00,32'h01E2); //Set Link Timer to 10000 ns
|
| 371 |
|
|
u1WishboneMstr.tsk_Write(7'b10011_00,32'h0000);
|
| 372 |
|
|
u1WishboneMstr.tsk_Read(7'b10010_00,r16_CoreVersion);
|
| 373 |
|
|
$display("Link Timer 0 %x",r16_CoreVersion);
|
| 374 |
|
|
u1WishboneMstr.tsk_Read(7'b10011_00,r16_CoreVersion);
|
| 375 |
|
|
$display("Link Timer 1 %x",r16_CoreVersion);
|
| 376 |
|
|
u1WishboneMstr.tsk_Write(7'b10100_00,{27'h0,1'b1,4'b0011}); //Enable SGMII Mode,
|
| 377 |
|
|
u1WishboneMstr.tsk_Read(7'b10100_00,r16_CoreVersion);
|
| 378 |
|
|
$display("Mode Register 1 %x",r16_CoreVersion);
|
| 379 |
|
|
|
| 380 |
|
|
|
| 381 |
|
|
//U0 is MINE
|
| 382 |
|
|
r16_u0Ability=16'h1800;
|
| 383 |
|
|
u0WishboneMstr.tsk_Write(7'b00100_00,r16_u0Ability); //Set Dev Ability, this is advertised information
|
| 384 |
|
|
u0WishboneMstr.tsk_Write((8<<2),32'h0000_01E2); //Set Link Timer to 2500 ns
|
| 385 |
|
|
u0WishboneMstr.tsk_Write((9<<2),32'h0000_0000);
|
| 386 |
|
|
u0WishboneMstr.tsk_Write((31<<2),32'h0007); //Enable SGMII, PHY Side
|
| 387 |
|
|
$display("Restart PHY auto-nego");
|
| 388 |
|
|
u0WishboneMstr.tsk_Write(0,32'h0000_1340); //Restart Auto-negotiation, set Full Duplex, 1000Mbps
|
| 389 |
|
|
|
| 390 |
|
|
end
|
| 391 |
|
|
endtask
|
| 392 |
|
|
|
| 393 |
|
|
task tsk_ScenariosGenerator;
|
| 394 |
|
|
//Generate Type of Transmission
|
| 395 |
|
|
begin
|
| 396 |
|
|
tstcfg_Seed = $random;
|
| 397 |
|
|
tstcfg_Type = $dist_uniform(tstcfg_Seed,0,4);
|
| 398 |
|
|
tstcfg_Type = `tstcfg_Normal;
|
| 399 |
|
|
case(tstcfg_Type)
|
| 400 |
|
|
`tstcfg_Normal: begin $display("Transmit Type Normal"); tsk_TransmitNormal(); end
|
| 401 |
|
|
`tstcfg_BurstTrans: begin $display("Transmit Type Burst"); tsk_TransmitBurst(); end
|
| 402 |
|
|
`tstcfg_CarrierExt: begin $display("Transmit Type Carrier Extension"); tsk_TransmitCarrExt(); end
|
| 403 |
|
|
`tstcfg_ErrorProp1: begin $display("Transmit Type Error Prop within Frame"); tsk_TransmitErrInFrame(); end
|
| 404 |
|
|
`tstcfg_ErrorProp2: begin $display("Transmit Type Error Prop out of Frame"); tsk_TransmitErrOutFrame();end
|
| 405 |
|
|
endcase
|
| 406 |
|
|
|
| 407 |
|
|
end
|
| 408 |
|
|
endtask
|
| 409 |
|
|
|
| 410 |
|
|
task tsk_TransmitNormal;
|
| 411 |
|
|
integer PktSize;
|
| 412 |
|
|
integer PktNum;
|
| 413 |
|
|
integer PktIFG;
|
| 414 |
|
|
integer Idx;
|
| 415 |
|
|
integer Octet;
|
| 416 |
|
|
begin
|
| 417 |
|
|
PktNum = $dist_uniform(tstcfg_Seed,1,10);//From 1 to 10
|
| 418 |
|
|
for(Idx=0;Idx
|
| 419 |
|
|
begin
|
| 420 |
|
|
PktIFG = $dist_uniform(tstcfg_Seed,10,14);//From 2 to 10
|
| 421 |
|
|
tstcfg_PktSize = $dist_uniform(tstcfg_Seed,0,4);
|
| 422 |
|
|
|
| 423 |
|
|
case(tstcfg_PktSize)
|
| 424 |
|
|
`tstcfg_SizeXShort : PktSize = $dist_uniform(tstcfg_Seed,64,128);
|
| 425 |
|
|
`tstcfg_SizeShort : PktSize = $dist_uniform(tstcfg_Seed,128,512);
|
| 426 |
|
|
`tstcfg_SizeMedium : PktSize = $dist_uniform(tstcfg_Seed,512,1024);
|
| 427 |
|
|
`tstcfg_SizeLarge : PktSize = $dist_uniform(tstcfg_Seed,1024,1518);
|
| 428 |
|
|
`tstcfg_SizeXLarge : PktSize = $dist_uniform(tstcfg_Seed,1518,9000);
|
| 429 |
|
|
endcase
|
| 430 |
|
|
|
| 431 |
|
|
s32_TxCarrierExtCycles[tstcfg_TxPktCnt+Idx]=(PktSize&32'h1)?1:0;
|
| 432 |
|
|
s32_TxCarrierErrCycles[tstcfg_TxPktCnt+Idx]=0;
|
| 433 |
|
|
for(Octet=0;Octet
|
| 434 |
|
|
begin
|
| 435 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][Octet]=$random;
|
| 436 |
|
|
end
|
| 437 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][8]=PktSize & 32'h00FF;
|
| 438 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][9]=((PktSize & 32'hFF00)>>8);
|
| 439 |
|
|
//Transmit:
|
| 440 |
|
|
|
| 441 |
|
|
fork
|
| 442 |
|
|
begin
|
| 443 |
|
|
$display("u0: Sending Packet %d Size %d",tstcfg_TxPktCnt+Idx,PktSize);
|
| 444 |
|
|
u0MacEmulator.tsk_TransmitPkt(r8_TxBuffer[tstcfg_TxPktCnt+Idx],PktSize,PktIFG);
|
| 445 |
|
|
end
|
| 446 |
|
|
begin
|
| 447 |
|
|
$display("u1: Sending Packet %d Size %d",tstcfg_TxPktCnt+Idx,PktSize);
|
| 448 |
|
|
//#8; //If You Remove This Delay, you will have error in first packet.
|
| 449 |
|
|
u1MacEmulator.tsk_TransmitPkt(r8_TxBuffer[tstcfg_TxPktCnt+Idx],PktSize,PktIFG);
|
| 450 |
|
|
end
|
| 451 |
|
|
join
|
| 452 |
|
|
|
| 453 |
|
|
|
| 454 |
|
|
end
|
| 455 |
|
|
tstcfg_TxPktCnt = tstcfg_TxPktCnt+PktNum;
|
| 456 |
|
|
|
| 457 |
|
|
end
|
| 458 |
|
|
endtask
|
| 459 |
|
|
|
| 460 |
|
|
|
| 461 |
|
|
task tsk_TransmitBurst;
|
| 462 |
|
|
integer PktSize;
|
| 463 |
|
|
integer PktNum;
|
| 464 |
|
|
integer PktIFG;
|
| 465 |
|
|
integer Idx;
|
| 466 |
|
|
integer Octet;
|
| 467 |
|
|
integer ExtCycles;
|
| 468 |
|
|
integer TotalExtCycles;
|
| 469 |
|
|
integer TotalBytes;
|
| 470 |
|
|
integer PktStartOffset;
|
| 471 |
|
|
begin
|
| 472 |
|
|
PktNum = $dist_uniform(tstcfg_Seed,1,6);//From 1 to 10
|
| 473 |
|
|
PktIFG = $dist_uniform(tstcfg_Seed,10,14);//From 2 to 10
|
| 474 |
|
|
s32_TxCarrierExtCycles[tstcfg_TxPktCnt]=0;
|
| 475 |
|
|
TotalBytes=0;
|
| 476 |
|
|
TotalExtCycles=0;
|
| 477 |
|
|
PktStartOffset=0;
|
| 478 |
|
|
$display("Bursting : %d packets",PktNum);
|
| 479 |
|
|
for(Idx=0;Idx
|
| 480 |
|
|
begin
|
| 481 |
|
|
tstcfg_PktSize = $dist_uniform(tstcfg_Seed,0,3); //Nojumbo
|
| 482 |
|
|
ExtCycles = $dist_uniform(tstcfg_Seed,3,5);//Burst must have at least 2 /R/ interpacket R
|
| 483 |
|
|
|
| 484 |
|
|
case(tstcfg_PktSize)
|
| 485 |
|
|
`tstcfg_SizeXShort : PktSize = $dist_uniform(tstcfg_Seed,64,128);
|
| 486 |
|
|
`tstcfg_SizeShort : PktSize = $dist_uniform(tstcfg_Seed,128,512);
|
| 487 |
|
|
`tstcfg_SizeMedium : PktSize = $dist_uniform(tstcfg_Seed,512,1024);
|
| 488 |
|
|
`tstcfg_SizeLarge : PktSize = $dist_uniform(tstcfg_Seed,1024,1518);
|
| 489 |
|
|
`tstcfg_SizeXLarge : PktSize = $dist_uniform(tstcfg_Seed,1518,9000);
|
| 490 |
|
|
endcase
|
| 491 |
|
|
|
| 492 |
|
|
TotalExtCycles=TotalExtCycles+ExtCycles;
|
| 493 |
|
|
TotalBytes = TotalBytes+PktSize;
|
| 494 |
|
|
|
| 495 |
|
|
//Generate Packet
|
| 496 |
|
|
for(Octet=0;Octet
|
| 497 |
|
|
begin
|
| 498 |
|
|
if(Octet<7)
|
| 499 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt][PktStartOffset+Octet]=8'h55;
|
| 500 |
|
|
else if(Octet==7)
|
| 501 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt][PktStartOffset+Octet]=8'hD5;
|
| 502 |
|
|
else
|
| 503 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt][PktStartOffset+Octet]=$random;
|
| 504 |
|
|
end
|
| 505 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt][PktStartOffset+8]=PktSize & 32'h00FF;
|
| 506 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt][PktStartOffset+9]=((PktSize & 32'hFF00)>>8);
|
| 507 |
|
|
//Transmit:
|
| 508 |
|
|
$display("Not complete task");
|
| 509 |
|
|
$display("Sender : Sending Packet %d (part %d) Size %d",tstcfg_TxPktCnt,Idx,PktSize);
|
| 510 |
|
|
end
|
| 511 |
|
|
//Send Interframe Gap
|
| 512 |
|
|
s32_TxCarrierErrCycles[tstcfg_TxPktCnt]=0;
|
| 513 |
|
|
s32_TxCarrierExtCycles[tstcfg_TxPktCnt]=((TotalBytes+TotalExtCycles)&32'h1)?(TotalExtCycles+1):TotalExtCycles;
|
| 514 |
|
|
tstcfg_TxPktCnt = tstcfg_TxPktCnt+1;
|
| 515 |
|
|
end
|
| 516 |
|
|
endtask
|
| 517 |
|
|
|
| 518 |
|
|
task tsk_TransmitCarrExt;
|
| 519 |
|
|
integer PktSize;
|
| 520 |
|
|
integer PktNum;
|
| 521 |
|
|
integer PktIFG;
|
| 522 |
|
|
integer Idx;
|
| 523 |
|
|
integer Octet;
|
| 524 |
|
|
integer ExtCycles;
|
| 525 |
|
|
begin
|
| 526 |
|
|
PktNum = $dist_uniform(tstcfg_Seed,1,10);//From 1 to 10
|
| 527 |
|
|
for(Idx=0;Idx
|
| 528 |
|
|
begin
|
| 529 |
|
|
PktIFG = $dist_uniform(tstcfg_Seed,10,14);//From 2 to 10
|
| 530 |
|
|
tstcfg_PktSize = $dist_uniform(tstcfg_Seed,0,4);
|
| 531 |
|
|
ExtCycles = $dist_uniform(tstcfg_Seed,1,100);//From 2 to 10
|
| 532 |
|
|
|
| 533 |
|
|
case(tstcfg_PktSize)
|
| 534 |
|
|
`tstcfg_SizeXShort : PktSize = $dist_uniform(tstcfg_Seed,64,128);
|
| 535 |
|
|
`tstcfg_SizeShort : PktSize = $dist_uniform(tstcfg_Seed,128,512);
|
| 536 |
|
|
`tstcfg_SizeMedium : PktSize = $dist_uniform(tstcfg_Seed,512,1024);
|
| 537 |
|
|
`tstcfg_SizeLarge : PktSize = $dist_uniform(tstcfg_Seed,1024,1518);
|
| 538 |
|
|
`tstcfg_SizeXLarge : PktSize = $dist_uniform(tstcfg_Seed,1518,9000);
|
| 539 |
|
|
endcase
|
| 540 |
|
|
|
| 541 |
|
|
s32_TxCarrierExtCycles[tstcfg_TxPktCnt+Idx]=((PktSize+ExtCycles)&32'h1)?ExtCycles+1:ExtCycles;
|
| 542 |
|
|
s32_TxCarrierErrCycles[tstcfg_TxPktCnt+Idx]=0;
|
| 543 |
|
|
//Generate Packet
|
| 544 |
|
|
for(Octet=0;Octet
|
| 545 |
|
|
begin
|
| 546 |
|
|
if(Octet<7)
|
| 547 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][Octet]=8'h55;
|
| 548 |
|
|
else if(Octet==7)
|
| 549 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][Octet]=8'hD5;
|
| 550 |
|
|
else
|
| 551 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][Octet]=$random;
|
| 552 |
|
|
end
|
| 553 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][8]=PktSize & 32'h00FF;
|
| 554 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][9]=((PktSize & 32'hFF00)>>8);
|
| 555 |
|
|
//Transmit:
|
| 556 |
|
|
$display("Not complete task");
|
| 557 |
|
|
$display("Sender : Sending Packet %d Size %d",(tstcfg_TxPktCnt+Idx),PktSize);
|
| 558 |
|
|
end
|
| 559 |
|
|
tstcfg_TxPktCnt = tstcfg_TxPktCnt+PktNum;
|
| 560 |
|
|
end
|
| 561 |
|
|
endtask
|
| 562 |
|
|
|
| 563 |
|
|
task tsk_TransmitErrInFrame;
|
| 564 |
|
|
integer PktSize;
|
| 565 |
|
|
integer PktNum;
|
| 566 |
|
|
integer PktIFG;
|
| 567 |
|
|
integer Idx;
|
| 568 |
|
|
integer Octet;
|
| 569 |
|
|
integer ErrorCycle;
|
| 570 |
|
|
integer ErrorPos;
|
| 571 |
|
|
begin
|
| 572 |
|
|
PktNum = $dist_uniform(tstcfg_Seed,1,10);//From 1 to 10
|
| 573 |
|
|
ErrorCycle = $dist_uniform(tstcfg_Seed,1,10);//From 1 to 10
|
| 574 |
|
|
|
| 575 |
|
|
for(Idx=0;Idx
|
| 576 |
|
|
begin
|
| 577 |
|
|
PktIFG = $dist_uniform(tstcfg_Seed,10,14);//From 2 to 10
|
| 578 |
|
|
tstcfg_PktSize = $dist_uniform(tstcfg_Seed,0,4);
|
| 579 |
|
|
|
| 580 |
|
|
case(tstcfg_PktSize)
|
| 581 |
|
|
`tstcfg_SizeXShort : PktSize = $dist_uniform(tstcfg_Seed,64,128);
|
| 582 |
|
|
`tstcfg_SizeShort : PktSize = $dist_uniform(tstcfg_Seed,128,512);
|
| 583 |
|
|
`tstcfg_SizeMedium : PktSize = $dist_uniform(tstcfg_Seed,512,1024);
|
| 584 |
|
|
`tstcfg_SizeLarge : PktSize = $dist_uniform(tstcfg_Seed,1024,1518);
|
| 585 |
|
|
`tstcfg_SizeXLarge : PktSize = $dist_uniform(tstcfg_Seed,1518,9000);
|
| 586 |
|
|
endcase
|
| 587 |
|
|
|
| 588 |
|
|
s32_TxCarrierExtCycles[tstcfg_TxPktCnt+Idx]=(PktSize&32'h1)?1:0;
|
| 589 |
|
|
ErrorPos = $dist_uniform(tstcfg_Seed,1,(PktSize-ErrorCycle));
|
| 590 |
|
|
s32_TxCarrierErrCycles[tstcfg_TxPktCnt+Idx]=ErrorCycle;
|
| 591 |
|
|
for(Octet=0;Octet
|
| 592 |
|
|
begin
|
| 593 |
|
|
if(Octet<7)
|
| 594 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][Octet]=8'h55;
|
| 595 |
|
|
else if(Octet==7)
|
| 596 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][Octet]=8'hD5;
|
| 597 |
|
|
else
|
| 598 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][Octet]=$random;
|
| 599 |
|
|
end
|
| 600 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][8]=PktSize & 32'h00FF;
|
| 601 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][9]=((PktSize & 32'hFF00)>>8);
|
| 602 |
|
|
//Transmit:
|
| 603 |
|
|
$display("Not complete task");
|
| 604 |
|
|
|
| 605 |
|
|
$display("Sender : Sending Packet %d Size %d",tstcfg_TxPktCnt+Idx,PktSize);
|
| 606 |
|
|
end
|
| 607 |
|
|
tstcfg_TxPktCnt = tstcfg_TxPktCnt+PktNum;
|
| 608 |
|
|
|
| 609 |
|
|
end
|
| 610 |
|
|
endtask
|
| 611 |
|
|
|
| 612 |
|
|
task tsk_TransmitErrOutFrame;
|
| 613 |
|
|
integer PktSize;
|
| 614 |
|
|
integer PktNum;
|
| 615 |
|
|
integer PktIFG;
|
| 616 |
|
|
integer Idx;
|
| 617 |
|
|
integer Octet;
|
| 618 |
|
|
integer ErrorCycle;
|
| 619 |
|
|
integer ErrorPos;
|
| 620 |
|
|
integer ExtCycles;
|
| 621 |
|
|
begin
|
| 622 |
|
|
PktNum = $dist_uniform(tstcfg_Seed,1,10);//From 1 to 10
|
| 623 |
|
|
|
| 624 |
|
|
for(Idx=0;Idx
|
| 625 |
|
|
begin
|
| 626 |
|
|
ExtCycles = $dist_uniform(tstcfg_Seed,7,20);
|
| 627 |
|
|
ErrorCycle = $dist_uniform(tstcfg_Seed,1,3);//From 1 to 10
|
| 628 |
|
|
PktIFG = $dist_uniform(tstcfg_Seed,10,14);//From 2 to 10
|
| 629 |
|
|
tstcfg_PktSize = $dist_uniform(tstcfg_Seed,0,4);
|
| 630 |
|
|
case(tstcfg_PktSize)
|
| 631 |
|
|
`tstcfg_SizeXShort : PktSize = $dist_uniform(tstcfg_Seed,64,128);
|
| 632 |
|
|
`tstcfg_SizeShort : PktSize = $dist_uniform(tstcfg_Seed,128,512);
|
| 633 |
|
|
`tstcfg_SizeMedium : PktSize = $dist_uniform(tstcfg_Seed,512,1024);
|
| 634 |
|
|
`tstcfg_SizeLarge : PktSize = $dist_uniform(tstcfg_Seed,1024,1518);
|
| 635 |
|
|
`tstcfg_SizeXLarge : PktSize = $dist_uniform(tstcfg_Seed,1518,9000);
|
| 636 |
|
|
endcase
|
| 637 |
|
|
|
| 638 |
|
|
s32_TxCarrierExtCycles[tstcfg_TxPktCnt+Idx]=((PktSize+ExtCycles)&32'h1)?(ExtCycles+1):ExtCycles;
|
| 639 |
|
|
ErrorPos = $dist_uniform(tstcfg_Seed,3,(ExtCycles-ErrorCycle));
|
| 640 |
|
|
$display("----Ext = %d, Error = %d",ExtCycles,ErrorCycle);
|
| 641 |
|
|
s32_TxCarrierErrCycles[tstcfg_TxPktCnt+Idx]=ErrorCycle;
|
| 642 |
|
|
for(Octet=0;Octet
|
| 643 |
|
|
begin
|
| 644 |
|
|
if(Octet<7)
|
| 645 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][Octet]=8'h55;
|
| 646 |
|
|
else if(Octet==7)
|
| 647 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][Octet]=8'hD5;
|
| 648 |
|
|
else
|
| 649 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][Octet]=$random;
|
| 650 |
|
|
end
|
| 651 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][8]=PktSize & 32'h00FF;
|
| 652 |
|
|
r8_TxBuffer[tstcfg_TxPktCnt+Idx][9]=((PktSize & 32'hFF00)>>8);
|
| 653 |
|
|
//Transmit:
|
| 654 |
|
|
$display("Not complete task");
|
| 655 |
|
|
|
| 656 |
|
|
$display("Sender : Sending Packet %d Size %d",tstcfg_TxPktCnt+Idx,PktSize);
|
| 657 |
|
|
end
|
| 658 |
|
|
tstcfg_TxPktCnt = tstcfg_TxPktCnt+PktNum;
|
| 659 |
|
|
|
| 660 |
|
|
end
|
| 661 |
|
|
endtask
|
| 662 |
|
|
|
| 663 |
|
|
|
| 664 |
|
|
//Informatiion
|
| 665 |
|
|
always@(*)
|
| 666 |
|
|
begin
|
| 667 |
|
|
if(w_u0LinkUp==1'b1) $display("Link Acquired"); else $display("Link Dropped");
|
| 668 |
|
|
if(w_u0ANDone==1'b1) begin
|
| 669 |
|
|
$display("Auto-nego completes");
|
| 670 |
|
|
$display("Link Speed %d Mbps",(w2_u0Speed==2'b10)?1000:((w2_u0Speed==2'b01)?100:((w2_u0Speed==2'b00)?10:0)));
|
| 671 |
|
|
$display("Link Duplex %s ",w_u0Duplex?"Full":"Half");
|
| 672 |
|
|
end
|
| 673 |
|
|
end
|
| 674 |
|
|
|
| 675 |
|
|
reg [15:00] r16_LpAbility;
|
| 676 |
|
|
initial
|
| 677 |
|
|
begin
|
| 678 |
|
|
|
| 679 |
|
|
forever
|
| 680 |
|
|
begin
|
| 681 |
|
|
#1000;
|
| 682 |
|
|
u1WishboneMstr.tsk_Read(7'b00101_00,r16_LpAbility); //Enable SGMII Mode, Speed 1000Gb, Full Duplex
|
| 683 |
|
|
//$display("Partner Ability %x",r16_LpAbility);
|
| 684 |
|
|
end
|
| 685 |
|
|
end
|
| 686 |
|
|
|
| 687 |
|
|
endmodule
|
| 688 |
|
|
|
| 689 |
|
|
//TODO Test case Loopback
|
| 690 |
|
|
//TODO Test Auto Negotiation (Good)
|
| 691 |
|
|
//TODO Test Restart Auto Negotiation (Good)
|
| 692 |
|
|
//TODO Test case 1) Basic, Random size packets from 16 bytes to 10000 bytes
|
| 693 |
|
|
//TODO Test case 2) Carrier Extension, figure 35-6
|
| 694 |
|
|
//TODO Test case 3) Burst transmission, figure 35-7
|
| 695 |
|
|
//TODO Test case 4) Error Propagation with in aframe, figure 35-4
|
| 696 |
|
|
//TODO Test case 5) Error Propagation with carrier extension, figure 35-4
|
