OpenCores
URL https://opencores.org/ocsvn/sgmii/sgmii/trunk

Subversion Repositories sgmii

[/] [sgmii/] [trunk/] [sim/] [Veritil.v] - Blame information for rev 11

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 jefflieu
 
2
/*
3
Include this file after module
4
*/
5
integer ErrorCnt=0;
6
integer ErrorCode=0;
7
        initial begin
8
                ErrorCnt=0;
9
                ErrorCode=0;
10
        end
11 11 jefflieu
`define Info(Message) $display("I@(%d):%s",$time,Message);
12 4 jefflieu
`define CheckE(Signal,Value,SignalName) if(Signal!==Value) begin \
13
                                $display("E@(%d): expect %x, actual %x (%s,%s,%d)",$time,Value,Signal,SignalName,`__FILE__,`__LINE__); \
14
                                ErrorCnt=ErrorCnt+1;\
15
                                end
16
`define CheckF(Signal,Value,SignalName) if(Signal!==Value) begin \
17
                                $display("F@(%d): expect %x, actual %x (%s,%s,%d)",$time,Value,Signal,SignalName,`__FILE__,`__LINE__); \
18
                                $stop(1);\
19
                                end
20
`define CheckW(Signal,Value,SignalName) if(Signal!==Value) begin \
21
                                $display("W@(%d): expect %x, actual %x (%s,%s,%d)",$time,Value,Signal,SignalName,`__FILE__,`__LINE__); \
22
                                end
23
 
24
`define WaitTil(Signal,Value,Clk,Message)       while(Signal!==Value) begin @(posedge Clk);#0.001;end \
25
                                $display(Message);
26
`define WaitTilRise(Signal)     @(posedge Signal);#0.001;
27
`define WaitTilRall(Signal)     @(negedge Signal);#0.001;
28
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.