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[/] [sgmii/] [trunk/] [sim/] [mMACEmulator.sv] - Blame information for rev 5

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1 4 jefflieu 
/*
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Developed by Jeff Lieu (lieumychuong@gmail.com)
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File            :
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Description     :
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Remarks         :
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Revision        :
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        Date    Author  Description
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*/
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`timescale 1ns/10ps
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module mMACEmulator(
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        input i_RxClk,
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        input i_TxClk,
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        input [07:00] i8_RxD,
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        input i_RxDV,
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        input i_RxER,
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        output reg [07:00] o8_TxD,
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        output reg o_TxEN,
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        output reg o_TxER,
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        input i_Reset_L);
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        reg r_Active;
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        integer Octet;
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        integer ExtCycles;
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        integer ErrCycles;
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        integer RxPktCnt;
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        wire w_Active;
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        wire w_Sop;
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        wire w_Eop;
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        reg [07:00] ReceivedPkt[0:10000];
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        integer RxPtr;
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        reg ReceiveEnable;
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        assign w_Sop = ~r_Active & w_Active;
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        assign w_Eop = r_Active & (~w_Active);
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                initial
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                        begin
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                        RxPktCnt=0;
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                        o_TxEN=0;
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                        o_TxER=0;
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                        o8_TxD=0;
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                        ReceiveEnable <= 1'b0;
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                        end
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        assign w_Active=i_RxDV|i_RxER;
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        always@(posedge i_RxClk)
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                begin
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                        r_Active <= w_Active;
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                end
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        task automatic tsk_ReceivePkt;
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                output [07:00] ov_ReceivedPkt[0:10000];
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                output integer FrameSize;
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                output integer ExtCycles;
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                output integer ErrCycles;
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                integer Octet;
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        begin
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                ExtCycles = 0;
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                ErrCycles = 0;
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                for(Octet=0;Octet<10000;Octet=Octet+1)
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                        ov_ReceivedPkt[Octet]=0;
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                Octet=0;
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                while(w_Active!=1'b1||r_Active!=1'b0)
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                        @(posedge i_RxClk);
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                while(r_Active!=1'b1||w_Active!=1'b0)
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                begin
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                        if(i_RxDV==1'b1 && i_RxER==1'b0)
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                                begin
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                                if(r_Active==1'b0) $display("MAC: Start Receiving");
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                                ov_ReceivedPkt[Octet]=i8_RxD;
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                                Octet=Octet+1;
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                                //$write("%x ",i8_RxD);
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                                end
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                        else if(i_RxDV==1'b0 && i_RxER==1'b1) begin
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                                case(i8_RxD)
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                                8'h0F: begin
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                                                ExtCycles = ExtCycles+1;
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                                           end
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                                8'h1F: begin
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                                                $display("Error Propagation");
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                                                ExtCycles = ExtCycles+1;
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                                                ErrCycles = ErrCycles+1;
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                                                end
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                                default: $display("Unknown %x",i8_RxD);
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                                endcase
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                                end
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                        else if(i_RxDV==1'b1 && i_RxER==1'b1) begin
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                                        ErrCycles = ErrCycles+1;
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                                        //ov_ReceivedPkt[Octet]=i8_RxD;
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                                        //Octet = Octet+1;
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                        end
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                        @(posedge i_RxClk);
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                end
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                FrameSize=Octet;
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                $display("MAC: Packet Received with %d bytes",FrameSize);
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        end
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        endtask
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        task automatic tsk_TransmitPkt;
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                ref reg [7:0] iv_TransmitPkt[0:10000];
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                input integer PktSize;
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                input integer PktIFG;
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                integer Octet;
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        begin
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                for(Octet=0;Octet
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                                begin
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                                @(posedge i_TxClk);#1;
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                                o_TxEN = 1'b1;
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                                o_TxER = 1'b0;
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                                o8_TxD = iv_TransmitPkt[Octet];
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                                end
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                                @(posedge i_TxClk);#1;
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                                o_TxEN = 1'b0;
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                        //Interframe Gap
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                        for(Octet=0;Octet
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                                begin @(posedge i_TxClk);#1; end
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        end
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        endtask
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endmodule

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