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jefflieu |
/*
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Developed By Subtleware Corporation Pte Ltd 2011
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File :
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Description :
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Remarks : No Support for Next Page
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Revision :
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Date Author Description
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02/09/12 Jefflieu
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*/
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`include "SGMIIDefs.v"
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`timescale 1ns/100ps
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`define c10ms (10_000_000/`cSystemClkPeriod)
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`define c1p6ms (00_001_000/`cSystemClkPeriod)
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module mANCtrl(
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input i_Clk,
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input i_ARst_L,
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input i_Cke,
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input i_RestartAN,
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input i_SyncStatus,
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input i_ANEnable,
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input [20:00] i21_LinkTimer,
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output [15:00] o16_LpAdvAbility,
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input [16:01] i16_LcAdvAbility,
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input [15:00] i16_RxConfigReg,
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input i_RUDIConfig,
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input i_RUDIIdle,
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input i_RUDIInvalid,
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output o_ANComplete,
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output reg [02:00] o3_Xmit,
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output reg [15:00] o16_TxConfigReg);
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localparam stAN_ENABLE = 8'h01,
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stAN_RESTART = 8'h02,
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stABILITY_DTECT = 8'h04,
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stACK_DTECT = 8'h08,
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stCMPLT_ACK = 8'h10,
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stIDLE_DTECT = 8'h20,
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stLINK_OK = 8'h40,
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stAN_DIS_LINKOK = 8'h80;
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reg [20:00] r21_LinkTimer;
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reg [02:00] r2_RxCfgRegMchCntr;
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wire w_AbiMatch;
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reg r_ConsistencyMatch;
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wire w_AckMatch;
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reg [07:00] r8_State;
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reg r_ANEable;
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wire w_LinkTimerDone;
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reg [16:01] r16_LpAdvAbility; //Link partner Advertised Ability, updated every time RUDIConfig is valid
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reg r_NxtPage;
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reg r_NxtPageLoaded;
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reg r_ToggleTx;
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reg r_ToggleRx;
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reg [01:00] r2_AbilityMatchCnt;
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reg [01:00] r2_ConsistMatchCnt;
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reg [01:00] r2_AcknowlMatchCnt;
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reg [15:00] r16_AbilityReg; //Captured of Partner Ability before going to Acknowledge Detect
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reg [01:00] r2_IdleMatchCnt;
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wire w_IdleMatch;
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assign w_LinkTimerDone = (r21_LinkTimer==i21_LinkTimer)?1'b1:1'b0;
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assign w_AbiMatch = (r2_AbilityMatchCnt==2'b11)?1'b1:1'b0;
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assign w_AckMatch = (r2_AcknowlMatchCnt==2'b11)?1'b1:1'b0;
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assign w_IdleMatch = (r2_IdleMatchCnt==2'b11)?1'b1:1'b0;
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assign o16_LpAdvAbility = r16_LpAdvAbility;
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assign o_ANComplete = (r8_State==stLINK_OK)?1'b1:1'b0;
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always@(posedge i_Clk or negedge i_ARst_L)
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if(i_ARst_L==1'b0) begin
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r8_State <= stAN_ENABLE;
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end else begin
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r_ANEable <= i_ANEnable;
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if((~i_Cke) || i_RestartAN || (~i_SyncStatus) || i_RUDIInvalid || (r_ANEable^i_ANEnable))
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r8_State <= stAN_ENABLE;
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else
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case(r8_State)
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stAN_ENABLE : if(i_ANEnable) r8_State <= stAN_RESTART; else r8_State <= stAN_DIS_LINKOK;
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stAN_RESTART : if(w_LinkTimerDone) r8_State <= stABILITY_DTECT;
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stABILITY_DTECT : if(w_AbiMatch && r16_LpAdvAbility!=16'h0000) r8_State <= stACK_DTECT;
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stACK_DTECT : if((w_AckMatch && (~r_ConsistencyMatch))||(w_AbiMatch && i16_RxConfigReg==16'h0000 && i_RUDIConfig))
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r8_State <= stAN_ENABLE;
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else if(w_AckMatch && r_ConsistencyMatch)
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r8_State <= stCMPLT_ACK;
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stCMPLT_ACK : if(w_AbiMatch && r16_LpAdvAbility==16'h0000) r8_State <= stAN_ENABLE;
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else if(w_LinkTimerDone && (~w_AbiMatch||(r16_LpAdvAbility!=16'h0000)))
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r8_State <= stIDLE_DTECT;
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stIDLE_DTECT : if(w_IdleMatch && w_LinkTimerDone) r8_State <= stLINK_OK; else
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if(w_IdleMatch && r16_LpAdvAbility==16'h0000) r8_State <= stAN_ENABLE;
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stLINK_OK : if(w_AbiMatch) r8_State <= stAN_ENABLE;
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stAN_DIS_LINKOK : r8_State <= stAN_DIS_LINKOK;
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endcase
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end
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always@(posedge i_Clk or negedge i_ARst_L)
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if(!i_ARst_L) begin
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r16_LpAdvAbility <= 16'h0000;
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o3_Xmit <= `cXmitIDLE;
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r21_LinkTimer <= 21'h0;
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o16_TxConfigReg <= 16'h0;
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r2_IdleMatchCnt <= 2'b00;
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r16_AbilityReg <= 16'h0;
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end else begin
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//Xmit
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case(r8_State)
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stAN_ENABLE : if(i_ANEnable) o3_Xmit <= `cXmitCONFIG; else o3_Xmit <= `cXmitIDLE;
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stIDLE_DTECT: o3_Xmit <= `cXmitIDLE;
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stLINK_OK : o3_Xmit <= `cXmitDATA;
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stAN_DIS_LINKOK: o3_Xmit <= `cXmitDATA;
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endcase
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case(r8_State)
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stAN_ENABLE: r21_LinkTimer <= 21'h0;
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stAN_RESTART: if(w_LinkTimerDone==1'b0) r21_LinkTimer <= r21_LinkTimer+21'h1;
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stACK_DTECT : r21_LinkTimer <= 21'h0;
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stCMPLT_ACK : if(w_LinkTimerDone && (~w_AbiMatch||(r16_LpAdvAbility!=16'h0000))) r21_LinkTimer <= 21'h0; else
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if(w_LinkTimerDone==1'b0) r21_LinkTimer <= r21_LinkTimer+21'h1;
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stIDLE_DTECT: if(w_LinkTimerDone==1'b0) r21_LinkTimer <= r21_LinkTimer+21'h1;
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stLINK_OK : r21_LinkTimer <= 21'h0;
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endcase
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case(r8_State)
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stAN_ENABLE: if(i_ANEnable) o16_TxConfigReg <= 16'h0000;
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stAN_RESTART: if(w_LinkTimerDone) begin
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o16_TxConfigReg[15] <= i16_LcAdvAbility[16];
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o16_TxConfigReg[14] <= 1'b0;
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o16_TxConfigReg[13:0] <= i16_LcAdvAbility[14:1];
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end
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stACK_DTECT : o16_TxConfigReg[14] <= 1'b1;
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endcase
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if(r8_State==stABILITY_DTECT) r_ToggleTx <= i16_LcAdvAbility[12];
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else if(r8_State==stCMPLT_ACK) r_ToggleTx <= ~r_ToggleTx;
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if(r8_State==stCMPLT_ACK) r_ToggleRx<=i16_RxConfigReg[11];
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//Sync Reset
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if(r8_State==stAN_RESTART)
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begin
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r2_AbilityMatchCnt <= 2'b00;
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r16_AbilityReg <= 16'h0;
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r16_LpAdvAbility <= 16'h0;
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r2_AcknowlMatchCnt <= 2'b00;
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r_ConsistencyMatch <= 1'b0;
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r2_IdleMatchCnt <= 2'b00;
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end else
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begin
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//w_AbiMatch
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if(i_RUDIIdle)
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r2_AbilityMatchCnt <= 2'b00;
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else if(i_RUDIConfig) begin
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if(i16_RxConfigReg[13:00] == r16_LpAdvAbility[14:01] && i16_RxConfigReg[15]==r16_LpAdvAbility[16])
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begin
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if(r2_AbilityMatchCnt!=2'b11) r2_AbilityMatchCnt<=r2_AbilityMatchCnt+1;
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end
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else
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r2_AbilityMatchCnt <= 2'b01;
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end
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if(r8_State==stABILITY_DTECT && w_AbiMatch && r16_LpAdvAbility!=16'h00) r16_AbilityReg <= r16_LpAdvAbility;
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//Ack Match
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if(i_RUDIIdle)
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r2_AcknowlMatchCnt <= 2'b00;
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else if(i_RUDIConfig) begin
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if(i16_RxConfigReg[15:00] == r16_LpAdvAbility[16:01] && (i16_RxConfigReg[14]==1'b1))
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begin
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if(r2_AcknowlMatchCnt!=2'b11) r2_AcknowlMatchCnt<=r2_AcknowlMatchCnt+1;
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//Consistency Match
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//When the flag acknowledge match is about to be set
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//If the bits are same as r16_AbilityReg , consistent
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//Else Not consistent;
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//Consistency match is set at the same time as Acknowledge match
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if(r2_AcknowlMatchCnt==2'b10 && (i16_RxConfigReg[13:00] == r16_AbilityReg[13:00] && i16_RxConfigReg[15]==r16_AbilityReg[15]))
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r_ConsistencyMatch <= 1'b1; else r_ConsistencyMatch<=1'b0;
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end
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else
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r2_AcknowlMatchCnt <= 2'b01;
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end
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if(i_RUDIConfig)
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r16_LpAdvAbility <= i16_RxConfigReg;
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if(i_RUDIIdle) r2_IdleMatchCnt <= r2_IdleMatchCnt+2'b01;
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else if(i_RUDIConfig|i_RUDIInvalid) r2_IdleMatchCnt<=2'b00;
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end
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end
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//synopsys synthesis_off
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reg [239:0] r240_ANStateName;
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always@(*)
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case(r8_State)
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stAN_ENABLE :r240_ANStateName<="stAN_ENABLE ";
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stAN_RESTART :r240_ANStateName<="stAN_RESTART ";
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stABILITY_DTECT :r240_ANStateName<="stABILITY_DTECT ";
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stACK_DTECT :r240_ANStateName<="stACK_DTECT ";
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stCMPLT_ACK :r240_ANStateName<="stCMPLT_ACK ";
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stIDLE_DTECT :r240_ANStateName<="stIDLE_DTECT ";
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stLINK_OK :r240_ANStateName<="stLINK_OK ";
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stAN_DIS_LINKOK :r240_ANStateName<="stAN_DIS_LINKOK ";
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endcase
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//synopsys synthesis_on
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endmodule
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