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jefflieu |
`define NO_PLI
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`timescale 1ns / 1ps
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module tb;
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initial begin
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$display("***********************************************************");
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$display("title: tb.demo_dec");
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$display("desc: demonstration testbench");
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$display(" (c) Altera Inc. ALL RIGHTS RESERVED ");
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$display(" www.altera.com ");
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$display("***********************************************************");
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$display("PURPOSE: Demonstrate basic function and provide hookup example.");
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$display("PURPOSE: Note: no error checking is performed.");
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$display("METHOD: A generator emits several random data and control values.");
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$display("***********************************************************");
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end
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/**********************************************************************/
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// DEFINES AND INCLUDES
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/**********************************************************************/
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`define TBID "tb.demo_enc"
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reg clk;
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reg reset_n;
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reg dec_idle_del;
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reg dec_enable;
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reg [9:0] dec_datain;
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reg dec_rdin;
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reg dec_rdforce;
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wire dec_kerr;
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wire [7:0] dec_dataout;
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wire dec_valid;
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wire dec_rdout;
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wire dec_rdcascade;
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wire dec_kout;
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wire dec_rderr;
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mAlt8b10bdec mAlt8b10bdec(
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.clk (clk) // input
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,.reset_n (reset_n) // input
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,.idle_del (dec_idle_del) // input
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,.ena (dec_enable) // input
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,.datain (dec_datain) // input [9:0]
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,.rdforce (dec_rdforce) // input
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,.rdin (dec_rdin) // input
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,.valid (dec_valid) // output
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,.dataout (dec_dataout) // output [7:0]
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,.kout (dec_kout) // output
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,.kerr (dec_kerr) // output
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//,.disparity (dec_disparity) // output [1:0]
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,.rdout (dec_rdout) // output
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,.rderr (dec_rderr) // output
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);
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initial begin
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dec_enable = 1;
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dec_rdforce = 0;
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dec_rdin = 0;
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dec_idle_del = 0;
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@(posedge clk) dec_datain <= 10'h0b9;
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@(posedge clk) dec_datain <= 10'h0b9;
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@(posedge clk) dec_datain <= 10'h17c;
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@(posedge clk) dec_datain <= 10'h283;
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@(posedge clk) dec_datain <= 10'h17c;
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@(posedge clk) dec_datain <= 10'h283;
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@(posedge clk) dec_datain <= 10'h17c;
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@(posedge clk) dec_datain <= 10'h283;
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@(posedge clk) dec_datain <= 10'h17c;
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@(posedge clk) dec_datain <= 10'h283;
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@(posedge clk) dec_datain <= 10'h17c;
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@(posedge clk) dec_datain <= 10'h283;
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@(posedge clk) dec_datain <= 10'h17c;
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@(posedge clk) dec_datain <= 10'h283;
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@(posedge clk) dec_datain <= 10'h17c;
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@(posedge clk) dec_datain <= 10'h283;
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@(posedge clk) dec_datain <= 10'h17c;
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@(posedge clk) dec_datain <= 10'h283;
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@(posedge clk) dec_datain <= 10'h17c;
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@(posedge clk) dec_datain <= 10'h283;
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@(posedge clk) dec_datain <= 10'h17c;
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@(posedge clk) dec_datain <= 10'h283;
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@(posedge clk) dec_datain <= 10'h17c;
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@(posedge clk) dec_datain <= 10'h358;
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@(posedge clk) dec_datain <= 10'h2d2;
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@(posedge clk) dec_datain <= 10'h172;
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@(posedge clk) dec_datain <= 10'h171;
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@(posedge clk) dec_datain <= 10'h192;
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@(posedge clk) dec_datain <= 10'h0ea;
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@(posedge clk) dec_datain <= 10'h335;
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@(posedge clk) dec_datain <= 10'h113;
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@(posedge clk) dec_datain <= 10'h36a;
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@(posedge clk) dec_datain <= 10'h30e;
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@(posedge clk) dec_datain <= 10'h34c;
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@(posedge clk) dec_datain <= 10'h2c3;
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@(posedge clk) dec_datain <= 10'h21c;
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@(posedge clk) dec_datain <= 10'h365;
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@(posedge clk) dec_datain <= 10'h26c;
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@(posedge clk) dec_datain <= 10'h2e4;
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@(posedge clk) dec_datain <= 10'h1d2;
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@(posedge clk) dec_datain <= 10'h1e1;
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@(posedge clk) dec_datain <= 10'h08b;
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@(posedge clk) dec_datain <= 10'h18d;
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@(posedge clk) dec_datain <= 10'h267;
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@(posedge clk) dec_datain <= 10'h313;
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@(posedge clk) dec_datain <= 10'h0a9;
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@(posedge clk) dec_datain <= 10'h1b2;
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@(posedge clk) dec_datain <= 10'h2d3;
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@(posedge clk) dec_datain <= 10'h272;
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@(posedge clk) dec_datain <= 10'h283;
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@(posedge clk) dec_datain <= 10'h1e9;
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@(posedge clk) dec_datain <= 10'h22a;
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@(posedge clk) dec_datain <= 10'h295;
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@(posedge clk) dec_datain <= 10'h19e;
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@(posedge clk) dec_datain <= 10'h1a4;
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@(posedge clk) dec_datain <= 10'h057;
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@(posedge clk) dec_datain <= 10'h26b;
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@(posedge clk) dec_datain <= 10'h0b1;
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@(posedge clk) dec_datain <= 10'h0c7;
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@(posedge clk) dec_datain <= 10'h2d6;
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@(posedge clk) dec_datain <= 10'h2b2;
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@(posedge clk) dec_datain <= 10'h2b8;
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@(posedge clk) dec_datain <= 10'h292;
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@(posedge clk) dec_datain <= 10'h1bc;
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@(posedge clk) dec_datain <= 10'h21a;
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@(posedge clk) dec_datain <= 10'h1dc;
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@(posedge clk) dec_datain <= 10'h22c;
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@(posedge clk) dec_datain <= 10'h097;
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@(posedge clk) dec_datain <= 10'h1e3;
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@(posedge clk) dec_datain <= 10'h3a1;
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@(posedge clk) dec_datain <= 10'h3a2;
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@(posedge clk) dec_datain <= 10'h2a2;
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@(posedge clk) dec_datain <= 10'h1b2;
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@(posedge clk) dec_datain <= 10'h0e6;
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@(posedge clk) dec_datain <= 10'h22e;
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@(posedge clk) dec_datain <= 10'h296;
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@(posedge clk) dec_datain <= 10'h296;
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@(posedge clk) dec_datain <= 10'h07c;
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@(posedge clk) dec_datain <= 10'h24b;
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@(posedge clk) dec_datain <= 10'h139;
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@(posedge clk) dec_datain <= 10'h33c;
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@(posedge clk) dec_datain <= 10'h31c;
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@(posedge clk) dec_datain <= 10'h178;
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@(posedge clk) dec_datain <= 10'h04d;
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@(posedge clk) dec_datain <= 10'h1a9;
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@(posedge clk) dec_datain <= 10'h25a;
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@(posedge clk) dec_datain <= 10'h23c;
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@(posedge clk) dec_datain <= 10'h179;
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@(posedge clk) dec_datain <= 10'h0b2;
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@(posedge clk) dec_datain <= 10'h1cb;
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@(posedge clk) dec_datain <= 10'h131;
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@(posedge clk) dec_datain <= 10'h2cd;
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@(posedge clk) dec_datain <= 10'h0ac;
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@(posedge clk) dec_datain <= 10'h359;
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@(posedge clk) dec_datain <= 10'h349;
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@(posedge clk) dec_datain <= 10'h171;
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@(posedge clk) dec_datain <= 10'h32c;
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@(posedge clk) dec_datain <= 10'h143;
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@(posedge clk) dec_datain <= 10'h0e5;
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@(posedge clk) dec_datain <= 10'h139;
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@(posedge clk) dec_datain <= 10'h2cb;
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@(posedge clk) dec_datain <= 10'h249;
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@(posedge clk) dec_datain <= 10'h17c;
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@(posedge clk) dec_datain <= 10'h283;
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@(posedge clk) dec_datain <= 10'h17c;
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@(posedge clk) dec_datain <= 10'h283;
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@(posedge clk) dec_datain <= 10'h2d6;
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@(posedge clk) dec_datain <= 10'h095;
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@(posedge clk) dec_datain <= 10'h0dc;
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@(posedge clk) dec_datain <= 10'h05b;
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@(posedge clk) dec_datain <= 10'h1ad;
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@(posedge clk) dec_datain <= 10'h14e;
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@(posedge clk) dec_datain <= 10'h11c;
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@(posedge clk) dec_datain <= 10'h353;
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@(posedge clk) dec_datain <= 10'h346;
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@(posedge clk) dec_datain <= 10'h183;
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@(posedge clk) dec_datain <= 10'h297;
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@(posedge clk) dec_datain <= 10'h285;
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@(posedge clk) dec_datain <= 10'h0b5;
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@(posedge clk) dec_datain <= 10'h157;
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@(posedge clk) dec_datain <= 10'h313;
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@(posedge clk) dec_datain <= 10'h191;
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@(posedge clk) dec_datain <= 10'h14d;
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@(posedge clk) dec_datain <= 10'h1ea;
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@(posedge clk) dec_datain <= 10'h12c;
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@(posedge clk) dec_datain <= 10'h29a;
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@(posedge clk) dec_datain <= 10'h0f1;
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@(posedge clk) dec_datain <= 10'h0cd;
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@(posedge clk) dec_datain <= 10'h0bc;
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@(posedge clk) dec_datain <= 10'h2ad;
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@(posedge clk) dec_datain <= 10'h278;
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@(posedge clk) dec_datain <= 10'h2a8;
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@(posedge clk) dec_datain <= 10'h17c;
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@(posedge clk) dec_datain <= 10'h283;
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@(posedge clk) dec_datain <= 10'h17c;
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@(posedge clk) dec_datain <= 10'h283;
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@(posedge clk) dec_datain <= 10'h28d;
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@(posedge clk) dec_datain <= 10'h2a6;
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@(posedge clk) dec_datain <= 10'h266;
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@(posedge clk) dec_datain <= 10'h14e;
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@(posedge clk) dec_datain <= 10'h2dc;
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@(posedge clk) dec_datain <= 10'h093;
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@(posedge clk) dec_datain <= 10'h0b9;
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@(posedge clk) dec_datain <= 10'h27c;
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@(posedge clk) dec_datain <= 10'h2a8;
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@(posedge clk) dec_datain <= 10'h2ba;
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$display("$$$ Exit status for testbench tb.demo_dec : TESTBENCH_PASSED ");
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$finish;
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end
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// clock generator (100 MHz)
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initial begin
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clk <= 0;
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forever begin
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#10;
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clk = !clk;
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end
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end
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// reset task
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initial begin
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reset_n <= 0;
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repeat (10) @(posedge clk);
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reset_n <= 1;
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end
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// logging task
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always @(posedge clk) begin
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$display("%0t dec_enable = %b dec_datain = %x, dec_kout = %b, dec_dataout = %x",
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$time, dec_enable, dec_datain, dec_kout, dec_dataout);
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end
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endmodule
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