Subversion Repositories sgmii

//IP Functional Simulation Model

//VERSION_BEGIN 12.0SP2 cbx_mgl 2012:08:02:15:20:46:SJ cbx_simgen 2012:08:02:15:18:54:SJ  VERSION_END

// synthesis VERILOG_INPUT_VERSION VERILOG_2001

// altera message_off 10463

// Copyright (C) 1991-2012 Altera Corporation

// Your use of Altera Corporation's design tools, logic functions

// and other software and tools, and its AMPP partner logic

// functions, and any output files from any of the foregoing

// (including device programming or simulation files), and any

// associated documentation or information are expressly subject

// to the terms and conditions of the Altera Program License

// Subscription Agreement, Altera MegaCore Function License

// Agreement, or other applicable license agreement, including,

// without limitation, that your use is for the sole purpose of

// programming logic devices manufactured by Altera and sold by

// Altera or its authorized distributors.  Please refer to the

// applicable agreement for further details.

// You may only use these simulation model output files for simulation

// purposes and expressly not for synthesis or any other purposes (in which

// event Altera disclaims all warranties of any kind).

//synopsys translate_off

//synthesis_resources = lut 95 mux21 33 oper_decoder 3 oper_mux 10

`timescale 1 ps / 1 ps

module  mAlt8b10benc

        (

        clk,

        datain,

        dataout,

        ena,

        idle_ins,

        kerr,

        kin,

        rdcascade,

        rdforce,

        rdin,

        rdout,

        reset_n,

        valid) /* synthesis synthesis_clearbox=1 */;

        input   clk;

        input   [7:0]  datain;

        output   [9:0]  dataout;

        input   ena;

        input   idle_ins;

        output   kerr;

        input   kin;

        output   rdcascade;

        input   rdforce;

        input   rdin;

        output   rdout;

        input   reset_n;

        output   valid;

        reg     nii0i43;

        reg     nii0i44;

        reg     nii0l41;

        reg     nii0l42;

        reg     nii0O39;

        reg     nii0O40;

        reg     niiii37;

        reg     niiii38;

        reg     niiiO35;

        reg     niiiO36;

        reg     niill33;

        reg     niill34;

        reg     niiOi31;

        reg     niiOi32;

        reg     niiOO29;

        reg     niiOO30;

        reg     nil0l25;

        reg     nil0l26;

        reg     nil0O23;

        reg     nil0O24;

        reg     nil1l27;

        reg     nil1l28;

        reg     nilii21;

        reg     nilii22;

        reg     nilil19;

        reg     nilil20;

        reg     niliO17;

        reg     niliO18;

        reg     nilli15;

        reg     nilli16;

        reg     nilll13;

        reg     nilll14;

        reg     nillO11;

        reg     nillO12;

        reg     nilOl10;

        reg     nilOl9;

        reg     nilOO7;

        reg     nilOO8;

        reg     niO0i3;

        reg     niO0i4;

        reg     niO0l1;

        reg     niO0l2;

        reg     niO1i5;

        reg     niO1i6;

        reg     nll0l;

        reg     niOiO;

        reg     niOli;

        reg     niOll;

        reg     niOlO;

        reg     niOOi;

        reg     niOOl;

        reg     niOOO;

        reg     nl0Oi;

        reg     nl0Ol;

        reg     nl0OO;

        reg     nl10i;

        reg     nl10l;

        reg     nl10O;

        reg     nl11i;

        reg     nl11l;

        reg     nl11O;

        reg     nl1ii;

        reg     nl1il;

        reg     nl1li;

        reg     nli0i;

        reg     nli0l;

        reg     nli0O;

        reg     nli1i;

        reg     nli1l;

        reg     nli1O;

        reg     nliii;

        reg     nliil;

        reg     nliiO;

        reg     nlili;

        reg     nlill;

        reg     nlilO;

        reg     nliOi;

        reg     nliOl;

        reg     nliOO;

        reg     nll0O;

        reg     nll1i;

        reg     nll1l;

        reg     nll1O;

        reg     nllii;

        reg     nllil;

        reg     nlliO;

        reg     nllli;

        reg     nllll;

        reg     nlllO;

        reg     nllOi;

        reg     nllOl;

        reg     nllOO;

        reg     nlO0i;

        reg     nlO1i;

        reg     nlO1l;

        reg     nlO1O_clk_prev;

        wire    wire_nlO1O_CLRN;

        wire    wire_nlO1O_PRN;

        wire    wire_n00i_dataout;

        wire    wire_n00l_dataout;

        wire    wire_n00O_dataout;

        wire    wire_n01i_dataout;

        wire    wire_n01l_dataout;

        wire    wire_n01O_dataout;

        wire    wire_n0ii_dataout;

        wire    wire_n0il_dataout;

        wire    wire_n0iO_dataout;

        wire    wire_n0li_dataout;

        wire    wire_n0ll_dataout;

        wire    wire_n1Oi_dataout;

        wire    wire_n1Ol_dataout;

        wire    wire_n1OO_dataout;

        wire    wire_niil_dataout;

        wire    wire_niiO_dataout;

        wire    wire_nili_dataout;

        wire    wire_nill_dataout;

        wire    wire_nilO_dataout;

        wire    wire_niOi_dataout;

        wire    wire_niOl_dataout;

        wire    wire_niOO_dataout;

        wire    wire_nl1i_dataout;

        wire    wire_nlO0O_dataout;

        wire    wire_nlOii_dataout;

        wire    wire_nlOil_dataout;

        wire    wire_nlOiO_dataout;

        wire    wire_nlOli_dataout;

        wire    wire_nlOll_dataout;

        wire    wire_nlOlO_dataout;

        wire    wire_nlOOi_dataout;

        wire    wire_nlOOl_dataout;

        wire    wire_nlOOO_dataout;

        wire  [255:0]   wire_ni0l_o;

        wire  [31:0]   wire_nl0ii_o;

        wire  [255:0]   wire_nl0lO_o;

        wire  wire_n10i_o;

        wire  wire_n10l_o;

        wire  wire_n10O_o;

        wire  wire_n11i_o;

        wire  wire_n11l_o;

        wire  wire_n11O_o;

        wire  wire_n1ii_o;

        wire  wire_n1il_o;

        wire  wire_n1iO_o;

        wire  wire_n1li_o;

        wire  ni00i;

        wire  ni00l;

        wire  ni00O;

        wire  ni01O;

        wire  ni0ii;

        wire  ni0il;

        wire  ni0iO;

        wire  ni0li;

        wire  ni0ll;

        wire  ni0lO;

        wire  ni0Oi;

        wire  ni0Ol;

        wire  ni0OO;

        wire  nii1i;

        wire  nii1l;

        wire  nii1O;

        wire  nil0i;

        wire  niO1l;

        wire  niO1O;

        wire  niOil;

        wire  w_nl00i761w;

        wire  w_nl00i826w;

        wire  w_nl00l586w;

        wire  w_nl00l670w;

        wire  w_nl01i1201w;

        wire  w_nl01i1253w;

        wire  w_nl01l1082w;

        wire  w_nl01l1134w;

        wire  w_nl01O921w;

        wire  w_nl01O983w;

        wire  w_nl0il359w;

        wire  w_nl0il462w;

        initial

                nii0i43 = 0;

        always @ ( posedge clk)

                  nii0i43 <= nii0i44;

        event nii0i43_event;

        initial

                #1 ->nii0i43_event;

        always @(nii0i43_event)

                nii0i43 <= {1{1'b1}};

        initial

                nii0i44 = 0;

        always @ ( posedge clk)

                  nii0i44 <= nii0i43;

        initial

                nii0l41 = 0;

        always @ ( posedge clk)

                  nii0l41 <= nii0l42;

        event nii0l41_event;

        initial

                #1 ->nii0l41_event;

        always @(nii0l41_event)

                nii0l41 <= {1{1'b1}};

        initial

                nii0l42 = 0;

        always @ ( posedge clk)

                  nii0l42 <= nii0l41;

        initial

                nii0O39 = 0;

        always @ ( posedge clk)

                  nii0O39 <= nii0O40;

        event nii0O39_event;

        initial

                #1 ->nii0O39_event;

        always @(nii0O39_event)

                nii0O39 <= {1{1'b1}};

        initial

                nii0O40 = 0;

        always @ ( posedge clk)

                  nii0O40 <= nii0O39;

        initial

                niiii37 = 0;

        always @ ( posedge clk)

                  niiii37 <= niiii38;

        event niiii37_event;

        initial

                #1 ->niiii37_event;

        always @(niiii37_event)

                niiii37 <= {1{1'b1}};

        initial

                niiii38 = 0;

        always @ ( posedge clk)

                  niiii38 <= niiii37;

        initial

                niiiO35 = 0;

        always @ ( posedge clk)

                  niiiO35 <= niiiO36;

        event niiiO35_event;

        initial

                #1 ->niiiO35_event;

        always @(niiiO35_event)

                niiiO35 <= {1{1'b1}};

        initial

                niiiO36 = 0;

        always @ ( posedge clk)

                  niiiO36 <= niiiO35;

        initial

                niill33 = 0;

        always @ ( posedge clk)

                  niill33 <= niill34;

        event niill33_event;

        initial

                #1 ->niill33_event;

        always @(niill33_event)

                niill33 <= {1{1'b1}};

        initial

                niill34 = 0;

        always @ ( posedge clk)

                  niill34 <= niill33;

        initial

                niiOi31 = 0;

        always @ ( posedge clk)

                  niiOi31 <= niiOi32;

        event niiOi31_event;

        initial

                #1 ->niiOi31_event;

        always @(niiOi31_event)

                niiOi31 <= {1{1'b1}};

        initial

                niiOi32 = 0;

        always @ ( posedge clk)

                  niiOi32 <= niiOi31;

        initial

                niiOO29 = 0;

        always @ ( posedge clk)

                  niiOO29 <= niiOO30;

        event niiOO29_event;

        initial

                #1 ->niiOO29_event;

        always @(niiOO29_event)

                niiOO29 <= {1{1'b1}};

        initial

                niiOO30 = 0;

        always @ ( posedge clk)

                  niiOO30 <= niiOO29;

        initial

                nil0l25 = 0;

        always @ ( posedge clk)

                  nil0l25 <= nil0l26;

        event nil0l25_event;

        initial

                #1 ->nil0l25_event;

        always @(nil0l25_event)

                nil0l25 <= {1{1'b1}};

        initial

                nil0l26 = 0;

        always @ ( posedge clk)

                  nil0l26 <= nil0l25;

        initial

                nil0O23 = 0;

        always @ ( posedge clk)

                  nil0O23 <= nil0O24;

        event nil0O23_event;

        initial

                #1 ->nil0O23_event;

        always @(nil0O23_event)

                nil0O23 <= {1{1'b1}};

        initial

                nil0O24 = 0;

        always @ ( posedge clk)

                  nil0O24 <= nil0O23;

        initial

                nil1l27 = 0;

        always @ ( posedge clk)

                  nil1l27 <= nil1l28;

        event nil1l27_event;

        initial

                #1 ->nil1l27_event;

        always @(nil1l27_event)

                nil1l27 <= {1{1'b1}};

        initial

                nil1l28 = 0;

        always @ ( posedge clk)

                  nil1l28 <= nil1l27;

        initial

                nilii21 = 0;

        always @ ( posedge clk)

                  nilii21 <= nilii22;

        event nilii21_event;

        initial

                #1 ->nilii21_event;

        always @(nilii21_event)

                nilii21 <= {1{1'b1}};

        initial

                nilii22 = 0;

        always @ ( posedge clk)

                  nilii22 <= nilii21;

        initial

                nilil19 = 0;

        always @ ( posedge clk)

                  nilil19 <= nilil20;

        event nilil19_event;

        initial

                #1 ->nilil19_event;

        always @(nilil19_event)

                nilil19 <= {1{1'b1}};

        initial

                nilil20 = 0;

        always @ ( posedge clk)

                  nilil20 <= nilil19;

        initial

                niliO17 = 0;

        always @ ( posedge clk)

                  niliO17 <= niliO18;

        event niliO17_event;

        initial

                #1 ->niliO17_event;

        always @(niliO17_event)

                niliO17 <= {1{1'b1}};

        initial

                niliO18 = 0;

        always @ ( posedge clk)

                  niliO18 <= niliO17;

        initial

                nilli15 = 0;

        always @ ( posedge clk)

                  nilli15 <= nilli16;

        event nilli15_event;

        initial

                #1 ->nilli15_event;

        always @(nilli15_event)

                nilli15 <= {1{1'b1}};

        initial

                nilli16 = 0;

        always @ ( posedge clk)

                  nilli16 <= nilli15;

        initial

                nilll13 = 0;

        always @ ( posedge clk)

                  nilll13 <= nilll14;

        event nilll13_event;

        initial

                #1 ->nilll13_event;

        always @(nilll13_event)

                nilll13 <= {1{1'b1}};

        initial

                nilll14 = 0;

        always @ ( posedge clk)

                  nilll14 <= nilll13;

        initial

                nillO11 = 0;

        always @ ( posedge clk)

                  nillO11 <= nillO12;

        event nillO11_event;

        initial

                #1 ->nillO11_event;

        always @(nillO11_event)

                nillO11 <= {1{1'b1}};

        initial

                nillO12 = 0;

        always @ ( posedge clk)

                  nillO12 <= nillO11;

        initial

                nilOl10 = 0;

        always @ ( posedge clk)

                  nilOl10 <= nilOl9;

        initial

                nilOl9 = 0;

        always @ ( posedge clk)

                  nilOl9 <= nilOl10;

        event nilOl9_event;

        initial

                #1 ->nilOl9_event;

        always @(nilOl9_event)

                nilOl9 <= {1{1'b1}};

        initial

                nilOO7 = 0;

        always @ ( posedge clk)

                  nilOO7 <= nilOO8;

        event nilOO7_event;

        initial

                #1 ->nilOO7_event;

        always @(nilOO7_event)

                nilOO7 <= {1{1'b1}};

        initial

                nilOO8 = 0;

        always @ ( posedge clk)

                  nilOO8 <= nilOO7;

        initial

                niO0i3 = 0;

        always @ ( posedge clk)

                  niO0i3 <= niO0i4;

        event niO0i3_event;

        initial

                #1 ->niO0i3_event;

        always @(niO0i3_event)

                niO0i3 <= {1{1'b1}};

        initial

                niO0i4 = 0;

        always @ ( posedge clk)

                  niO0i4 <= niO0i3;

        initial

                niO0l1 = 0;

        always @ ( posedge clk)

                  niO0l1 <= niO0l2;

        event niO0l1_event;

        initial

                #1 ->niO0l1_event;

        always @(niO0l1_event)

                niO0l1 <= {1{1'b1}};

        initial

                niO0l2 = 0;

        always @ ( posedge clk)

                  niO0l2 <= niO0l1;

        initial

                niO1i5 = 0;

        always @ ( posedge clk)

                  niO1i5 <= niO1i6;

        event niO1i5_event;

        initial

                #1 ->niO1i5_event;

        always @(niO1i5_event)

                niO1i5 <= {1{1'b1}};

        initial

                niO1i6 = 0;

        always @ ( posedge clk)

                  niO1i6 <= niO1i5;

        initial

        begin

                nll0l = 0;

        end

        always @ ( posedge clk or  negedge reset_n)

        begin

                if (reset_n == 1'b0)

                begin

                        nll0l <= 0;

                end

                else if  (nliil == 1'b1)

                begin

                        nll0l <= niOil;

                end

        end

        event nll0l_event;

        initial

                #1 ->nll0l_event;

        always @(nll0l_event)

                nll0l <= 1;

        initial

        begin

                niOiO = 0;

                niOli = 0;

                niOll = 0;

                niOlO = 0;

                niOOi = 0;

                niOOl = 0;

                niOOO = 0;

                nl0Oi = 0;

                nl0Ol = 0;

                nl0OO = 0;

                nl10i = 0;

                nl10l = 0;

                nl10O = 0;

                nl11i = 0;

                nl11l = 0;

                nl11O = 0;

                nl1ii = 0;

                nl1il = 0;

                nl1li = 0;

                nli0i = 0;

                nli0l = 0;

                nli0O = 0;

                nli1i = 0;

                nli1l = 0;

                nli1O = 0;

                nliii = 0;

                nliil = 0;

                nliiO = 0;

                nlili = 0;

                nlill = 0;

                nlilO = 0;

                nliOi = 0;

                nliOl = 0;

                nliOO = 0;

                nll0O = 0;

                nll1i = 0;

                nll1l = 0;

                nll1O = 0;

                nllii = 0;

                nllil = 0;

                nlliO = 0;

                nllli = 0;

                nllll = 0;

                nlllO = 0;

                nllOi = 0;

                nllOl = 0;

                nllOO = 0;

                nlO0i = 0;

                nlO1i = 0;

                nlO1l = 0;

        end

        always @ (clk or wire_nlO1O_PRN or wire_nlO1O_CLRN)

        begin

                if (wire_nlO1O_PRN == 1'b0)

                begin

                        niOiO <= 1;

                        niOli <= 1;

                        niOll <= 1;

                        niOlO <= 1;

                        niOOi <= 1;

                        niOOl <= 1;

                        niOOO <= 1;

                        nl0Oi <= 1;

                        nl0Ol <= 1;

                        nl0OO <= 1;

                        nl10i <= 1;

                        nl10l <= 1;

                        nl10O <= 1;

                        nl11i <= 1;

                        nl11l <= 1;

                        nl11O <= 1;

                        nl1ii <= 1;

                        nl1il <= 1;

                        nl1li <= 1;

                        nli0i <= 1;

                        nli0l <= 1;

                        nli0O <= 1;

                        nli1i <= 1;

                        nli1l <= 1;

                        nli1O <= 1;

                        nliii <= 1;

                        nliil <= 1;

                        nliiO <= 1;

                        nlili <= 1;

                        nlill <= 1;

                        nlilO <= 1;

                        nliOi <= 1;

                        nliOl <= 1;

                        nliOO <= 1;

                        nll0O <= 1;

                        nll1i <= 1;

                        nll1l <= 1;

                        nll1O <= 1;

                        nllii <= 1;

                        nllil <= 1;

                        nlliO <= 1;

                        nllli <= 1;

                        nllll <= 1;

                        nlllO <= 1;

                        nllOi <= 1;

                        nllOl <= 1;

                        nllOO <= 1;

                        nlO0i <= 1;

                        nlO1i <= 1;

                        nlO1l <= 1;

                end

                else if  (wire_nlO1O_CLRN == 1'b0)

                begin

                        niOiO <= 0;

                        niOli <= 0;

                        niOll <= 0;

                        niOlO <= 0;

                        niOOi <= 0;

                        niOOl <= 0;

                        niOOO <= 0;

                        nl0Oi <= 0;

                        nl0Ol <= 0;

                        nl0OO <= 0;

                        nl10i <= 0;

                        nl10l <= 0;

                        nl10O <= 0;

                        nl11i <= 0;

                        nl11l <= 0;

                        nl11O <= 0;

                        nl1ii <= 0;

                        nl1il <= 0;

                        nl1li <= 0;

                        nli0i <= 0;

                        nli0l <= 0;

                        nli0O <= 0;

                        nli1i <= 0;

                        nli1l <= 0;

                        nli1O <= 0;

                        nliii <= 0;

                        nliil <= 0;

                        nliiO <= 0;

                        nlili <= 0;

                        nlill <= 0;

                        nlilO <= 0;

                        nliOi <= 0;

                        nliOl <= 0;

                        nliOO <= 0;

                        nll0O <= 0;

                        nll1i <= 0;

                        nll1l <= 0;

                        nll1O <= 0;

                        nllii <= 0;

                        nllil <= 0;

                        nlliO <= 0;

                        nllli <= 0;

                        nllll <= 0;

                        nlllO <= 0;

                        nllOi <= 0;

                        nllOl <= 0;

                        nllOO <= 0;

                        nlO0i <= 0;

                        nlO1i <= 0;

                        nlO1l <= 0;

                end

                else

                if (clk != nlO1O_clk_prev && clk == 1'b1)

                begin

                        niOiO <= (~ ni00i);

                        niOli <= (~ ni00l);

                        niOll <= (~ ni00O);

                        niOlO <= (~ ni0ii);

                        niOOi <= (~ ni0il);

                        niOOl <= (~ ni0iO);

                        niOOO <= (~ ni0li);

                        nl0Oi <= ((wire_ni0l_o[254] | wire_ni0l_o[251]) | wire_ni0l_o[247]);

                        nl0Ol <= (~ wire_ni0l_o[251]);

                        nl0OO <= (~ wire_ni0l_o[247]);

                        nl10i <= ni0Ol;

                        nl10l <= ni0OO;

                        nl10O <= nii1i;

                        nl11i <= (~ ni0ll);

                        nl11l <= (~ ni0lO);

                        nl11O <= (~ ni0Oi);

                        nl1ii <= nii1l;

                        nl1il <= nii1O;

                        nl1li <= (~ ni01O);

                        nli0i <= (((wire_ni0l_o[220] | wire_ni0l_o[92]) | wire_ni0l_o[28]) | (~ (niiiO36 ^ niiiO35)));

                        nli0l <= (~ niO1O);

                        nli0O <= ((((wire_ni0l_o[255] | wire_ni0l_o[124]) | wire_ni0l_o[92]) | wire_ni0l_o[60]) | (~ (niill34 ^ niill33)));

                        nli1i <= nil0i;

                        nli1l <= (~ ((((wire_ni0l_o[254] | wire_ni0l_o[253]) | wire_ni0l_o[251]) | wire_ni0l_o[247]) | (~ (niiii38 ^ niiii37))));

                        nli1O <= (~ niO1l);

                        nliii <= ((idle_ins | ena) | (~ (niiOi32 ^ niiOi31)));

                        nliil <= nliii;

                        nliiO <= nlili;

                        nlili <= ((kin | (~ ena)) | (~ (niiOO30 ^ niiOO29)));

                        nlill <= wire_niil_dataout;

                        nlilO <= wire_niiO_dataout;

                        nliOi <= wire_nili_dataout;

                        nliOl <= wire_nill_dataout;

                        nliOO <= wire_nilO_dataout;

                        nll0O <= nliil;

                        nll1i <= wire_niOi_dataout;

                        nll1l <= wire_niOl_dataout;

                        nll1O <= wire_niOO_dataout;

                        nllii <= wire_nlO0O_dataout;

                        nllil <= wire_nlOii_dataout;

                        nlliO <= wire_nlOil_dataout;

                        nllli <= wire_nlOiO_dataout;

                        nllll <= wire_nlOli_dataout;

                        nlllO <= wire_nlOll_dataout;

                        nllOi <= wire_nlOlO_dataout;

                        nllOl <= wire_nlOOi_dataout;

                        nllOO <= wire_nlOOl_dataout;

                        nlO0i <= ((wire_ni0l_o[253] | wire_ni0l_o[251]) | wire_ni0l_o[247]);

                        nlO1i <= wire_nlOOO_dataout;

                        nlO1l <= ((nliiO & (~ nl1il)) & (nil1l28 ^ nil1l27));

                end

                nlO1O_clk_prev <= clk;

        end

        assign

                wire_nlO1O_CLRN = ((nil0O24 ^ nil0O23) & reset_n),

                wire_nlO1O_PRN = (nil0l26 ^ nil0l25);

        assign          wire_n00i_dataout = (nliiO === 1'b1) ? nli1O : niOOl;

        assign          wire_n00l_dataout = (nliiO === 1'b1) ? nli0i : niOOO;

        assign          wire_n00O_dataout = (nliiO === 1'b1) ? nli0l : nl11i;

        assign          wire_n01i_dataout = (nliiO === 1'b1) ? nl0OO : niOll;

        assign          wire_n01l_dataout = (nliiO === 1'b1) ? nli1i : niOlO;

        assign          wire_n01O_dataout = (nliiO === 1'b1) ? nli1l : niOOi;

        assign          wire_n0ii_dataout = (nliiO === 1'b1) ? nli0O : nl11l;

        assign          wire_n0il_dataout = (nliiO === 1'b1) ? nl1ii : nl11O;

        or(wire_n0iO_dataout, nl10i, nliiO);

        or(wire_n0li_dataout, nl10l, nliiO);

        and(wire_n0ll_dataout, nl10O, ~(nliiO));

        assign          wire_n1Oi_dataout = (nliiO === 1'b1) ? nlO0i : nl1li;

        assign          wire_n1Ol_dataout = (nliiO === 1'b1) ? nl0Oi : niOiO;

        assign          wire_n1OO_dataout = (nliiO === 1'b1) ? nl0Ol : niOli;

        and(wire_niil_dataout, datain[0], ena);

        and(wire_niiO_dataout, datain[1], ena);

        or(wire_nili_dataout, datain[2], ~(ena));

        or(wire_nill_dataout, datain[3], ~(ena));

        or(wire_nilO_dataout, datain[4], ~(ena));

        or(wire_niOi_dataout, datain[5], ~(ena));

        and(wire_niOl_dataout, datain[6], ena);

        or(wire_niOO_dataout, datain[7], ~(ena));

        assign          wire_nl1i_dataout = (rdforce === 1'b1) ? rdin : nll0l;

        assign          wire_nlO0O_dataout = (wire_nl1i_dataout === 1'b1) ? wire_n11i_o : wire_n1Oi_dataout;

        assign          wire_nlOii_dataout = (wire_nl1i_dataout === 1'b1) ? wire_n11l_o : wire_n1Ol_dataout;

        assign          wire_nlOil_dataout = (wire_nl1i_dataout === 1'b1) ? wire_n11O_o : wire_n1OO_dataout;

        assign          wire_nlOiO_dataout = (wire_nl1i_dataout === 1'b1) ? wire_n10i_o : wire_n01i_dataout;

        assign          wire_nlOli_dataout = (wire_nl1i_dataout === 1'b1) ? wire_n10l_o : wire_n01l_dataout;

        assign          wire_nlOll_dataout = (wire_nl1i_dataout === 1'b1) ? wire_n10O_o : wire_n01O_dataout;

        assign          wire_nlOlO_dataout = (wire_nl1i_dataout === 1'b1) ? wire_n1ii_o : wire_n00i_dataout;

        assign          wire_nlOOi_dataout = (wire_nl1i_dataout === 1'b1) ? wire_n1il_o : wire_n00l_dataout;

        assign          wire_nlOOl_dataout = (wire_nl1i_dataout === 1'b1) ? wire_n1iO_o : wire_n00O_dataout;

        assign          wire_nlOOO_dataout = (wire_nl1i_dataout === 1'b1) ? wire_n1li_o : wire_n0ii_dataout;

        oper_decoder   ni0l

        (

        .i({nll1O, nll1l, nll1i, ((niO0i4 ^ niO0i3) & nliOO), nliOl, nliOi, nlilO, ((niO0l2 ^ niO0l1) & nlill)}),

        .o(wire_ni0l_o));

        defparam

                ni0l.width_i = 8,

                ni0l.width_o = 256;

        oper_decoder   nl0ii

        (

        .i({nliOO, nliOl, nliOi, nlilO, nlill}),

        .o(wire_nl0ii_o));

        defparam

                nl0ii.width_i = 5,

                nl0ii.width_o = 32;

        oper_decoder   nl0lO

        (

        .i({nll1O, nll1l, nll1i, nliOO, ((nii0i44 ^ nii0i43) & nliOl), nliOi, ((nii0l42 ^ nii0l41) & nlilO), ((nii0O40 ^ nii0O39) & nlill)}),

        .o(wire_nl0lO_o));

        defparam

                nl0lO.width_i = 8,

                nl0lO.width_o = 256;

        oper_mux   n10i

        (

        .data({(~ wire_n01i_dataout), wire_n01i_dataout, (~ wire_n01i_dataout), wire_n01i_dataout}),

        .o(wire_n10i_o),

        .sel({((niliO18 ^ niliO17) & wire_n0li_dataout), wire_n0iO_dataout}));

        defparam

                n10i.width_data = 4,

                n10i.width_sel = 2;

        oper_mux   n10l

        (

        .data({(~ wire_n01l_dataout), wire_n01l_dataout, (~ wire_n01l_dataout), wire_n01l_dataout}),

        .o(wire_n10l_o),

        .sel({wire_n0li_dataout, wire_n0iO_dataout}));

        defparam

                n10l.width_data = 4,

                n10l.width_sel = 2;

        oper_mux   n10O

        (

        .data({(~ wire_n01O_dataout), ((nilli16 ^ nilli15) & wire_n01O_dataout), (~ wire_n01O_dataout), wire_n01O_dataout}),

        .o(wire_n10O_o),

        .sel({wire_n0li_dataout, wire_n0iO_dataout}));

        defparam

                n10O.width_data = 4,

                n10O.width_sel = 2;

        oper_mux   n11i

        (

        .data({(~ wire_n1Oi_dataout), wire_n1Oi_dataout, (~ wire_n1Oi_dataout), wire_n1Oi_dataout}),

        .o(wire_n11i_o),

        .sel({wire_n0li_dataout, wire_n0iO_dataout}));

        defparam

                n11i.width_data = 4,

                n11i.width_sel = 2;

        oper_mux   n11l

        (

        .data({(~ wire_n1Ol_dataout), ((nilii22 ^ nilii21) & wire_n1Ol_dataout), (~ wire_n1Ol_dataout), wire_n1Ol_dataout}),

        .o(wire_n11l_o),

        .sel({wire_n0li_dataout, wire_n0iO_dataout}));

        defparam

                n11l.width_data = 4,

                n11l.width_sel = 2;

        oper_mux   n11O

        (

        .data({(~ wire_n1OO_dataout), wire_n1OO_dataout, (~ wire_n1OO_dataout), wire_n1OO_dataout}),

        .o(wire_n11O_o),

        .sel({wire_n0li_dataout, ((nilil20 ^ nilil19) & wire_n0iO_dataout)}));

        defparam

                n11O.width_data = 4,

                n11O.width_sel = 2;

        oper_mux   n1ii

        (

        .data({((nilll14 ^ nilll13) & (~ wire_n00i_dataout)), (~ wire_n00i_dataout), {2{wire_n00i_dataout}}}),

        .o(wire_n1ii_o),

        .sel({wire_n0li_dataout, wire_n0iO_dataout}));

        defparam

                n1ii.width_data = 4,

                n1ii.width_sel = 2;

        oper_mux   n1il

        (

        .data({{2{(~ wire_n00l_dataout)}}, wire_n00l_dataout, (wire_n0ll_dataout ^ wire_n00l_dataout)}),

        .o(wire_n1il_o),

        .sel({wire_n0li_dataout, wire_n0iO_dataout}));

        defparam

                n1il.width_data = 4,

                n1il.width_sel = 2;

        oper_mux   n1iO

        (

        .data({{2{(~ wire_n00O_dataout)}}, wire_n00O_dataout, ((wire_n0ll_dataout ^ wire_n00O_dataout) ^ (~ (nillO12 ^ nillO11)))}),

        .o(wire_n1iO_o),

        .sel({wire_n0li_dataout, ((nilOl10 ^ nilOl9) & wire_n0iO_dataout)}));

        defparam

                n1iO.width_data = 4,

                n1iO.width_sel = 2;

        oper_mux   n1li

        (

        .data({{2{(~ wire_n0ii_dataout)}}, ((nilOO8 ^ nilOO7) & wire_n0ii_dataout), wire_n0ii_dataout}),

        .o(wire_n1li_o),

        .sel({wire_n0li_dataout, ((niO1i6 ^ niO1i5) & wire_n0iO_dataout)}));

        defparam

                n1li.width_data = 4,

                n1li.width_sel = 2;

        assign

                dataout = {nlO1i, nllOO, nllOl, nllOi, nlllO, nllll, nllli, nlliO, nllil, nllii},

                kerr = nlO1l,

                ni00i = ((((((((((((wire_nl0ii_o[31] | wire_nl0ii_o[29]) | wire_nl0ii_o[2]) | wire_nl0ii_o[0]) | wire_nl0ii_o[28]) | wire_nl0ii_o[25]) | wire_nl0ii_o[21]) | wire_nl0ii_o[13]) | wire_nl0ii_o[12]) | wire_nl0ii_o[9]) | wire_nl0ii_o[5]) | wire_nl0ii_o[20]) | wire_nl0ii_o[17]),

                ni00l = (((((((((((((wire_nl0ii_o[27] | wire_nl0ii_o[24]) | wire_nl0ii_o[15]) | wire_nl0ii_o[4]) | wire_nl0ii_o[0]) | wire_nl0ii_o[26]) | wire_nl0ii_o[25]) | wire_nl0ii_o[19]) | wire_nl0ii_o[11]) | wire_nl0ii_o[10]) | wire_nl0ii_o[9]) | wire_nl0ii_o[3]) | wire_nl0ii_o[18]) | wire_nl0ii_o[17]),

                ni00O = ((((((((((((((wire_nl0ii_o[31] | wire_nl0ii_o[24]) | wire_nl0ii_o[23]) | wire_nl0ii_o[16]) | wire_nl0ii_o[8]) | wire_nl0ii_o[7]) | wire_nl0ii_o[22]) | wire_nl0ii_o[21]) | wire_nl0ii_o[19]) | wire_nl0ii_o[6]) | wire_nl0ii_o[5]) | wire_nl0ii_o[3]) | wire_nl0ii_o[20]) | wire_nl0ii_o[18]) | wire_nl0ii_o[17]),

                ni01O = ((((((((((((wire_nl0ii_o[30] | wire_nl0ii_o[16]) | wire_nl0ii_o[15]) | wire_nl0ii_o[1]) | wire_nl0ii_o[28]) | wire_nl0ii_o[26]) | wire_nl0ii_o[22]) | wire_nl0ii_o[14]) | wire_nl0ii_o[12]) | wire_nl0ii_o[10]) | wire_nl0ii_o[6]) | wire_nl0ii_o[20]) | wire_nl0ii_o[18]),

                ni0ii = (((((((((((((wire_nl0ii_o[8] | wire_nl0ii_o[7]) | wire_nl0ii_o[4]) | wire_nl0ii_o[2]) | wire_nl0ii_o[1]) | wire_nl0ii_o[14]) | wire_nl0ii_o[13]) | wire_nl0ii_o[11]) | wire_nl0ii_o[12]) | wire_nl0ii_o[10]) | wire_nl0ii_o[9]) | wire_nl0ii_o[6]) | wire_nl0ii_o[5]) | wire_nl0ii_o[3]),

                ni0il = (((((((((((((wire_nl0ii_o[30] | wire_nl0ii_o[29]) | wire_nl0ii_o[27]) | wire_nl0ii_o[23]) | wire_nl0ii_o[7]) | wire_nl0ii_o[28]) | wire_nl0ii_o[26]) | wire_nl0ii_o[25]) | wire_nl0ii_o[22]) | wire_nl0ii_o[21]) | wire_nl0ii_o[19]) | wire_nl0ii_o[14]) | wire_nl0ii_o[13]) | wire_nl0ii_o[11]),

                ni0iO = (((((((((((((((((w_nl01i1253w | wire_nl0lO_o[89]) | wire_nl0lO_o[86]) | wire_nl0lO_o[85]) | wire_nl0lO_o[84]) | wire_nl0lO_o[83]) | wire_nl0lO_o[82]) | wire_nl0lO_o[81]) | wire_nl0lO_o[78]) | wire_nl0lO_o[77]) | wire_nl0lO_o[76]) | wire_nl0lO_o[75]) | wire_nl0lO_o[74]) | wire_nl0lO_o[73]) | wire_nl0lO_o[71]) | wire_nl0lO_o[70]) | wire_nl0lO_o[69]) | wire_nl0lO_o[67]),

                ni0li = ((((((((((((((((((((w_nl01l1134w | wire_nl0lO_o[165]) | wire_nl0lO_o[163]) | wire_nl0lO_o[58]) | wire_nl0lO_o[57]) | wire_nl0lO_o[54]) | wire_nl0lO_o[53]) | wire_nl0lO_o[52]) | wire_nl0lO_o[51]) | wire_nl0lO_o[50]) | wire_nl0lO_o[49]) | wire_nl0lO_o[46]) | wire_nl0lO_o[45]) | wire_nl0lO_o[44]) | wire_nl0lO_o[43]) | wire_nl0lO_o[42]) | wire_nl0lO_o[41]) | wire_nl0lO_o[39]) | wire_nl0lO_o[38]) | wire_nl0lO_o[37]) | wire_nl0lO_o[35]),

                ni0ll = ((((((((((((((((((((((((((w_nl01O983w | wire_nl0lO_o[76]) | wire_nl0lO_o[75]) | wire_nl0lO_o[74]) | wire_nl0lO_o[73]) | wire_nl0lO_o[71]) | wire_nl0lO_o[70]) | wire_nl0lO_o[69]) | wire_nl0lO_o[67]) | wire_nl0lO_o[58]) | wire_nl0lO_o[57]) | wire_nl0lO_o[54]) | wire_nl0lO_o[53]) | wire_nl0lO_o[52]) | wire_nl0lO_o[51]) | wire_nl0lO_o[50]) | wire_nl0lO_o[49]) | wire_nl0lO_o[46]) | wire_nl0lO_o[45]) | wire_nl0lO_o[44]) | wire_nl0lO_o[43]) | wire_nl0lO_o[42]) | wire_nl0lO_o[41]) | wire_nl0lO_o[39]) | wire_nl0lO_o[38]) | wire_nl0lO_o[37]) | wire_nl0lO_o[35]),

                ni0lO = (((((((((((((((((((((((w_nl00i826w | wire_nl0lO_o[201]) | wire_nl0lO_o[199]) | wire_nl0lO_o[198]) | wire_nl0lO_o[197]) | wire_nl0lO_o[195]) | wire_nl0lO_o[186]) | wire_nl0lO_o[185]) | wire_nl0lO_o[182]) | wire_nl0lO_o[181]) | wire_nl0lO_o[180]) | wire_nl0lO_o[179]) | wire_nl0lO_o[178]) | wire_nl0lO_o[177]) | wire_nl0lO_o[174]) | wire_nl0lO_o[173]) | wire_nl0lO_o[172]) | wire_nl0lO_o[171]) | wire_nl0lO_o[170]) | wire_nl0lO_o[169]) | wire_nl0lO_o[167]) | wire_nl0lO_o[166]) | wire_nl0lO_o[165]) | wire_nl0lO_o[163]),

                ni0Oi = ((((((((((((((((((((w_nl00l670w | wire_nl0lO_o[80]) | wire_nl0lO_o[79]) | wire_nl0lO_o[72]) | wire_nl0lO_o[68]) | wire_nl0lO_o[66]) | wire_nl0lO_o[65]) | wire_nl0lO_o[64]) | wire_nl0lO_o[63]) | wire_nl0lO_o[62]) | wire_nl0lO_o[61]) | wire_nl0lO_o[59]) | wire_nl0lO_o[56]) | wire_nl0lO_o[55]) | wire_nl0lO_o[48]) | wire_nl0lO_o[47]) | wire_nl0lO_o[40]) | wire_nl0lO_o[36]) | wire_nl0lO_o[34]) | wire_nl0lO_o[33]) | wire_nl0lO_o[32]),

                ni0Ol = (((((((((((((wire_nl0ii_o[31] | wire_nl0ii_o[30]) | wire_nl0ii_o[29]) | wire_nl0ii_o[27]) | wire_nl0ii_o[24]) | wire_nl0ii_o[23]) | wire_nl0ii_o[16]) | wire_nl0ii_o[15]) | wire_nl0ii_o[8]) | wire_nl0ii_o[7]) | wire_nl0ii_o[4]) | wire_nl0ii_o[2]) | wire_nl0ii_o[1]) | wire_nl0ii_o[0]),

                ni0OO = ((((((((((((((((((((w_nl0il462w | wire_nl0lO_o[19]) | wire_nl0lO_o[18]) | wire_nl0lO_o[17]) | wire_nl0lO_o[16]) | wire_nl0lO_o[15]) | wire_nl0lO_o[14]) | wire_nl0lO_o[13]) | wire_nl0lO_o[12]) | wire_nl0lO_o[11]) | wire_nl0lO_o[10]) | wire_nl0lO_o[9]) | wire_nl0lO_o[8]) | wire_nl0lO_o[7]) | wire_nl0lO_o[6]) | wire_nl0lO_o[5]) | wire_nl0lO_o[4]) | wire_nl0lO_o[3]) | wire_nl0lO_o[2]) | wire_nl0lO_o[1]) | wire_nl0lO_o[0]),

                nii1i = (((((wire_nl0lO_o[244] | wire_nl0lO_o[242]) | wire_nl0lO_o[241]) | wire_nl0lO_o[238]) | wire_nl0lO_o[237]) | wire_nl0lO_o[235]),

                nii1l = (((((((wire_nl0lO_o[255] | wire_nl0lO_o[254]) | wire_nl0lO_o[253]) | wire_nl0lO_o[252]) | wire_nl0lO_o[251]) | wire_nl0lO_o[247]) | wire_nl0lO_o[156]) | wire_nl0lO_o[28]),

                nii1O = ((((((((((((wire_nl0lO_o[255] | wire_nl0lO_o[254]) | wire_nl0lO_o[253]) | wire_nl0lO_o[252]) | wire_nl0lO_o[251]) | wire_nl0lO_o[247]) | wire_nl0lO_o[220]) | wire_nl0lO_o[188]) | wire_nl0lO_o[156]) | wire_nl0lO_o[124]) | wire_nl0lO_o[92]) | wire_nl0lO_o[60]) | wire_nl0lO_o[28]),

                nil0i = 1'b1,

                niO1l = (((((wire_ni0l_o[255] | wire_ni0l_o[220]) | wire_ni0l_o[156]) | wire_ni0l_o[124]) | wire_ni0l_o[92]) | wire_ni0l_o[28]),

                niO1O = ((((((((wire_ni0l_o[255] | wire_ni0l_o[254]) | wire_ni0l_o[253]) | wire_ni0l_o[252]) | wire_ni0l_o[251]) | wire_ni0l_o[247]) | wire_ni0l_o[92]) | wire_ni0l_o[60]) | wire_ni0l_o[28]),

                niOil = ((~ wire_nl1i_dataout) ^ wire_n0il_dataout),

                rdcascade = niOil,

                rdout = nll0l,

                valid = nll0O,

                w_nl00i761w = ((((((((((((((((((((((((((((((((((((((((((((((((((wire_nl0lO_o[252] | wire_nl0lO_o[220]) | wire_nl0lO_o[188]) | wire_nl0lO_o[124]) | wire_nl0lO_o[238]) | wire_nl0lO_o[237]) | wire_nl0lO_o[235]) | wire_nl0lO_o[250]) | wire_nl0lO_o[249]) | wire_nl0lO_o[246]) | wire_nl0lO_o[245]) | wire_nl0lO_o[243]) | wire_nl0lO_o[236]) | wire_nl0lO_o[234]) | wire_nl0lO_o[233]) | wire_nl0lO_o[231]) | wire_nl0lO_o[230]) | wire_nl0lO_o[229]) | wire_nl0lO_o[227]) | wire_nl0lO_o[159]) | wire_nl0lO_o[158]) | wire_nl0lO_o[157]) | wire_nl0lO_o[155]) | wire_nl0lO_o[152]) | wire_nl0lO_o[151]) | wire_nl0lO_o[144]) | wire_nl0lO_o[143]) | wire_nl0lO_o[136]) | wire_nl0lO_o[132]) | wire_nl0lO_o[130]) | wire_nl0lO_o[129]) | wire_nl0lO_o[128]) | wire_nl0lO_o[122]) | wire_nl0lO_o[121]) | wire_nl0lO_o[118]) | wire_nl0lO_o[117]) | wire_nl0lO_o[116]) | wire_nl0lO_o[115]) | wire_nl0lO_o[114]) | wire_nl0lO_o[113]) | wire_nl0lO_o[110]) | wire_nl0lO_o[109]) | wire_nl0lO_o[108]) | wire_nl0lO_o[107]) | wire_nl0lO_o[106]) | wire_nl0lO_o[105]) | wire_nl0lO_o[103]) | wire_nl0lO_o[102]) | wire_nl0lO_o[101]) | wire_nl0lO_o[99]) | wire_nl0lO_o[31]),

                w_nl00i826w = (((((((((((((((((((((((((((((((((((((((((((((((((((w_nl00i761w | wire_nl0lO_o[30]) | wire_nl0lO_o[29]) | wire_nl0lO_o[27]) | wire_nl0lO_o[24]) | wire_nl0lO_o[23]) | wire_nl0lO_o[16]) | wire_nl0lO_o[15]) | wire_nl0lO_o[8]) | wire_nl0lO_o[4]) | wire_nl0lO_o[2]) | wire_nl0lO_o[1]) | wire_nl0lO_o[0]) | wire_nl0lO_o[223]) | wire_nl0lO_o[222]) | wire_nl0lO_o[221]) | wire_nl0lO_o[219]) | wire_nl0lO_o[216]) | wire_nl0lO_o[215]) | wire_nl0lO_o[208]) | wire_nl0lO_o[207]) | wire_nl0lO_o[200]) | wire_nl0lO_o[196]) | wire_nl0lO_o[194]) | wire_nl0lO_o[193]) | wire_nl0lO_o[192]) | wire_nl0lO_o[191]) | wire_nl0lO_o[190]) | wire_nl0lO_o[189]) | wire_nl0lO_o[187]) | wire_nl0lO_o[184]) | wire_nl0lO_o[183]) | wire_nl0lO_o[176]) | wire_nl0lO_o[175]) | wire_nl0lO_o[168]) | wire_nl0lO_o[164]) | wire_nl0lO_o[162]) | wire_nl0lO_o[161]) | wire_nl0lO_o[160]) | wire_nl0lO_o[218]) | wire_nl0lO_o[217]) | wire_nl0lO_o[214]) | wire_nl0lO_o[213]) | wire_nl0lO_o[212]) | wire_nl0lO_o[211]) | wire_nl0lO_o[210]) | wire_nl0lO_o[209]) | wire_nl0lO_o[206]) | wire_nl0lO_o[205]) | wire_nl0lO_o[204]) | wire_nl0lO_o[203]) | wire_nl0lO_o[202]),

                w_nl00l586w = ((((((((((((((((((((((((((((((((((((((((((((((((((wire_nl0lO_o[252] | wire_nl0lO_o[156]) | wire_nl0lO_o[28]) | wire_nl0lO_o[244]) | wire_nl0lO_o[242]) | wire_nl0lO_o[241]) | wire_nl0lO_o[238]) | wire_nl0lO_o[237]) | wire_nl0lO_o[235]) | wire_nl0lO_o[250]) | wire_nl0lO_o[249]) | wire_nl0lO_o[246]) | wire_nl0lO_o[245]) | wire_nl0lO_o[243]) | wire_nl0lO_o[236]) | wire_nl0lO_o[234]) | wire_nl0lO_o[233]) | wire_nl0lO_o[231]) | wire_nl0lO_o[230]) | wire_nl0lO_o[229]) | wire_nl0lO_o[227]) | wire_nl0lO_o[154]) | wire_nl0lO_o[153]) | wire_nl0lO_o[150]) | wire_nl0lO_o[149]) | wire_nl0lO_o[148]) | wire_nl0lO_o[147]) | wire_nl0lO_o[146]) | wire_nl0lO_o[145]) | wire_nl0lO_o[142]) | wire_nl0lO_o[141]) | wire_nl0lO_o[140]) | wire_nl0lO_o[139]) | wire_nl0lO_o[138]) | wire_nl0lO_o[137]) | wire_nl0lO_o[135]) | wire_nl0lO_o[134]) | wire_nl0lO_o[133]) | wire_nl0lO_o[131]) | wire_nl0lO_o[127]) | wire_nl0lO_o[126]) | wire_nl0lO_o[125]) | wire_nl0lO_o[123]) | wire_nl0lO_o[120]) | wire_nl0lO_o[119]) | wire_nl0lO_o[112]) | wire_nl0lO_o[111]) | wire_nl0lO_o[104]) | wire_nl0lO_o[100]) | wire_nl0lO_o[98]) | wire_nl0lO_o[97]),

                w_nl00l670w = (((((((((((((((((((((((((((((((((((((((((((((((((((w_nl00l586w | wire_nl0lO_o[96]) | wire_nl0lO_o[26]) | wire_nl0lO_o[25]) | wire_nl0lO_o[22]) | wire_nl0lO_o[21]) | wire_nl0lO_o[20]) | wire_nl0lO_o[19]) | wire_nl0lO_o[18]) | wire_nl0lO_o[17]) | wire_nl0lO_o[14]) | wire_nl0lO_o[13]) | wire_nl0lO_o[12]) | wire_nl0lO_o[11]) | wire_nl0lO_o[10]) | wire_nl0lO_o[9]) | wire_nl0lO_o[7]) | wire_nl0lO_o[6]) | wire_nl0lO_o[5]) | wire_nl0lO_o[3]) | wire_nl0lO_o[223]) | wire_nl0lO_o[222]) | wire_nl0lO_o[221]) | wire_nl0lO_o[219]) | wire_nl0lO_o[216]) | wire_nl0lO_o[215]) | wire_nl0lO_o[208]) | wire_nl0lO_o[207]) | wire_nl0lO_o[200]) | wire_nl0lO_o[196]) | wire_nl0lO_o[194]) | wire_nl0lO_o[193]) | wire_nl0lO_o[192]) | wire_nl0lO_o[191]) | wire_nl0lO_o[190]) | wire_nl0lO_o[189]) | wire_nl0lO_o[187]) | wire_nl0lO_o[184]) | wire_nl0lO_o[183]) | wire_nl0lO_o[176]) | wire_nl0lO_o[175]) | wire_nl0lO_o[168]) | wire_nl0lO_o[164]) | wire_nl0lO_o[162]) | wire_nl0lO_o[161]) | wire_nl0lO_o[160]) | wire_nl0lO_o[95]) | wire_nl0lO_o[94]) | wire_nl0lO_o[93]) | wire_nl0lO_o[91]) | wire_nl0lO_o[88]) | wire_nl0lO_o[87]),

                w_nl01i1201w = ((((((((((((((((((((((((((((((((((((((((((((((((((wire_nl0lO_o[255] | wire_nl0lO_o[254]) | wire_nl0lO_o[253]) | wire_nl0lO_o[251]) | wire_nl0lO_o[247]) | wire_nl0lO_o[220]) | wire_nl0lO_o[92]) | wire_nl0lO_o[244]) | wire_nl0lO_o[242]) | wire_nl0lO_o[241]) | wire_nl0lO_o[248]) | wire_nl0lO_o[240]) | wire_nl0lO_o[239]) | wire_nl0lO_o[232]) | wire_nl0lO_o[228]) | wire_nl0lO_o[226]) | wire_nl0lO_o[225]) | wire_nl0lO_o[224]) | wire_nl0lO_o[159]) | wire_nl0lO_o[158]) | wire_nl0lO_o[157]) | wire_nl0lO_o[155]) | wire_nl0lO_o[152]) | wire_nl0lO_o[151]) | wire_nl0lO_o[144]) | wire_nl0lO_o[143]) | wire_nl0lO_o[136]) | wire_nl0lO_o[132]) | wire_nl0lO_o[130]) | wire_nl0lO_o[129]) | wire_nl0lO_o[128]) | wire_nl0lO_o[127]) | wire_nl0lO_o[126]) | wire_nl0lO_o[125]) | wire_nl0lO_o[123]) | wire_nl0lO_o[120]) | wire_nl0lO_o[119]) | wire_nl0lO_o[112]) | wire_nl0lO_o[111]) | wire_nl0lO_o[104]) | wire_nl0lO_o[100]) | wire_nl0lO_o[98]) | wire_nl0lO_o[97]) | wire_nl0lO_o[96]) | wire_nl0lO_o[31]) | wire_nl0lO_o[30]) | wire_nl0lO_o[29]) | wire_nl0lO_o[27]) | wire_nl0lO_o[24]) | wire_nl0lO_o[23]) | wire_nl0lO_o[16]),

                w_nl01i1253w = (((((((((((((((((((((((((((((((((((((((((((((((((((w_nl01i1201w | wire_nl0lO_o[15]) | wire_nl0lO_o[8]) | wire_nl0lO_o[4]) | wire_nl0lO_o[2]) | wire_nl0lO_o[1]) | wire_nl0lO_o[0]) | wire_nl0lO_o[223]) | wire_nl0lO_o[222]) | wire_nl0lO_o[221]) | wire_nl0lO_o[219]) | wire_nl0lO_o[216]) | wire_nl0lO_o[215]) | wire_nl0lO_o[208]) | wire_nl0lO_o[207]) | wire_nl0lO_o[200]) | wire_nl0lO_o[196]) | wire_nl0lO_o[194]) | wire_nl0lO_o[193]) | wire_nl0lO_o[192]) | wire_nl0lO_o[95]) | wire_nl0lO_o[94]) | wire_nl0lO_o[93]) | wire_nl0lO_o[91]) | wire_nl0lO_o[88]) | wire_nl0lO_o[87]) | wire_nl0lO_o[80]) | wire_nl0lO_o[79]) | wire_nl0lO_o[72]) | wire_nl0lO_o[68]) | wire_nl0lO_o[66]) | wire_nl0lO_o[65]) | wire_nl0lO_o[64]) | wire_nl0lO_o[218]) | wire_nl0lO_o[217]) | wire_nl0lO_o[214]) | wire_nl0lO_o[213]) | wire_nl0lO_o[212]) | wire_nl0lO_o[211]) | wire_nl0lO_o[210]) | wire_nl0lO_o[209]) | wire_nl0lO_o[206]) | wire_nl0lO_o[205]) | wire_nl0lO_o[204]) | wire_nl0lO_o[203]) | wire_nl0lO_o[202]) | wire_nl0lO_o[201]) | wire_nl0lO_o[199]) | wire_nl0lO_o[198]) | wire_nl0lO_o[197]) | wire_nl0lO_o[195]) | wire_nl0lO_o[90]),

                w_nl01l1082w = ((((((((((((((((((((((((((((((((((((((((((((((((((wire_nl0lO_o[255] | wire_nl0lO_o[254]) | wire_nl0lO_o[253]) | wire_nl0lO_o[251]) | wire_nl0lO_o[247]) | wire_nl0lO_o[188]) | wire_nl0lO_o[60]) | wire_nl0lO_o[28]) | wire_nl0lO_o[248]) | wire_nl0lO_o[240]) | wire_nl0lO_o[239]) | wire_nl0lO_o[232]) | wire_nl0lO_o[228]) | wire_nl0lO_o[226]) | wire_nl0lO_o[225]) | wire_nl0lO_o[224]) | wire_nl0lO_o[159]) | wire_nl0lO_o[158]) | wire_nl0lO_o[157]) | wire_nl0lO_o[155]) | wire_nl0lO_o[152]) | wire_nl0lO_o[151]) | wire_nl0lO_o[144]) | wire_nl0lO_o[143]) | wire_nl0lO_o[136]) | wire_nl0lO_o[132]) | wire_nl0lO_o[130]) | wire_nl0lO_o[129]) | wire_nl0lO_o[128]) | wire_nl0lO_o[127]) | wire_nl0lO_o[126]) | wire_nl0lO_o[125]) | wire_nl0lO_o[123]) | wire_nl0lO_o[120]) | wire_nl0lO_o[119]) | wire_nl0lO_o[112]) | wire_nl0lO_o[111]) | wire_nl0lO_o[104]) | wire_nl0lO_o[100]) | wire_nl0lO_o[98]) | wire_nl0lO_o[97]) | wire_nl0lO_o[96]) | wire_nl0lO_o[26]) | wire_nl0lO_o[25]) | wire_nl0lO_o[22]) | wire_nl0lO_o[21]) | wire_nl0lO_o[20]) | wire_nl0lO_o[19]) | wire_nl0lO_o[18]) | wire_nl0lO_o[17]) | wire_nl0lO_o[14]),

                w_nl01l1134w = (((((((((((((((((((((((((((((((((((((((((((((((((((w_nl01l1082w | wire_nl0lO_o[13]) | wire_nl0lO_o[12]) | wire_nl0lO_o[11]) | wire_nl0lO_o[10]) | wire_nl0lO_o[9]) | wire_nl0lO_o[7]) | wire_nl0lO_o[6]) | wire_nl0lO_o[5]) | wire_nl0lO_o[3]) | wire_nl0lO_o[191]) | wire_nl0lO_o[190]) | wire_nl0lO_o[189]) | wire_nl0lO_o[187]) | wire_nl0lO_o[184]) | wire_nl0lO_o[183]) | wire_nl0lO_o[176]) | wire_nl0lO_o[175]) | wire_nl0lO_o[168]) | wire_nl0lO_o[164]) | wire_nl0lO_o[162]) | wire_nl0lO_o[161]) | wire_nl0lO_o[160]) | wire_nl0lO_o[63]) | wire_nl0lO_o[62]) | wire_nl0lO_o[61]) | wire_nl0lO_o[59]) | wire_nl0lO_o[56]) | wire_nl0lO_o[55]) | wire_nl0lO_o[48]) | wire_nl0lO_o[47]) | wire_nl0lO_o[40]) | wire_nl0lO_o[36]) | wire_nl0lO_o[34]) | wire_nl0lO_o[33]) | wire_nl0lO_o[32]) | wire_nl0lO_o[186]) | wire_nl0lO_o[185]) | wire_nl0lO_o[182]) | wire_nl0lO_o[181]) | wire_nl0lO_o[180]) | wire_nl0lO_o[179]) | wire_nl0lO_o[178]) | wire_nl0lO_o[177]) | wire_nl0lO_o[174]) | wire_nl0lO_o[173]) | wire_nl0lO_o[172]) | wire_nl0lO_o[171]) | wire_nl0lO_o[170]) | wire_nl0lO_o[169]) | wire_nl0lO_o[167]) | wire_nl0lO_o[166]),

                w_nl01O921w = ((((((((((((((((((((((((((((((((((((((((((((((((((wire_nl0lO_o[255] | wire_nl0lO_o[254]) | wire_nl0lO_o[253]) | wire_nl0lO_o[251]) | wire_nl0lO_o[247]) | wire_nl0lO_o[156]) | wire_nl0lO_o[124]) | wire_nl0lO_o[92]) | wire_nl0lO_o[60]) | wire_nl0lO_o[248]) | wire_nl0lO_o[240]) | wire_nl0lO_o[239]) | wire_nl0lO_o[232]) | wire_nl0lO_o[228]) | wire_nl0lO_o[226]) | wire_nl0lO_o[225]) | wire_nl0lO_o[224]) | wire_nl0lO_o[154]) | wire_nl0lO_o[153]) | wire_nl0lO_o[150]) | wire_nl0lO_o[149]) | wire_nl0lO_o[148]) | wire_nl0lO_o[147]) | wire_nl0lO_o[146]) | wire_nl0lO_o[145]) | wire_nl0lO_o[142]) | wire_nl0lO_o[141]) | wire_nl0lO_o[140]) | wire_nl0lO_o[139]) | wire_nl0lO_o[138]) | wire_nl0lO_o[137]) | wire_nl0lO_o[135]) | wire_nl0lO_o[134]) | wire_nl0lO_o[133]) | wire_nl0lO_o[131]) | wire_nl0lO_o[122]) | wire_nl0lO_o[121]) | wire_nl0lO_o[118]) | wire_nl0lO_o[117]) | wire_nl0lO_o[116]) | wire_nl0lO_o[115]) | wire_nl0lO_o[114]) | wire_nl0lO_o[113]) | wire_nl0lO_o[110]) | wire_nl0lO_o[109]) | wire_nl0lO_o[108]) | wire_nl0lO_o[107]) | wire_nl0lO_o[106]) | wire_nl0lO_o[105]) | wire_nl0lO_o[103]) | wire_nl0lO_o[102]),

                w_nl01O983w = (((((((((((((((((((((((((((((((((((((((((((((((((((w_nl01O921w | wire_nl0lO_o[101]) | wire_nl0lO_o[99]) | wire_nl0lO_o[31]) | wire_nl0lO_o[30]) | wire_nl0lO_o[29]) | wire_nl0lO_o[27]) | wire_nl0lO_o[24]) | wire_nl0lO_o[23]) | wire_nl0lO_o[16]) | wire_nl0lO_o[15]) | wire_nl0lO_o[8]) | wire_nl0lO_o[4]) | wire_nl0lO_o[2]) | wire_nl0lO_o[1]) | wire_nl0lO_o[0]) | wire_nl0lO_o[95]) | wire_nl0lO_o[94]) | wire_nl0lO_o[93]) | wire_nl0lO_o[91]) | wire_nl0lO_o[88]) | wire_nl0lO_o[87]) | wire_nl0lO_o[80]) | wire_nl0lO_o[79]) | wire_nl0lO_o[72]) | wire_nl0lO_o[68]) | wire_nl0lO_o[66]) | wire_nl0lO_o[65]) | wire_nl0lO_o[64]) | wire_nl0lO_o[63]) | wire_nl0lO_o[62]) | wire_nl0lO_o[61]) | wire_nl0lO_o[59]) | wire_nl0lO_o[56]) | wire_nl0lO_o[55]) | wire_nl0lO_o[48]) | wire_nl0lO_o[47]) | wire_nl0lO_o[40]) | wire_nl0lO_o[36]) | wire_nl0lO_o[34]) | wire_nl0lO_o[33]) | wire_nl0lO_o[32]) | wire_nl0lO_o[90]) | wire_nl0lO_o[89]) | wire_nl0lO_o[86]) | wire_nl0lO_o[85]) | wire_nl0lO_o[84]) | wire_nl0lO_o[83]) | wire_nl0lO_o[82]) | wire_nl0lO_o[81]) | wire_nl0lO_o[78]) | wire_nl0lO_o[77]),

                w_nl0il359w = ((((((((((((((((((((((((((((((((((((((((((((((((((wire_nl0lO_o[255] | wire_nl0lO_o[254]) | wire_nl0lO_o[253]) | wire_nl0lO_o[252]) | wire_nl0lO_o[251]) | wire_nl0lO_o[247]) | wire_nl0lO_o[156]) | wire_nl0lO_o[124]) | wire_nl0lO_o[28]) | wire_nl0lO_o[250]) | wire_nl0lO_o[249]) | wire_nl0lO_o[248]) | wire_nl0lO_o[246]) | wire_nl0lO_o[245]) | wire_nl0lO_o[243]) | wire_nl0lO_o[240]) | wire_nl0lO_o[239]) | wire_nl0lO_o[236]) | wire_nl0lO_o[234]) | wire_nl0lO_o[233]) | wire_nl0lO_o[232]) | wire_nl0lO_o[231]) | wire_nl0lO_o[230]) | wire_nl0lO_o[229]) | wire_nl0lO_o[228]) | wire_nl0lO_o[227]) | wire_nl0lO_o[226]) | wire_nl0lO_o[225]) | wire_nl0lO_o[224]) | wire_nl0lO_o[159]) | wire_nl0lO_o[158]) | wire_nl0lO_o[157]) | wire_nl0lO_o[155]) | wire_nl0lO_o[154]) | wire_nl0lO_o[153]) | wire_nl0lO_o[152]) | wire_nl0lO_o[151]) | wire_nl0lO_o[150]) | wire_nl0lO_o[149]) | wire_nl0lO_o[148]) | wire_nl0lO_o[147]) | wire_nl0lO_o[146]) | wire_nl0lO_o[145]) | wire_nl0lO_o[144]) | wire_nl0lO_o[143]) | wire_nl0lO_o[142]) | wire_nl0lO_o[141]) | wire_nl0lO_o[140]) | wire_nl0lO_o[139]) | wire_nl0lO_o[138]) | wire_nl0lO_o[137]),

                w_nl0il462w = (((((((((((((((((((((((((((((((((((((((((((((((((((w_nl0il359w | wire_nl0lO_o[136]) | wire_nl0lO_o[135]) | wire_nl0lO_o[134]) | wire_nl0lO_o[133]) | wire_nl0lO_o[132]) | wire_nl0lO_o[131]) | wire_nl0lO_o[130]) | wire_nl0lO_o[129]) | wire_nl0lO_o[128]) | wire_nl0lO_o[127]) | wire_nl0lO_o[126]) | wire_nl0lO_o[125]) | wire_nl0lO_o[123]) | wire_nl0lO_o[122]) | wire_nl0lO_o[121]) | wire_nl0lO_o[120]) | wire_nl0lO_o[119]) | wire_nl0lO_o[118]) | wire_nl0lO_o[117]) | wire_nl0lO_o[116]) | wire_nl0lO_o[115]) | wire_nl0lO_o[114]) | wire_nl0lO_o[113]) | wire_nl0lO_o[112]) | wire_nl0lO_o[111]) | wire_nl0lO_o[110]) | wire_nl0lO_o[109]) | wire_nl0lO_o[108]) | wire_nl0lO_o[107]) | wire_nl0lO_o[106]) | wire_nl0lO_o[105]) | wire_nl0lO_o[104]) | wire_nl0lO_o[103]) | wire_nl0lO_o[102]) | wire_nl0lO_o[101]) | wire_nl0lO_o[100]) | wire_nl0lO_o[99]) | wire_nl0lO_o[98]) | wire_nl0lO_o[97]) | wire_nl0lO_o[96]) | wire_nl0lO_o[31]) | wire_nl0lO_o[30]) | wire_nl0lO_o[29]) | wire_nl0lO_o[27]) | wire_nl0lO_o[26]) | wire_nl0lO_o[25]) | wire_nl0lO_o[24]) | wire_nl0lO_o[23]) | wire_nl0lO_o[22]) | wire_nl0lO_o[21]) | wire_nl0lO_o[20]);

endmodule //mAlt8b10benc

//synopsys translate_on

//VALID FILE