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[/] [sgmii/] [trunk/] [src/] [mAltGX/] [mAlt8b10benc_run_modelsim.tcl] - Blame information for rev 13

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#!/usr/bin/env tcl
######################################################################
#
# Synopsis:
# tcl run_modelsim.tcl [-option value]* (Unix Systems)
# vish run_modelsim.tcl [-option value]* (Any Command Line)
# do run_modelsim.tcl [-option value]* (Modelsim GUI)
#
# Options:
#   -gate <device_family>
#     Forces Script to run Gate Level Simulation with <device_family>
#     Simulation Model must have been compiled using quartus_eda
#   -tbfile <testbench[.v|.vhd]>
#     Specifies Testbench File Name
#   -tbmod <testbench_module_name>
#     Specifies Testbench Module Name
#   -simfile <simulation_model[.vo|.vho]>
#     Specifies IP Functional Simulation Model File Name
#
# Usage:
# *The Filename for this script must be have a .tcl extension
#  To run a testbench specify the testbench file, the simulation
#  model file (.vo or .vho), and the testbench module name.
#  This can be done by either editing the DEFAULTS SECTION given 
#  below or by means of command line arguments.
# *This script uses the file name of the simulation model to determine
#  whether to run either a verilog (.vo) or vhdl (.vho) simulation.
#  If there are additional Verilog or VHDL files that need to be
#  compiled they can be specified under their respective lists in the
#  DEFAULTS SECTION (Reminder: you can use '\' for line continuation)
# *The script defaults to running simgen simulations.
#  To run a Gate Level Simulation you must use the '-gate' option.
#  Libraries for the respective device families must be supplied
#  in the QUARTUS LIBRARIES SECTION (See Below).
#
# Prerequisistes:
# This script is assumes that the user successfully ran IPToolBench
# and has all the necessary files (.vo, .iv. etc.) in the folder
# In the case of a Gate Level Simulation the '.vo'/'.vho' file must
# have been previously compiled using quartus_eda and the device family
# specified by '-gate' should match the device family with which the 
# Simulation Model was compiled with.  A version of Modelsim compatible
# with the simulation file must also be available and the path to the 
# Modelsim commands must be included in the PATH environment variable.
# Ideally you should run this script using 'vish' in the command line. 
# The script can also be executed using the Modelsim GUI using  
# 'do run_modelsim.tcl'.  You cannot execute the script if 
# QUARTUS_ROOTDIR Environment Variable is not set to a valid
# Quartus II Installation.
# 
# Simulator Output:
# run_modelsim.log
#
# Device Family Libraries supported in Current Version:
# stratix, stratixii, stratixgx, stratixiigx, cyclone, cycloneii,
# apexii, apex20ke, apex20kc, cycloneii, hardcopyii
#
########################################################################
 
########################################################################
# DEFAULTS SECTION                                                     #
########################################################################
# Edit these Variables to match your required Testbench Settings       #
 
# Default Device Family
# e.g. "stratixii"
set def_device_fam "stingray"
# Default Testbench File
# e.g. "rio_c_8_32_4_tb.v"
set def_test_bench "mAlt8b10benc_tb.v"
# Default Model Language
# e.g. "verilog"
set def_model_lang "verilog"
# Default Simgen/Gate Level Model Filename
# e.g. rio_c_8_32_4.vo or rio_c_8_32_4.vho
set def_model_file "mAlt8b10benc.vo"
# Default Testbench Modelsim Module
# Usually this is set to 'tb' or something like 'slite_tb'
set def_model_tb "tb"
# List of Additional Verilog Files to be Compiled
# e.g. {sii_clk_gen.v sii_av_master.v sii_reset.v}
set add_verilog_files {}
# List of Additional VHDL Files to be Compiled
# e.g. {sii_clk_gen.vhd sii_clk_gen_components.vhd}
set add_vhdl_files {}
 
if {[catch {vsim -version} ]} {
 set shell 1
} else {
 set shell 0
}
 
# Procedure to display Info Messages
proc myinfo { args } {
  global shell
  foreach mesg $args {
    if {$shell} {
      puts stdout "\# Info: $mesg"
    } else {
      puts "\# Info: $mesg"
    }
  }
}
 
# Procedure to display Error Messages and exit the script
proc myerror { args } {
  global shell
  foreach mesg $args {
    if {$shell} {
      puts stderr "\# Error: $mesg"
    } else {
      puts "\# Error: $mesg"
    }
  }
  if {$shell} {
    exit
  } else {
    error "Terminating script"
  }
}
 
# Procedure to run an external command (such as vsim)
proc myexec { args } {
  global shell
  if {$shell} {
    eval "exec $args"
  } else {
    eval $args
  }
}
 
########################################################################
# END DEFAULTS SECTION                                                 #
########################################################################
# Get Command Line Arguments
# Gate Level Simulation must be specified along with a device family name
if {[info exists device_fam]} {
  unset device_fam
}
if {[info exists testbench]} {
  unset testbench
}
if {[info exists model_tb]} {
  unset model_tb
}
if {[info exists model_file]} {
  unset model_file
}
 
foreach arg $argv {
  if {[info exists next_val]} {
    set $next_val $arg
    unset next_val
  } else {
    if {[string match -nocase "-gate" $arg]} {
      set next_val "device_fam";
    } elseif {[string match -nocase "-tbfile" $arg]} {
      set next_val "testbench"
    } elseif {[string match -nocase "-tbmod" $arg]} {
      set next_val "model_tb"
    } elseif {[string match -nocase "-simfile" $arg]} {
      set next_val "model_file"
    } elseif {[string match -nocase "-gui" $arg]} {
      myinfo "Testbench is run in GUI mode"
    } else {
      myerror "Invalid Argument Specified: $arg\n"
    }
  }
}
 
if {![info exists device_fam]} {
  set device_fam $def_device_fam
}
if {![info exists testbench]} {
  set testbench $def_test_bench
}
if {![info exists model_tb]} {
  set model_tb $def_model_tb
}
if {![info exists model_file]} {
  set model_file $def_model_file
}
 
# Check to make sure script is being run in the correct directory
if {![file exists $testbench]} {
  if {[file exists tb.v]} {
    file copy tb.v $testbench
  } else {
    set mesg1 "Testbench File not Found.\n"
    set mesg2 "Please run from the testbench directory\n"
    myerror $mesg1 $mesg2
  }
}
 
# Identify Simulation Type through Filename  
if {[string match -nocase "*.vo" $model_file]} {
  set model_file [string trimright $model_file "vo"]
  set model_file [string trimright $model_file "."]
  set f_ext ".vo"
  set exec_com "vlog"
  set exec_arg1 "-hazards"
  set exec_arg2 "-work"
} elseif {[string match -nocase "*.vho" $model_file]} {
  set model_file [string trimright $model_file "vho"]
  set model_file [string trimright $model_file "."]
  set f_ext ".vho"
  set exec_com "vcom"
  set exec_arg1 "-93"
  set exec_arg2 "-work"
} else {
  myerror "Unrecognized File Extension for $model_file\n"
}
 
# Check for presence of IP functional simulation model
if {![file exists ${model_file}${f_ext}]} {
  set mesg1 "Can't find Verilog IP Functional Simulation Model."
  set mesg2 "Make sure it is created before attempting to run this script."
  myerror $mesg1 $mesg2
}
 
# Get Location of Quartus Libraries
global env
 
if {[info exists env(QUARTUS_ROOTDIR)]} {
  set lib_path "$env(QUARTUS_ROOTDIR)/eda/sim_lib/"
} else {
  myerror "Can't find QUARTUS II\n"
}
 
########################################################################
# QUARTUS LIBRARIES SECTION                                            #
########################################################################
# Edit this section to add support for additional device families      #
 
# Library Information for Modelsim
# ORDER OF FILES IS IMPORTANT
# $libraries: A list with library names
# $lib_files: A nested list of library files for items in $libraries
#              Files must be located in $QUARTUS_ROOTDIR/eda/sim_libs/
if {$f_ext == ".vo"} {
  # Default Simgen Libraries
  set libraries {lpm altera_mf sgate }
  set lib_files {{220model.v} {altera_mf.v} {sgate.v} }
} else {
  # Default Simgen Libraries
  set libraries {lpm altera_mf sgate }
  set lib_files {{220pack.vhd 220model.vhd } \
    {altera_mf_components.vhd altera_mf.vhd } \
    {sgate_pack.vhd sgate.vhd} }
}
 
########################################################################
# END QUARTUS LIBRARIES SECTION                                        #
########################################################################
 
# Remove modelsim.ini
if {[file exists modelsim.ini]} {
  myinfo "Removing modelsim.ini"
  file delete -force modelsim.ini
}
 
set includ_str ""
# Check if we are running a version of ModelSim Altera Edition
set version [myexec vsim -version]
if {[string match -nocase "*ALTERA*" $version]} {
  # Verilog Libraries have a '_ver' appended
  if {$f_ext == ".vo"} {
    set ver_addon "_ver"
  } else {
    set ver_addon ""
  }
  # Map Precompiled Libraries to current Project
  foreach lib_dir $libraries {
    myinfo "Including Library ${lib_dir}${ver_addon}"
    append includ_str " -L ${lib_dir}${ver_addon}"
  }
} else {
  # If we aren't running an Altera Edition of Modelsim,
  # take information from $libraries and $lib_files
  # to compile the Modelsim libraries for Simulation
  set lib_count 0
  foreach lib_dir $libraries {
    if {[file isdirectory $lib_dir]} {
      myinfo "Cleaning ${lib_dir} Directory"
      file delete -force $lib_dir
    }
    myinfo "Compiling Library ${lib_dir}"
    myexec vlib $lib_dir
    foreach lib_file [lindex $lib_files $lib_count] {
      myexec $exec_com $exec_arg1 $exec_arg2 $lib_dir ${lib_path}${lib_file}
    }
    set lib_count [expr $lib_count+1]
    append includ_str " -L $lib_dir"
  }
}
 
# Compile Simulation Model
if {[file isdirectory $model_file]} {
  myinfo "Cleaning ${model_file} Directory"
  file delete -force $model_file
}
myinfo "Compiling Model $model_file"
myexec vlib $model_file
myexec $exec_com $exec_arg2 $model_file ${model_file}${f_ext}
append includ_str " -L $model_file"
 
# Clean work Directory
if {[file isdirectory work]} {
  myinfo "Cleaning work Directory"
  file delete -force work
}
myexec vlib work
myexec vmap work
 
# Compile Testbench
 
myinfo "Compiling Testbench $testbench"
if {[string match -nocase "*.v" $testbench]} {
  myexec vlog -hazards -work work $testbench
} elseif {[string match -nocase "*.vhd" $testbench]} {
  vcom -93 -work work $testbench
} else {
  myerror "Unrecognized Testbench File Extension\n"
}
 
# Compile Extra Files if specified
 
foreach add_file $add_verilog_files {
  myinfo "Compiling File $add_file"
  myexec vlog $add_file
}
 
foreach add_file $add_vhdl_files {
  myinfo "Compiling File $add_file"
  myexec vcom $add_file
}
 
myinfo "Running Testbench"
 
# Finally we get to Run the Testbench
eval "myexec vsim +nowarnTSCALE +nowarnTFMPC +nowarnTOFD -c $includ_str -l run_modelsim.log -do \"run -all; quit\" $model_tb"
 
myinfo "Testbench Completed"
 
# Extract Testbench Exit Status from Log File
if {[catch {open "run_modelsim.log" "r"} log_input]} {
  myerror "Could not Open File run_modelsim.log for reading\n"
} else {
  while {[gets $log_input next_line] >= 0} {
    if {[string match -nocase "*Exit status for testbench*" $next_line]} {
      set next_line [string replace $next_line 0 5]
      myinfo "$next_line"
    }
  }
}
 
close $log_input
 
myinfo "Check run_modelsim.log for more Details"
 
exit

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Subversion Repositories sgmii

[/] [sgmii/] [trunk/] [src/] [mAltGX/] [mAlt8b10benc_run_modelsim.tcl] - Blame information for rev 13

Line No.	Rev	Author	Line
1	13	jefflieu	`#!/usr/bin/env tcl`
2			`######################################################################`
3			`#`
4			`# Synopsis:`
5			`# tcl run_modelsim.tcl [-option value]* (Unix Systems)`
6			`# vish run_modelsim.tcl [-option value]* (Any Command Line)`
7			`# do run_modelsim.tcl [-option value]* (Modelsim GUI)`
8			`#`
9			`# Options:`
10			`# -gate <device_family>`
11			`# Forces Script to run Gate Level Simulation with <device_family>`
12			`# Simulation Model must have been compiled using quartus_eda`
13			`# -tbfile <testbench[.v\|.vhd]>`
14			`# Specifies Testbench File Name`
15			`# -tbmod <testbench_module_name>`
16			`# Specifies Testbench Module Name`
17			`# -simfile <simulation_model[.vo\|.vho]>`
18			`# Specifies IP Functional Simulation Model File Name`
19			`#`
20			`# Usage:`
21			`# *The Filename for this script must be have a .tcl extension`
22			`# To run a testbench specify the testbench file, the simulation`
23			`# model file (.vo or .vho), and the testbench module name.`
24			`# This can be done by either editing the DEFAULTS SECTION given`
25			`# below or by means of command line arguments.`
26			`# *This script uses the file name of the simulation model to determine`
27			`# whether to run either a verilog (.vo) or vhdl (.vho) simulation.`
28			`# If there are additional Verilog or VHDL files that need to be`
29			`# compiled they can be specified under their respective lists in the`
30			`# DEFAULTS SECTION (Reminder: you can use '\' for line continuation)`
31			`# *The script defaults to running simgen simulations.`
32			`# To run a Gate Level Simulation you must use the '-gate' option.`
33			`# Libraries for the respective device families must be supplied`
34			`# in the QUARTUS LIBRARIES SECTION (See Below).`
35			`#`
36			`# Prerequisistes:`
37			`# This script is assumes that the user successfully ran IPToolBench`
38			`# and has all the necessary files (.vo, .iv. etc.) in the folder`
39			`# In the case of a Gate Level Simulation the '.vo'/'.vho' file must`
40			`# have been previously compiled using quartus_eda and the device family`
41			`# specified by '-gate' should match the device family with which the`
42			`# Simulation Model was compiled with. A version of Modelsim compatible`
43			`# with the simulation file must also be available and the path to the`
44			`# Modelsim commands must be included in the PATH environment variable.`
45			`# Ideally you should run this script using 'vish' in the command line.`
46			`# The script can also be executed using the Modelsim GUI using`
47			`# 'do run_modelsim.tcl'. You cannot execute the script if`
48			`# QUARTUS_ROOTDIR Environment Variable is not set to a valid`
49			`# Quartus II Installation.`
50			`#`
51			`# Simulator Output:`
52			`# run_modelsim.log`
53			`#`
54			`# Device Family Libraries supported in Current Version:`
55			`# stratix, stratixii, stratixgx, stratixiigx, cyclone, cycloneii,`
56			`# apexii, apex20ke, apex20kc, cycloneii, hardcopyii`
57			`#`
58			`########################################################################`
59
60			`########################################################################`
61			`# DEFAULTS SECTION #`
62			`########################################################################`
63			`# Edit these Variables to match your required Testbench Settings #`
64
65			`# Default Device Family`
66			`# e.g. "stratixii"`
67			`set def_device_fam "stingray"`
68			`# Default Testbench File`
69			`# e.g. "rio_c_8_32_4_tb.v"`
70			`set def_test_bench "mAlt8b10benc_tb.v"`
71			`# Default Model Language`
72			`# e.g. "verilog"`
73			`set def_model_lang "verilog"`
74			`# Default Simgen/Gate Level Model Filename`
75			`# e.g. rio_c_8_32_4.vo or rio_c_8_32_4.vho`
76			`set def_model_file "mAlt8b10benc.vo"`
77			`# Default Testbench Modelsim Module`
78			`# Usually this is set to 'tb' or something like 'slite_tb'`
79			`set def_model_tb "tb"`
80			`# List of Additional Verilog Files to be Compiled`
81			`# e.g. {sii_clk_gen.v sii_av_master.v sii_reset.v}`
82			`set add_verilog_files {}`
83			`# List of Additional VHDL Files to be Compiled`
84			`# e.g. {sii_clk_gen.vhd sii_clk_gen_components.vhd}`
85			`set add_vhdl_files {}`
86
87			`if {[catch {vsim -version} ]} {`
88			`set shell 1`
89			`} else {`
90			`set shell 0`
91			`}`
92
93			`# Procedure to display Info Messages`
94			`proc myinfo { args } {`
95			`global shell`
96			`foreach mesg $args {`
97			`if {$shell} {`
98			`puts stdout "\# Info: $mesg"`
99			`} else {`
100			`puts "\# Info: $mesg"`
101			`}`
102			`}`
103			`}`
104
105			`# Procedure to display Error Messages and exit the script`
106			`proc myerror { args } {`
107			`global shell`
108			`foreach mesg $args {`
109			`if {$shell} {`
110			`puts stderr "\# Error: $mesg"`
111			`} else {`
112			`puts "\# Error: $mesg"`
113			`}`
114			`}`
115			`if {$shell} {`
116			`exit`
117			`} else {`
118			`error "Terminating script"`
119			`}`
120			`}`
121
122			`# Procedure to run an external command (such as vsim)`
123			`proc myexec { args } {`
124			`global shell`
125			`if {$shell} {`
126			`eval "exec $args"`
127			`} else {`
128			`eval $args`
129			`}`
130			`}`
131
132			`########################################################################`
133			`# END DEFAULTS SECTION #`
134			`########################################################################`
135			`# Get Command Line Arguments`
136			`# Gate Level Simulation must be specified along with a device family name`
137			`if {[info exists device_fam]} {`
138			`unset device_fam`
139			`}`
140			`if {[info exists testbench]} {`
141			`unset testbench`
142			`}`
143			`if {[info exists model_tb]} {`
144			`unset model_tb`
145			`}`
146			`if {[info exists model_file]} {`
147			`unset model_file`
148			`}`
149
150			`foreach arg $argv {`
151			`if {[info exists next_val]} {`
152			`set $next_val $arg`
153			`unset next_val`
154			`} else {`
155			`if {[string match -nocase "-gate" $arg]} {`
156			`set next_val "device_fam";`
157			`} elseif {[string match -nocase "-tbfile" $arg]} {`
158			`set next_val "testbench"`
159			`} elseif {[string match -nocase "-tbmod" $arg]} {`
160			`set next_val "model_tb"`
161			`} elseif {[string match -nocase "-simfile" $arg]} {`
162			`set next_val "model_file"`
163			`} elseif {[string match -nocase "-gui" $arg]} {`
164			`myinfo "Testbench is run in GUI mode"`
165			`} else {`
166			`myerror "Invalid Argument Specified: $arg\n"`
167			`}`
168			`}`
169			`}`
170
171			`if {![info exists device_fam]} {`
172			`set device_fam $def_device_fam`
173			`}`
174			`if {![info exists testbench]} {`
175			`set testbench $def_test_bench`
176			`}`
177			`if {![info exists model_tb]} {`
178			`set model_tb $def_model_tb`
179			`}`
180			`if {![info exists model_file]} {`
181			`set model_file $def_model_file`
182			`}`
183
184			`# Check to make sure script is being run in the correct directory`
185			`if {![file exists $testbench]} {`
186			`if {[file exists tb.v]} {`
187			`file copy tb.v $testbench`
188			`} else {`
189			`set mesg1 "Testbench File not Found.\n"`
190			`set mesg2 "Please run from the testbench directory\n"`
191			`myerror $mesg1 $mesg2`
192			`}`
193			`}`
194
195			`# Identify Simulation Type through Filename`
196			`if {[string match -nocase "*.vo" $model_file]} {`
197			`set model_file [string trimright $model_file "vo"]`
198			`set model_file [string trimright $model_file "."]`
199			`set f_ext ".vo"`
200			`set exec_com "vlog"`
201			`set exec_arg1 "-hazards"`
202			`set exec_arg2 "-work"`
203			`} elseif {[string match -nocase "*.vho" $model_file]} {`
204			`set model_file [string trimright $model_file "vho"]`
205			`set model_file [string trimright $model_file "."]`
206			`set f_ext ".vho"`
207			`set exec_com "vcom"`
208			`set exec_arg1 "-93"`
209			`set exec_arg2 "-work"`
210			`} else {`
211			`myerror "Unrecognized File Extension for $model_file\n"`
212			`}`
213
214			`# Check for presence of IP functional simulation model`
215			`if {![file exists ${model_file}${f_ext}]} {`
216			`set mesg1 "Can't find Verilog IP Functional Simulation Model."`
217			`set mesg2 "Make sure it is created before attempting to run this script."`
218			`myerror $mesg1 $mesg2`
219			`}`
220
221			`# Get Location of Quartus Libraries`
222			`global env`
223
224			`if {[info exists env(QUARTUS_ROOTDIR)]} {`
225			`set lib_path "$env(QUARTUS_ROOTDIR)/eda/sim_lib/"`
226			`} else {`
227			`myerror "Can't find QUARTUS II\n"`
228			`}`
229
230			`########################################################################`
231			`# QUARTUS LIBRARIES SECTION #`
232			`########################################################################`
233			`# Edit this section to add support for additional device families #`
234
235			`# Library Information for Modelsim`
236			`# ORDER OF FILES IS IMPORTANT`
237			`# $libraries: A list with library names`
238			`# $lib_files: A nested list of library files for items in $libraries`
239			`# Files must be located in $QUARTUS_ROOTDIR/eda/sim_libs/`
240			`if {$f_ext == ".vo"} {`
241			`# Default Simgen Libraries`
242			`set libraries {lpm altera_mf sgate }`
243			`set lib_files {{220model.v} {altera_mf.v} {sgate.v} }`
244			`} else {`
245			`# Default Simgen Libraries`
246			`set libraries {lpm altera_mf sgate }`
247			`set lib_files {{220pack.vhd 220model.vhd } \`
248			`{altera_mf_components.vhd altera_mf.vhd } \`
249			`{sgate_pack.vhd sgate.vhd} }`
250			`}`
251
252			`########################################################################`
253			`# END QUARTUS LIBRARIES SECTION #`
254			`########################################################################`
255
256			`# Remove modelsim.ini`
257			`if {[file exists modelsim.ini]} {`
258			`myinfo "Removing modelsim.ini"`
259			`file delete -force modelsim.ini`
260			`}`
261
262			`set includ_str ""`
263			`# Check if we are running a version of ModelSim Altera Edition`
264			`set version [myexec vsim -version]`
265			`if {[string match -nocase "ALTERA" $version]} {`
266			`# Verilog Libraries have a '_ver' appended`
267			`if {$f_ext == ".vo"} {`
268			`set ver_addon "_ver"`
269			`} else {`
270			`set ver_addon ""`
271			`}`
272			`# Map Precompiled Libraries to current Project`
273			`foreach lib_dir $libraries {`
274			`myinfo "Including Library ${lib_dir}${ver_addon}"`
275			`append includ_str " -L ${lib_dir}${ver_addon}"`
276			`}`
277			`} else {`
278			`# If we aren't running an Altera Edition of Modelsim,`
279			`# take information from $libraries and $lib_files`
280			`# to compile the Modelsim libraries for Simulation`
281			`set lib_count 0`
282			`foreach lib_dir $libraries {`
283			`if {[file isdirectory $lib_dir]} {`
284			`myinfo "Cleaning ${lib_dir} Directory"`
285			`file delete -force $lib_dir`
286			`}`
287			`myinfo "Compiling Library ${lib_dir}"`
288			`myexec vlib $lib_dir`
289			`foreach lib_file [lindex $lib_files $lib_count] {`
290			`myexec $exec_com $exec_arg1 $exec_arg2 $lib_dir ${lib_path}${lib_file}`
291			`}`
292			`set lib_count [expr $lib_count+1]`
293			`append includ_str " -L $lib_dir"`
294			`}`
295			`}`
296
297			`# Compile Simulation Model`
298			`if {[file isdirectory $model_file]} {`
299			`myinfo "Cleaning ${model_file} Directory"`
300			`file delete -force $model_file`
301			`}`
302			`myinfo "Compiling Model $model_file"`
303			`myexec vlib $model_file`
304			`myexec $exec_com $exec_arg2 $model_file ${model_file}${f_ext}`
305			`append includ_str " -L $model_file"`
306
307			`# Clean work Directory`
308			`if {[file isdirectory work]} {`
309			`myinfo "Cleaning work Directory"`
310			`file delete -force work`
311			`}`
312			`myexec vlib work`
313			`myexec vmap work`
314
315			`# Compile Testbench`
316
317			`myinfo "Compiling Testbench $testbench"`
318			`if {[string match -nocase "*.v" $testbench]} {`
319			`myexec vlog -hazards -work work $testbench`
320			`} elseif {[string match -nocase "*.vhd" $testbench]} {`
321			`vcom -93 -work work $testbench`
322			`} else {`
323			`myerror "Unrecognized Testbench File Extension\n"`
324			`}`
325
326			`# Compile Extra Files if specified`
327
328			`foreach add_file $add_verilog_files {`
329			`myinfo "Compiling File $add_file"`
330			`myexec vlog $add_file`
331			`}`
332
333			`foreach add_file $add_vhdl_files {`
334			`myinfo "Compiling File $add_file"`
335			`myexec vcom $add_file`
336			`}`
337
338			`myinfo "Running Testbench"`
339
340			`# Finally we get to Run the Testbench`
341			`eval "myexec vsim +nowarnTSCALE +nowarnTFMPC +nowarnTOFD -c $includ_str -l run_modelsim.log -do \"run -all; quit\" $model_tb"`
342
343			`myinfo "Testbench Completed"`
344
345			`# Extract Testbench Exit Status from Log File`
346			`if {[catch {open "run_modelsim.log" "r"} log_input]} {`
347			`myerror "Could not Open File run_modelsim.log for reading\n"`
348			`} else {`
349			`while {[gets $log_input next_line] >= 0} {`
350			`if {[string match -nocase "Exit status for testbench" $next_line]} {`
351			`set next_line [string replace $next_line 0 5]`
352			`myinfo "$next_line"`
353			`}`
354			`}`
355			`}`
356
357			`close $log_input`
358
359			`myinfo "Check run_modelsim.log for more Details"`
360
361			`exit`