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[/] [sgmii/] [trunk/] [src/] [mAltGX/] [mAlt8b10benc_tb.v] - Blame information for rev 13

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1 13 jefflieu 
`define NO_PLI
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`timescale 1ns / 1ns
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module tb;
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initial begin
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  $display("***********************************************************");
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  $display("title:  tb.demo_enc");
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  $display("desc:   demonstration testbench");
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  $display("        (c) Altera Inc. ALL RIGHTS RESERVED           ");
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  $display("        www.altera.com                                ");
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  $display("***********************************************************");
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  $display("PURPOSE: Demonstrate basic function and provide hookup example.");
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  $display("PURPOSE: Note: no error checking is performed.");
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  $display("METHOD:  A generator emits several random data and control values.");
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  $display("***********************************************************");
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end
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/**********************************************************************/
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// DEFINES AND INCLUDES
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/**********************************************************************/
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`define TBID "tb.demo_enc"
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reg  clk;
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reg  reset_n;
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reg  enc_idle_ins;
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reg  enc_kin;
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reg  enc_enable;
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reg [7:0] enc_datain;
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reg  enc_rdin;
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reg  enc_rdforce;
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wire  enc_kerr;
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wire [9:0] enc_dataout;
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wire  enc_valid;
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wire  enc_rdout;
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wire  enc_rdcascade;
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mAlt8b10benc mAlt8b10benc(
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 .clk (clk) // input
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,.reset_n (reset_n) // input
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,.idle_ins (enc_idle_ins) // input
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,.kin (enc_kin) // input
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,.ena (enc_enable) // input
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,.datain (enc_datain) // input [7:0]
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,.rdin (enc_rdin) // input
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,.rdforce (enc_rdforce) // input
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,.kerr (enc_kerr) // output
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,.dataout (enc_dataout) // output [9:0]
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,.valid (enc_valid) // output
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,.rdout (enc_rdout) // output
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,.rdcascade (enc_rdcascade) // output
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);
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initial begin
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        enc_enable = 1;
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        enc_rdforce = 0;
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        enc_rdin = 0;
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        enc_idle_ins = 0;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'b1_101_11100;
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        while (!reset_n) @(posedge clk);
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        repeat (5)
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                @(posedge clk) {enc_kin, enc_datain} <= 9'b1_101_11100;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h8;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h82;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'hb2;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'hb1;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'hc2;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h6a;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h7f;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h93;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'ha;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h6e;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h18;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'b1_100_11100;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'hfc;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h5;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h2c;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h9b;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'he2;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'hfe;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'hb;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'hcd;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h28;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h73;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h9;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'hd2;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h93;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h32;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'b1_101_11100;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'he9;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'hea;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h55;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'hde;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'hdb;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'b1_111_10111;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h24;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h11;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h67;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h96;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h52;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h47;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h42;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'b1_110_11100;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'hfa;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'hfc;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'hec;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h17;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'he3;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'b1_111_11110;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'b1_111_11101;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h5d;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'hd2;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h66;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'he1;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h56;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h56;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'b1_111_11100;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h2b;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h80;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'b1_011_11100;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h7c;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'ha7;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'hed;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'hc9;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h3a;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'b1_111_11111;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'ha0;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h12;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'heb;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h91;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h8d;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'hc;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h19;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h10;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'hb1;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h6c;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'b1_010_11100;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h65;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h80;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h8b;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h30;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h96;
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        $display("%0t insert idles", $time);
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        enc_idle_ins = 1; enc_enable <= 0;
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        repeat (4) @(posedge clk);
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        $display("%0t stop inserting idles", $time);
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        enc_enable <= 1;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h15;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h7c;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'b1_111_11011;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'hc2;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'hae;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h9c;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h13;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h0;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'b1_001_11100;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h57;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h4f;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h1f;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'hb7;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h73;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'hc1;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'had;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'hea;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'b1_000_1100;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h5a;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h71;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h6d;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'b1_000_11100;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h42;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h27;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h57;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h4d;
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        $display("%0t turn off enc_enable", $time);
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        enc_enable <= 0;
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        repeat (4) @(posedge clk);
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        $display("%0t turn on enc_enable", $time);
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        enc_enable <= 1;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h46;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h26;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'hae;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h9c;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h13;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h0;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'b1_001_11100;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h57;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h4f;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h1f;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'hb7;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'h73;
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        @(posedge clk) {enc_kin, enc_datain} <= 9'hf3;
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        $display("$$$ Exit status for testbench tb.demo_enc :  TESTBENCH_PASSED ");
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        $finish;
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end
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// clock generator (100 MHz)
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initial begin
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        clk <= 0;
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        forever begin
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                #10;
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                clk = !clk;
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        end
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end
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// reset task
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initial begin
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        reset_n <= 0;
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        repeat (10) @(posedge clk);
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        reset_n <= 1;
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end
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// logging task
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always @(posedge clk) begin
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        $display("%0t enc_enable = %b enc_datain = %x, enc_kin = %b, enc_dataout = %x",
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                $time, enc_enable, enc_datain, enc_kin, enc_dataout);
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end
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endmodule

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