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[/] [sgmii/] [trunk/] [src/] [mAltGX/] [mAltA5GXlvds.v] - Blame information for rev 17

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Line No. Rev Author Line
1 13 jefflieu
 
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module mAltA5GXlvds (
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        input   i_SerRx,
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        output  o_SerTx,
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        input   i_RefClk125M,
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        output  o_CoreClk,
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        input   i_GxBPwrDwn,
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        input   i_XcverDigitalRst,
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    output      o_PllLocked,
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        output o_SignalDetect,
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        output [7:0] o8_RxCodeGroup,
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        output  o_RxCodeInvalid,
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        output  o_RxCodeCtrl,
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        input   i_RxBitSlip,
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        input [7:0] i8_TxCodeGroup,
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        input   i_TxCodeValid,
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        input   i_TxCodeCtrl,
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        input   i_TxForceNegDisp,
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    output      o_RunningDisparity);
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        wire [9:0]       w10_txdata;
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        wire [9:0]       w10_rxdata;
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        wire [9:0]       w10_txdatalocal;
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        wire [9:0]       w10_rxdatalocal;
29 15 jefflieu
        wire w_RxKErr,w_RxRdErr;
30 16 jefflieu
        wire w_TxClk,w_RxClk;
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        wire w_BitSlip;
32 13 jefflieu
 
33 16 jefflieu
 
34 15 jefflieu
        mEnc8b10bMem u8b10bEnc(
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        .i8_Din                         (i8_TxCodeGroup),               //HGFEDCBA
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        .i_Kin                          (i_TxCodeCtrl),
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        .i_ForceDisparity       (i_TxForceNegDisp),
38 16 jefflieu
        .i_Disparity            (~i_TxForceNegDisp),    //1 is positive, 0 is negative
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        .o10_Dout                       (w10_txdata),                   //abcdeifghj
40 15 jefflieu
        .o_Rd                           (o_RunningDisparity),
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        .o_KErr                         (),
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        .i_Clk                          (w_RxClk),
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        .i_ARst_L                       (~i_XcverDigitalRst));
44 13 jefflieu
 
45 15 jefflieu
        mDec8b10bMem u8b10bDec(
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        .o8_Dout                        (o8_RxCodeGroup),               //HGFEDCBA
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        .o_Kout                         (o_RxCodeCtrl),
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        .o_DErr                         (),
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        .o_KErr                         (w_RxKErr),
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        .o_DpErr                        (w_RxRdErr),
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        .i_ForceDisparity       (1'b0),
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        .i_Disparity            (1'b0),
53 16 jefflieu
        .i10_Din                        (w10_rxdata),                   //abcdeifghj
54 15 jefflieu
        .o_Rd                           (),
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        .i_Clk                          (w_RxClk),
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        .i_ARst_L                       (~i_XcverDigitalRst));
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58 13 jefflieu
        assign o_RxCodeInvalid = w_RxKErr|w_RxRdErr;
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        assign o_SignalDetect = (~o_RxCodeInvalid)|o_RxCodeCtrl;
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        mAltArriaVlvdsRx ulvdsrx (
62 16 jefflieu
        .rx_cda_reset                   (w_RxCdaReset),
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        .rx_channel_data_align  (i_RxBitSlip),
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        .rx_in                                  (i_SerRx),
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        .rx_inclock                             (i_RefClk125M),
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        .rx_out                                 (w10_rxdata),
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        .rx_locked                              (o_PllLocked),
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        .rx_reset                               (w_RxReset),
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        .rx_divfwdclk                   (w_RxClk));
70 13 jefflieu
 
71 16 jefflieu
        /////////////////////////////////////////////////
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        //Hold In Reset Until Stable
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        /////////////////////////////////////////////////
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        reg [11:0] r12_LockCnt;
75 17 jefflieu
        always@(posedge w_RxClk or negedge o_PllLocked)
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                if((~o_PllLocked))
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                        r12_LockCnt<=12'h0;
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                else begin
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                        if(~(&r12_LockCnt))
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                                r12_LockCnt<=r12_LockCnt+12'h1;
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                end
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        assign w_RxReset        = ~r12_LockCnt[11];
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        assign w_RxCdaReset = (r12_LockCnt[11:10]==2'b11)?1'b0:1'b1;
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        reg [9:0] r10_txdata;
87 13 jefflieu
        mAltArriaVlvdsTx ulvdstx(
88 16 jefflieu
        .tx_in                  (r10_txdata),
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        .tx_inclock             (w_TxSerClk),
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        .tx_enable              (w_TxEnClk),
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        .tx_out                 (o_SerTx));
92 13 jefflieu
 
93 16 jefflieu
        mAltLvdsPll uAltTxPll(
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                .refclk         (w_RxClk),      // refclk.clk
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                .rst            (w_PorRst),     // reset.reset
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                .outclk_0       (w_TxSerClk),   // outclk0.clk
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                .outclk_1       (w_TxEnClk),    // outclk1.clk
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                .outclk_2       (w_TxClk),              // outclk2.clk
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                .locked         (w_TxLocked)    // locked.export
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        );
101 13 jefflieu
 
102 16 jefflieu
        always@(posedge w_TxClk)
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                r10_txdata <= w10_txdata;
104 13 jefflieu
 
105 16 jefflieu
        assign o_CoreClk = w_RxClk;
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        reg [7:0] r8_PorTmr;
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        assign w_PorRst = ~(&r8_PorTmr);
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        always@(posedge i_RefClk125M)
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        begin
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                if(w_PorRst)
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                        r8_PorTmr <= r8_PorTmr+8'h1;
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        end
114 13 jefflieu
 
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endmodule

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