OpenCores
URL https://opencores.org/ocsvn/sgmii/sgmii/trunk

Subversion Repositories sgmii

[/] [sgmii/] [trunk/] [src/] [mRateAdapter.v] - Blame information for rev 15

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 jefflieu 
/*
2 15 jefflieu 
        Copyright © 2012 JeffLieu-lieumychuong@gmail.com
3 
 
4 
        This file is part of SGMII-IP-Core.
5 
    SGMII-IP-Core is free software: you can redistribute it and/or modify
6 
    it under the terms of the GNU General Public License as published by
7 
    the Free Software Foundation, either version 3 of the License, or
8 
    (at your option) any later version.
9 
 
10 
    SGMII-IP-Core is distributed in the hope that it will be useful,
11 
    but WITHOUT ANY WARRANTY; without even the implied warranty of
12 
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 
    GNU General Public License for more details.
14 
 
15 
    You should have received a copy of the GNU General Public License
16 
    along with SGMII-IP-Core.  If not, see <http://www.gnu.org/licenses/>.
17 
 
18 2 jefflieu 
File            :
19 
Description     :
20 
Remarks         :
21 
Revision        :
22 
        Date    Author          Description
23 
02/09/12        Jefflieu
24 
*/
25 
module mRateAdapter(
26 
        //MAC Side signal
27 
        input   i_TxClk,
28 
        input   i_TxEN,
29 
        input   i_TxER,
30 
        input   [07:00] i8_TxD,
31 
 
32 
        input   i_RxClk,
33 
        output  o_RxEN,
34 
        output  o_RxER,
35 
        output  [07:00] o8_RxD,
36 
 
37 
        input   [1:0] i2_Speed,
38 
 
39 
        //SGMII PHY side
40 
        input   i_SamplingClk,
41 
        input   i_GClk,
42 
        output  o_TxEN,
43 
        output  o_TxER,
44 
        output  [07:00] o8_TxD,
45 
 
46 
        input   i_RxEN,
47 
        input   i_RxER,
48 
        input   [07:00] i8_RxD
49 
);
50 
 
51 
        wire w_TxActive;
52 
        reg r_TxActive;
53 
        reg r_GTxEN;
54 
        reg r_GTxER;
55 
        reg [07:00] r8_GByte;
56 
        reg [07:00] r8_Byte;
57 
        reg [03:00] r4_LowNib;
58 
        reg r_HighNib;
59 
        reg r_TxEN_D;
60 
        reg r_TxER_D;
61 
        reg r_Active;
62 
        wire w_TxSop;
63 
        wire w_TxEop;
64 
 
65 11 jefflieu 
        assign w_TxActive = i_TxEN | i_TxER;
66 
        assign w_TxSop = (~r_TxActive & w_TxActive);
67 
        assign w_TxEop = (r_TxActive & ~w_TxActive);
68 2 jefflieu 
 
69 
        always@(posedge i_TxClk)
70 
        begin
71 
                r_TxActive <= w_TxActive;
72 
 
73 
                r_HighNib <= (w_TxSop)?1'b1:(~r_HighNib);
74 
 
75 
                if(w_TxActive) begin
76 
                        if(r_HighNib) r8_Byte <= {i8_TxD[3:0],r4_LowNib};
77 
                        if(r_HighNib && (~w_TxSop)) r_TxEN_D <= i_TxEN;
78 
                        if(r_HighNib && (~w_TxSop)) r_TxER_D <= i_TxER;
79 11 jefflieu 
                end else if(r_HighNib)
80 2 jefflieu 
                         begin
81 
                         r_TxEN_D <= 1'b0;
82 
                         r_TxER_D <= 1'b0;
83 
                         end
84 
                if((~r_HighNib)|| (w_TxSop))
85 
                        r4_LowNib <= i8_TxD[3:0];
86 
 
87 
        end
88 
 
89 
        always@(posedge i_GClk)
90 
        begin
91 
                if(i_SamplingClk==1'b1) begin
92 
                        r8_GByte <= r8_Byte;
93 
                        r_GTxEN <= r_TxEN_D;
94 
                        r_GTxER <= r_TxER_D;
95 
                end
96 
        end
97 
 
98 
        assign o8_TxD = (i2_Speed==2'b10)?i8_TxD:r8_GByte;
99 
        assign o_TxEN = (i2_Speed==2'b10)?i_TxEN:r_GTxEN;
100 
        assign o_TxER = (i2_Speed==2'b10)?i_TxER:r_GTxER;
101 
 
102 
 
103 
        //Receive
104 
        //Receive Counter
105 
        wire w_RxActive;
106 
        reg r_RxActive;
107 
        reg [03:00] r4_Cntr;
108 
        wire w_RxSop;
109 
        wire w_RxEop;
110 
        reg [05:00] r6_GByte;
111 
        reg [05:00] r6_MByte;
112 
 
113 
        assign w_RxSop = (~r_RxActive & w_RxActive);
114 
 
115 
        assign w_RxActive = i_RxEN | i_RxER;
116 
 
117 
        always@(posedge i_GClk)
118 
        begin
119 
                r_RxActive <= w_RxActive;
120 
                if(w_RxSop) r4_Cntr<=4'h0;
121 
                else if(w_RxActive) r4_Cntr <= ((r4_Cntr==4'h9)?4'h0:(r4_Cntr+4'h1));
122 11 jefflieu 
                else r4_Cntr <= 4'h0;
123 
 
124 2 jefflieu 
                if(r4_Cntr==4'h0) r6_GByte <= {i_RxEN,i_RxER,i8_RxD[3:0]};
125 
                else if(r4_Cntr==4'h5) r6_GByte <= {i_RxEN,i_RxER,i8_RxD[7:4]};
126 
        end
127 
 
128 
        always@(posedge i_RxClk)
129 
        begin
130 
                r6_MByte <= r6_GByte;
131 
        end
132 
 
133 
 
134 
        assign o8_RxD = (i2_Speed==2'b10)?i8_RxD:{r6_MByte[3:0],r6_MByte[3:0]};
135 
        assign o_RxEN = (i2_Speed==2'b10)?i_RxEN:r6_MByte[5];
136 
        assign o_RxER = (i2_Speed==2'b10)?i_RxER:r6_MByte[4];
137 
 
138 
 
139 
 
140 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.