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[/] [sgmii/] [trunk/] [src/] [mReceive.v] - Blame information for rev 5

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/*
Developed By Subtleware Corporation Pte Ltd 2011
File            :
Description     :
Remarks         :
Revision        :
        Date    Author          Description
02/09/12        Jefflieu
*/
`include "SGMIIDefs.v"
 
module mReceive(
 
        input   [07:00] i8_RxCodeGroupIn,
        input   i_RxCodeInvalid,
        input   i_RxCodeCtrl,
        input   i_RxEven,
        input   i_IsComma,
        input   [02:00] i3_Xmit,
 
        input   i_OrderedSetValid,
        input   i_IsI1Set,
        input   i_IsI2Set,
        input   i_IsC1Set,
        input   i_IsC2Set,
        input   i_IsTSet,
        input   i_IsVSet,
        input   i_IsSSet,
        input   i_IsRSet,
 
        input   i_CheckEndKDK,
        input   i_CheckEndKD21_5D0_0,
        input   i_CheckEndKD2_2D0_0,
        input   i_CheckEndTRK,
        input   i_CheckEndTRR,
        input   i_CheckEndRRR,
        input   i_CheckEndRRK,
        input   i_CheckEndRRS,
 
 
        output  reg     [15:00] o16_RxConfigReg,
        output  o_RUDIConfig,
        output  o_RUDIIdle,
        output  o_RUDIInvalid,
 
        output  reg o_RxDV,
        output  reg o_RxER,
        output  reg [07:00] o8_RxD,
        output  reg o_Invalid,
        output  reg o_Receiving,
 
 
        input   i_Clk,
        input   i_ARst_L
);
 
localparam      stWAIT_FOR_K    = 21'h000001,
                        stRX_K                  = 21'h000002,
                        stRX_CB                 = 21'h000004,
                        stRX_CC                 = 21'h000008,
                        stRX_CD                 = 21'h000010,
                        stRX_INVALID    = 21'h000020,
                        stIDLE_D                = 21'h000040,
                        stCARRIER_DTEC  = 21'h000080,
                        stFALSE_CARRIER = 21'h000100,
                        stSTART_OF_PKT  = 21'h000200,
                        stRECEIVE               = 21'h000400,
                        stEARLY_END             = 21'h000800,
                        stTRI_RRI               = 21'h001000,
                        stTRR_EXTEND    = 21'h002000,
                        stEPD2_CHK_END  = 21'h004000,
                        stPKT_BURST_RRS = 21'h008000,
                        stRX_DATA_ERR   = 21'h010000,
                        stRX_DATA               = 21'h020000,
                        stEARLY_END_EXT = 21'h040000,
                        stEXT_ERROR             = 21'h080000,
                        stLINK_FAILED   = 21'h100000;
 
reg             [20:00] r21_State;
reg             [20:00] r21_NxtState;
 
wire    wSUDIK28_5;
wire    wSUDID21_5;
wire    wSUDID2_2;
wire    wCarrierDtect;//what is this
wire    wSUDI;
 
wire    w_IsC1Set;
wire    w_IsC2Set;
wire    w_IsI1Set;
wire    w_IsI2Set;
wire    w_IsRSet;
wire    w_IsSSet;
wire    w_IsTSet;
wire    w_IsVSet;
 
        //synthesis translate_off
        reg [8*30-1:0] rvStateName;
        always@(*)
        begin
                case(r21_State)
                stWAIT_FOR_K    :       rvStateName <= "Wait For K";
                stRX_K                  :       rvStateName <= "RX K";
                stRX_CB                 :       rvStateName <= "RX CB";
                stRX_CC                 :       rvStateName <= "RX CC";
                stRX_CD                 :       rvStateName <= "RX CD";
                stRX_INVALID    :       rvStateName <= "RX Invalid";
                stIDLE_D                :       rvStateName <= "IDLE D";
                stCARRIER_DTEC  :       rvStateName <= "CARRIER DETECT";
                stFALSE_CARRIER :       rvStateName <= "FALSE CARRIER";
                stSTART_OF_PKT  :       rvStateName <= "Start of Packet";
                stRECEIVE               :       rvStateName <= "Receiving";
                stEARLY_END             :       rvStateName <= "Early End";
                stTRI_RRI               :       rvStateName <= "TRI RRI";
                stTRR_EXTEND    :       rvStateName <= "TRR Extend";
                stEPD2_CHK_END  :       rvStateName <= "EPD2 Check End";
                stPKT_BURST_RRS :       rvStateName <= "PKT BURST RRS";
                stRX_DATA_ERR   :       rvStateName <= "RX DATA Error";
                stRX_DATA               :       rvStateName <= "RX DATA";
                stEARLY_END_EXT :       rvStateName <= "Early End Ext";
                stEXT_ERROR             :       rvStateName <= "Ext Error";
                stLINK_FAILED   :       rvStateName <= "Link Failed";
                endcase
                //$display("mReceive State: %s",rvStateName);
        end
        //synthesis translate_on
 
 
        assign w_IsSSet = i_OrderedSetValid && i_IsRSet;
        assign wSUDI    = ~i_RxCodeInvalid;
        assign wCarrierDtect = i_IsRSet|i_IsSSet|i_IsTSet|i_IsVSet;
 
        always@(posedge i_Clk or negedge i_ARst_L)
        if(i_ARst_L==1'b0) begin
                r21_State <= stWAIT_FOR_K;
        end else begin
                r21_State <= r21_NxtState;
        end
 
        assign wSUDIK28_5 = (!i_RxCodeInvalid) && (i_RxCodeCtrl) && (i8_RxCodeGroupIn==`K28_5);
        assign wSUDID21_5 = (!i_RxCodeInvalid) && (!i_RxCodeCtrl) && (i8_RxCodeGroupIn==`D21_5);
        assign wSUDID2_2 = (!i_RxCodeInvalid) && (!i_RxCodeCtrl) && (i8_RxCodeGroupIn==`D2_2);
        always@(*)
        begin
                case(r21_State)
                stWAIT_FOR_K: if(i_IsComma && i_RxEven) r21_NxtState <= stRX_K; else r21_NxtState<=stWAIT_FOR_K;
                stRX_K          : if(wSUDID21_5||wSUDID2_2)
                                                r21_NxtState <= stRX_CB; else
                                                if((!i_RxCodeInvalid) && (i_RxCodeCtrl) && i3_Xmit!=`cXmitDATA)
                                                r21_NxtState <= stRX_INVALID; else
                                                        if(((!i_RxCodeInvalid) && (!i_RxCodeCtrl) && i3_Xmit!=`cXmitDATA && i8_RxCodeGroupIn!=`D21_5 && i8_RxCodeGroupIn!=`D2_2)||
                                                                ((!i_RxCodeInvalid) && i3_Xmit==`cXmitDATA && ((i8_RxCodeGroupIn!=`D21_5 && i8_RxCodeGroupIn!=`D2_2 && (!i_RxCodeCtrl))||i_RxCodeCtrl)))
                                                                r21_NxtState <= stIDLE_D; else
                                                                r21_NxtState <= stRX_K;
                stRX_CB         :       if((!i_RxCodeInvalid) && (!i_RxCodeCtrl)) r21_NxtState <= stRX_CC; else r21_NxtState <= stRX_INVALID;
                stRX_CC         :       if((!i_RxCodeInvalid) && (!i_RxCodeCtrl)) r21_NxtState <= stRX_CD; else r21_NxtState <= stRX_INVALID;
                stRX_CD         :       if((!i_RxCodeInvalid) && (i_RxCodeCtrl) && i8_RxCodeGroupIn==`K28_5 && i_RxEven)
                                                        r21_NxtState <= stRX_K;
                                                        else
                                                        r21_NxtState <= stRX_INVALID;
 
                stRX_INVALID:   if(wSUDIK28_5 && i_RxEven)
                                                        r21_NxtState <= stRX_K;
                                                        else
                                                        r21_NxtState <= stWAIT_FOR_K;
 
                stIDLE_D        :       if(!wSUDIK28_5 && (i3_Xmit!=`cXmitDATA))
                                                        r21_NxtState <= stRX_INVALID;
                                                else if(!i_RxCodeInvalid && i3_Xmit==`cXmitDATA && i_IsSSet)
                                                        r21_NxtState <= stSTART_OF_PKT;
                                                else if((!i_RxCodeInvalid && i3_Xmit==`cXmitDATA && (~wCarrierDtect)) || (wSUDIK28_5 && i_RxEven))
                                                        r21_NxtState <= stRX_K;
                                                else
                                                        r21_NxtState <= stFALSE_CARRIER;
 
                /*stCARRIER_DTEC: if(i_OrderedSetValid && i_IsSSet)
                                                        r21_NxtState <= stSTART_OF_PKT;
                                                else
                                                        r21_NxtState <= stFALSE_CARRIER;*/
                stFALSE_CARRIER : if(wSUDIK28_5 && i_RxEven) r21_NxtState <= stRX_K; else r21_NxtState <= stFALSE_CARRIER;
 
                stSTART_OF_PKT  : if(wSUDI)
                                                        begin
                                                                if(~i_RxCodeCtrl) r21_NxtState <= stRX_DATA; else
                                                                if((i_CheckEndKDK||i_CheckEndKD21_5D0_0||i_CheckEndKD2_2D0_0) &&i_RxEven)
                                                                        r21_NxtState <= stEARLY_END; else
                                                                if(i_CheckEndTRK && i_RxEven) r21_NxtState <= stTRI_RRI; else
                                                                if(i_CheckEndTRR) r21_NxtState <= stTRR_EXTEND; else
                                                                if(i_CheckEndRRR) r21_NxtState <= stEARLY_END_EXT; else
                                                                r21_NxtState <= stRX_DATA_ERR;
                                                        end
                                                  else r21_NxtState <= stRX_DATA_ERR;
                //stRECEIVE             : //zero cycle state
                stRX_DATA               : if(wSUDI)
                                                        begin
                                                                if(~i_RxCodeCtrl) r21_NxtState <= stRX_DATA; else
                                                                if((i_CheckEndKDK||i_CheckEndKD21_5D0_0||i_CheckEndKD2_2D0_0) &&i_RxEven)
                                                                        r21_NxtState <= stEARLY_END; else
                                                                if(i_CheckEndTRK && i_RxEven) r21_NxtState <= stTRI_RRI; else
                                                                if(i_CheckEndTRR) r21_NxtState <= stTRR_EXTEND; else
                                                                if(i_CheckEndRRR) r21_NxtState <= stEARLY_END_EXT; else
                                                                r21_NxtState <= stRX_DATA_ERR;
                                                        end
                                                  else r21_NxtState <= stRX_DATA_ERR;
                stRX_DATA_ERR   : if(wSUDI)
                                                        begin
                                                                if(~i_RxCodeCtrl) r21_NxtState <= stRX_DATA; else
                                                                if((i_CheckEndKDK||i_CheckEndKD21_5D0_0||i_CheckEndKD2_2D0_0) &&i_RxEven)
                                                                        r21_NxtState <= stEARLY_END; else
                                                                if(i_CheckEndTRK && i_RxEven) r21_NxtState <= stTRI_RRI; else
                                                                if(i_CheckEndTRR) r21_NxtState <= stTRR_EXTEND; else
                                                                if(i_CheckEndRRR) r21_NxtState <= stEARLY_END_EXT; else
                                                                r21_NxtState <= stRX_DATA_ERR;
                                                        end
                                                  else r21_NxtState <= stRX_DATA_ERR;
                stEARLY_END             : if(wSUDID21_5||wSUDID2_2) r21_NxtState <= stRX_CB; else r21_NxtState <= stIDLE_D;
                stTRI_RRI               : if(wSUDIK28_5) r21_NxtState <= stRX_K; else r21_NxtState <= stTRI_RRI;
                stTRR_EXTEND    : if(i_CheckEndRRR) r21_NxtState <= stTRR_EXTEND; else
                                                        if(i_CheckEndRRK && i_RxEven) r21_NxtState <= stTRI_RRI; else
                                                         if(i_CheckEndRRS) r21_NxtState <= stPKT_BURST_RRS; else
                                                          if(i_IsVSet) r21_NxtState <= stEXT_ERROR; else
                                                                r21_NxtState <= stTRR_EXTEND;
                stEARLY_END_EXT : if(i_CheckEndRRR) r21_NxtState <= stTRR_EXTEND; else
                                                        if(i_CheckEndRRK && i_RxEven) r21_NxtState <= stTRI_RRI; else
                                                         if(i_CheckEndRRS) r21_NxtState <= stPKT_BURST_RRS; else
                                                          if(i_IsVSet) r21_NxtState <= stEXT_ERROR; else
                                                                r21_NxtState <= stEARLY_END_EXT;
                //This is zero cycle state
                //stEPD2_CHK_END        : if(i_CheckEndRRR) r21_NxtState <= stTRR_EXTEND; else
                //                                      if(i_CheckEndRRK && i_RxEven) r21_NxtState <= stTRI_RRI; else
                //                                       if(i_CheckEndRRS) r21_NxtState <= stPKT_BURST_RRS; else
                //                                        r21_NxtState <= stEXT_ERROR; 
                stPKT_BURST_RRS : if(i_IsSSet && i_OrderedSetValid && wSUDI) r21_NxtState <= stSTART_OF_PKT; else r21_NxtState <= stPKT_BURST_RRS;
                stEXT_ERROR             : if(i_IsSSet && i_OrderedSetValid && wSUDI) r21_NxtState <= stSTART_OF_PKT; else
                                                        if(wSUDIK28_5 && i_RxEven) r21_NxtState <= stRX_K; else
                                                                if(i_CheckEndRRR) r21_NxtState <= stTRR_EXTEND; else
                                                                if(i_CheckEndRRK && i_RxEven) r21_NxtState <= stTRI_RRI; else
                                                                if(i_CheckEndRRS) r21_NxtState <= stPKT_BURST_RRS; else
                                                                r21_NxtState <= stEXT_ERROR;
                endcase
        end
 
        assign o_RUDIConfig = (r21_State==stRX_CD               )?1'b1:1'b0;
        assign o_RUDIIdle       = (r21_State==stIDLE_D          )?1'b1:1'b0;
        assign o_RUDIInvalid= (r21_State==stRX_INVALID && i3_Xmit==`cXmitCONFIG)?1'b1:1'b0;
 
        always@(posedge i_Clk or negedge i_ARst_L)
        if(i_ARst_L==1'b0) begin
                o_Receiving <= 1'b0;
                o_RxDV          <= 1'b0;
                o_RxER          <= 1'b0;
                o8_RxD          <= 8'h0;
                o16_RxConfigReg <= 16'h00;
        end else begin
 
                case(r21_NxtState)
                //stWAIT_FOR_K  :       
                stRX_K                  :       begin
                                                        o_Receiving <= 1'b0;
                                                        o_RxDV          <= 1'b0;
                                                        o_RxER          <= 1'b0;
                                                        end
                //stRX_CB                       :  
                stRX_CC                 :   o16_RxConfigReg[07:00] <= i8_RxCodeGroupIn;
                stRX_CD                 :       o16_RxConfigReg[15:08] <= i8_RxCodeGroupIn;
                stRX_INVALID    :       if(i3_Xmit==`cXmitDATA) o_Receiving <= 1'b1;
                stIDLE_D                :       begin
                                                        o_Receiving <= 1'b0;
                                                        o_RxDV          <= 1'b0;
                                                        o_RxER          <= 1'b0;
                                                        end
 
                //stCARRIER_DTEC:       o_Receiving <= 1'b1;
                stFALSE_CARRIER :       begin
                                                        o_RxER          <= 1'b1;
                                                        o8_RxD          <= 8'h0E;
                                                        end
                stSTART_OF_PKT  :       begin
                                                        o_Receiving <= 1'b1;
                                                        o_RxDV          <= 1'b1;
                                                        o_RxER          <= 1'b0;
                                                        o8_RxD          <= 8'h55;
                                                        end
                //stRECEIVE             :       
                stEARLY_END             :       o_RxER <= 1'b1;
                stTRI_RRI               :       begin
                                                        o_Receiving <= 1'b0;
                                                        o_RxER          <= 1'b0;
                                                        o_RxDV          <= 1'b0;
                                                        end
                stTRR_EXTEND    :       begin
                                                        o_RxER          <= 1'b1;
                                                        o_RxDV          <= 1'b0;
                                                        o8_RxD          <= 8'h0F;
                                                        end
                //stEPD2_CHK_END        :       
                stPKT_BURST_RRS :       begin
                                                        o_RxDV          <= 1'b0;
                                                        o8_RxD          <= 8'b0000_1111;
                                                        end
                stRX_DATA_ERR   :       o_RxER          <= 1'b1;
                stRX_DATA               :       begin
                                                        o_RxER          <= 1'b0;
                                                        o8_RxD          <= i8_RxCodeGroupIn;
                                                        end
                stEARLY_END_EXT :       o_RxER          <= 1'b1;
                stEXT_ERROR             :       begin
                                                        o_RxDV          <= 1'b0;
                                                        o8_RxD          <= 8'b0001_1111;
                                                        end
                stLINK_FAILED   :       begin
                                                        if(o_Receiving==1'b1)
                                                                begin
                                                                o_Receiving <= 1'b0;
                                                                o_RxER <= 1'b1;
                                                                end else
                                                                begin
                                                                o_RxDV <= 1'b0;
                                                                o_RxER <= 1'b0;
                                                                end
                                                        if(i3_Xmit!=`cXmitDATA)         o_Invalid <= 1'b1;
                                                        end
                endcase
        end
 
endmodule

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[/] [sgmii/] [trunk/] [src/] [mReceive.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	2	jefflieu	`/*`
2			`Developed By Subtleware Corporation Pte Ltd 2011`
3			`File :`
4			`Description :`
5			`Remarks :`
6			`Revision :`
7			`Date Author Description`
8			`02/09/12 Jefflieu`
9			`*/`
10			`include "SGMIIDefs.v"
11
12			`module mReceive(`
13
14			`input [07:00] i8_RxCodeGroupIn,`
15			`input i_RxCodeInvalid,`
16			`input i_RxCodeCtrl,`
17			`input i_RxEven,`
18			`input i_IsComma,`
19			`input [02:00] i3_Xmit,`
20
21			`input i_OrderedSetValid,`
22			`input i_IsI1Set,`
23			`input i_IsI2Set,`
24			`input i_IsC1Set,`
25			`input i_IsC2Set,`
26			`input i_IsTSet,`
27			`input i_IsVSet,`
28			`input i_IsSSet,`
29			`input i_IsRSet,`
30
31			`input i_CheckEndKDK,`
32			`input i_CheckEndKD21_5D0_0,`
33			`input i_CheckEndKD2_2D0_0,`
34			`input i_CheckEndTRK,`
35			`input i_CheckEndTRR,`
36			`input i_CheckEndRRR,`
37			`input i_CheckEndRRK,`
38			`input i_CheckEndRRS,`
39
40
41			`output reg [15:00] o16_RxConfigReg,`
42			`output o_RUDIConfig,`
43			`output o_RUDIIdle,`
44			`output o_RUDIInvalid,`
45
46			`output reg o_RxDV,`
47			`output reg o_RxER,`
48			`output reg [07:00] o8_RxD,`
49			`output reg o_Invalid,`
50			`output reg o_Receiving,`
51
52
53			`input i_Clk,`
54			`input i_ARst_L`
55			`);`
56
57			`localparam stWAIT_FOR_K = 21'h000001,`
58			`stRX_K = 21'h000002,`
59			`stRX_CB = 21'h000004,`
60			`stRX_CC = 21'h000008,`
61			`stRX_CD = 21'h000010,`
62			`stRX_INVALID = 21'h000020,`
63			`stIDLE_D = 21'h000040,`
64			`stCARRIER_DTEC = 21'h000080,`
65			`stFALSE_CARRIER = 21'h000100,`
66			`stSTART_OF_PKT = 21'h000200,`
67			`stRECEIVE = 21'h000400,`
68			`stEARLY_END = 21'h000800,`
69			`stTRI_RRI = 21'h001000,`
70			`stTRR_EXTEND = 21'h002000,`
71			`stEPD2_CHK_END = 21'h004000,`
72			`stPKT_BURST_RRS = 21'h008000,`
73			`stRX_DATA_ERR = 21'h010000,`
74			`stRX_DATA = 21'h020000,`
75			`stEARLY_END_EXT = 21'h040000,`
76			`stEXT_ERROR = 21'h080000,`
77			`stLINK_FAILED = 21'h100000;`
78
79			`reg [20:00] r21_State;`
80			`reg [20:00] r21_NxtState;`
81
82			`wire wSUDIK28_5;`
83			`wire wSUDID21_5;`
84			`wire wSUDID2_2;`
85			`wire wCarrierDtect;//what is this`
86			`wire wSUDI;`
87
88			`wire w_IsC1Set;`
89			`wire w_IsC2Set;`
90			`wire w_IsI1Set;`
91			`wire w_IsI2Set;`
92			`wire w_IsRSet;`
93			`wire w_IsSSet;`
94			`wire w_IsTSet;`
95			`wire w_IsVSet;`
96
97			`//synthesis translate_off`
98			`reg [8*30-1:0] rvStateName;`
99			`always@(*)`
100			`begin`
101			`case(r21_State)`
102			`stWAIT_FOR_K : rvStateName <= "Wait For K";`
103			`stRX_K : rvStateName <= "RX K";`
104			`stRX_CB : rvStateName <= "RX CB";`
105			`stRX_CC : rvStateName <= "RX CC";`
106			`stRX_CD : rvStateName <= "RX CD";`
107			`stRX_INVALID : rvStateName <= "RX Invalid";`
108			`stIDLE_D : rvStateName <= "IDLE D";`
109			`stCARRIER_DTEC : rvStateName <= "CARRIER DETECT";`
110			`stFALSE_CARRIER : rvStateName <= "FALSE CARRIER";`
111			`stSTART_OF_PKT : rvStateName <= "Start of Packet";`
112			`stRECEIVE : rvStateName <= "Receiving";`
113			`stEARLY_END : rvStateName <= "Early End";`
114			`stTRI_RRI : rvStateName <= "TRI RRI";`
115			`stTRR_EXTEND : rvStateName <= "TRR Extend";`
116			`stEPD2_CHK_END : rvStateName <= "EPD2 Check End";`
117			`stPKT_BURST_RRS : rvStateName <= "PKT BURST RRS";`
118			`stRX_DATA_ERR : rvStateName <= "RX DATA Error";`
119			`stRX_DATA : rvStateName <= "RX DATA";`
120			`stEARLY_END_EXT : rvStateName <= "Early End Ext";`
121			`stEXT_ERROR : rvStateName <= "Ext Error";`
122			`stLINK_FAILED : rvStateName <= "Link Failed";`
123			`endcase`
124			`//$display("mReceive State: %s",rvStateName);`
125			`end`
126			`//synthesis translate_on`
127
128
129			`assign w_IsSSet = i_OrderedSetValid && i_IsRSet;`
130			`assign wSUDI = ~i_RxCodeInvalid;`
131			`assign wCarrierDtect = i_IsRSet\|i_IsSSet\|i_IsTSet\|i_IsVSet;`
132
133			`always@(posedge i_Clk or negedge i_ARst_L)`
134			`if(i_ARst_L==1'b0) begin`
135			`r21_State <= stWAIT_FOR_K;`
136			`end else begin`
137			`r21_State <= r21_NxtState;`
138			`end`
139
140			assign wSUDIK28_5 = (!i_RxCodeInvalid) && (i_RxCodeCtrl) && (i8_RxCodeGroupIn==`K28_5);
141			assign wSUDID21_5 = (!i_RxCodeInvalid) && (!i_RxCodeCtrl) && (i8_RxCodeGroupIn==`D21_5);
142			assign wSUDID2_2 = (!i_RxCodeInvalid) && (!i_RxCodeCtrl) && (i8_RxCodeGroupIn==`D2_2);
143			`always@(*)`
144			`begin`
145			`case(r21_State)`
146			`stWAIT_FOR_K: if(i_IsComma && i_RxEven) r21_NxtState <= stRX_K; else r21_NxtState<=stWAIT_FOR_K;`
147			`stRX_K : if(wSUDID21_5\|\|wSUDID2_2)`
148			`r21_NxtState <= stRX_CB; else`
149	5	jefflieu	if((!i_RxCodeInvalid) && (i_RxCodeCtrl) && i3_Xmit!=`cXmitDATA)
150	2	jefflieu	`r21_NxtState <= stRX_INVALID; else`
151			if(((!i_RxCodeInvalid) && (!i_RxCodeCtrl) && i3_Xmit!=`cXmitDATA && i8_RxCodeGroupIn!=`D21_5 && i8_RxCodeGroupIn!=`D2_2)\|\|
152			((!i_RxCodeInvalid) && i3_Xmit==`cXmitDATA && ((i8_RxCodeGroupIn!=`D21_5 && i8_RxCodeGroupIn!=`D2_2 && (!i_RxCodeCtrl))\|\|i_RxCodeCtrl)))
153			`r21_NxtState <= stIDLE_D; else`
154			`r21_NxtState <= stRX_K;`
155			`stRX_CB : if((!i_RxCodeInvalid) && (!i_RxCodeCtrl)) r21_NxtState <= stRX_CC; else r21_NxtState <= stRX_INVALID;`
156			`stRX_CC : if((!i_RxCodeInvalid) && (!i_RxCodeCtrl)) r21_NxtState <= stRX_CD; else r21_NxtState <= stRX_INVALID;`
157			stRX_CD : if((!i_RxCodeInvalid) && (i_RxCodeCtrl) && i8_RxCodeGroupIn==`K28_5 && i_RxEven)
158			`r21_NxtState <= stRX_K;`
159			`else`
160			`r21_NxtState <= stRX_INVALID;`
161
162			`stRX_INVALID: if(wSUDIK28_5 && i_RxEven)`
163			`r21_NxtState <= stRX_K;`
164			`else`
165			`r21_NxtState <= stWAIT_FOR_K;`
166
167			stIDLE_D : if(!wSUDIK28_5 && (i3_Xmit!=`cXmitDATA))
168			`r21_NxtState <= stRX_INVALID;`
169			else if(!i_RxCodeInvalid && i3_Xmit==`cXmitDATA && i_IsSSet)
170			`r21_NxtState <= stSTART_OF_PKT;`
171			else if((!i_RxCodeInvalid && i3_Xmit==`cXmitDATA && (~wCarrierDtect)) \|\| (wSUDIK28_5 && i_RxEven))
172			`r21_NxtState <= stRX_K;`
173			`else`
174			`r21_NxtState <= stFALSE_CARRIER;`
175
176			`/*stCARRIER_DTEC: if(i_OrderedSetValid && i_IsSSet)`
177			`r21_NxtState <= stSTART_OF_PKT;`
178			`else`
179			`r21_NxtState <= stFALSE_CARRIER;*/`
180			`stFALSE_CARRIER : if(wSUDIK28_5 && i_RxEven) r21_NxtState <= stRX_K; else r21_NxtState <= stFALSE_CARRIER;`
181
182			`stSTART_OF_PKT : if(wSUDI)`
183			`begin`
184			`if(~i_RxCodeCtrl) r21_NxtState <= stRX_DATA; else`
185			`if((i_CheckEndKDK\|\|i_CheckEndKD21_5D0_0\|\|i_CheckEndKD2_2D0_0) &&i_RxEven)`
186			`r21_NxtState <= stEARLY_END; else`
187			`if(i_CheckEndTRK && i_RxEven) r21_NxtState <= stTRI_RRI; else`
188			`if(i_CheckEndTRR) r21_NxtState <= stTRR_EXTEND; else`
189			`if(i_CheckEndRRR) r21_NxtState <= stEARLY_END_EXT; else`
190			`r21_NxtState <= stRX_DATA_ERR;`
191			`end`
192			`else r21_NxtState <= stRX_DATA_ERR;`
193			`//stRECEIVE : //zero cycle state`
194			`stRX_DATA : if(wSUDI)`
195			`begin`
196			`if(~i_RxCodeCtrl) r21_NxtState <= stRX_DATA; else`
197			`if((i_CheckEndKDK\|\|i_CheckEndKD21_5D0_0\|\|i_CheckEndKD2_2D0_0) &&i_RxEven)`
198			`r21_NxtState <= stEARLY_END; else`
199			`if(i_CheckEndTRK && i_RxEven) r21_NxtState <= stTRI_RRI; else`
200			`if(i_CheckEndTRR) r21_NxtState <= stTRR_EXTEND; else`
201			`if(i_CheckEndRRR) r21_NxtState <= stEARLY_END_EXT; else`
202			`r21_NxtState <= stRX_DATA_ERR;`
203			`end`
204			`else r21_NxtState <= stRX_DATA_ERR;`
205			`stRX_DATA_ERR : if(wSUDI)`
206			`begin`
207			`if(~i_RxCodeCtrl) r21_NxtState <= stRX_DATA; else`
208			`if((i_CheckEndKDK\|\|i_CheckEndKD21_5D0_0\|\|i_CheckEndKD2_2D0_0) &&i_RxEven)`
209			`r21_NxtState <= stEARLY_END; else`
210			`if(i_CheckEndTRK && i_RxEven) r21_NxtState <= stTRI_RRI; else`
211			`if(i_CheckEndTRR) r21_NxtState <= stTRR_EXTEND; else`
212			`if(i_CheckEndRRR) r21_NxtState <= stEARLY_END_EXT; else`
213			`r21_NxtState <= stRX_DATA_ERR;`
214			`end`
215			`else r21_NxtState <= stRX_DATA_ERR;`
216			`stEARLY_END : if(wSUDID21_5\|\|wSUDID2_2) r21_NxtState <= stRX_CB; else r21_NxtState <= stIDLE_D;`
217			`stTRI_RRI : if(wSUDIK28_5) r21_NxtState <= stRX_K; else r21_NxtState <= stTRI_RRI;`
218			`stTRR_EXTEND : if(i_CheckEndRRR) r21_NxtState <= stTRR_EXTEND; else`
219			`if(i_CheckEndRRK && i_RxEven) r21_NxtState <= stTRI_RRI; else`
220			`if(i_CheckEndRRS) r21_NxtState <= stPKT_BURST_RRS; else`
221			`if(i_IsVSet) r21_NxtState <= stEXT_ERROR; else`
222			`r21_NxtState <= stTRR_EXTEND;`
223			`stEARLY_END_EXT : if(i_CheckEndRRR) r21_NxtState <= stTRR_EXTEND; else`
224			`if(i_CheckEndRRK && i_RxEven) r21_NxtState <= stTRI_RRI; else`
225			`if(i_CheckEndRRS) r21_NxtState <= stPKT_BURST_RRS; else`
226			`if(i_IsVSet) r21_NxtState <= stEXT_ERROR; else`
227			`r21_NxtState <= stEARLY_END_EXT;`
228			`//This is zero cycle state`
229			`//stEPD2_CHK_END : if(i_CheckEndRRR) r21_NxtState <= stTRR_EXTEND; else`
230			`// if(i_CheckEndRRK && i_RxEven) r21_NxtState <= stTRI_RRI; else`
231			`// if(i_CheckEndRRS) r21_NxtState <= stPKT_BURST_RRS; else`
232			`// r21_NxtState <= stEXT_ERROR;`
233			`stPKT_BURST_RRS : if(i_IsSSet && i_OrderedSetValid && wSUDI) r21_NxtState <= stSTART_OF_PKT; else r21_NxtState <= stPKT_BURST_RRS;`
234			`stEXT_ERROR : if(i_IsSSet && i_OrderedSetValid && wSUDI) r21_NxtState <= stSTART_OF_PKT; else`
235			`if(wSUDIK28_5 && i_RxEven) r21_NxtState <= stRX_K; else`
236			`if(i_CheckEndRRR) r21_NxtState <= stTRR_EXTEND; else`
237			`if(i_CheckEndRRK && i_RxEven) r21_NxtState <= stTRI_RRI; else`
238			`if(i_CheckEndRRS) r21_NxtState <= stPKT_BURST_RRS; else`
239			`r21_NxtState <= stEXT_ERROR;`
240			`endcase`
241			`end`
242
243			`assign o_RUDIConfig = (r21_State==stRX_CD )?1'b1:1'b0;`
244			`assign o_RUDIIdle = (r21_State==stIDLE_D )?1'b1:1'b0;`
245			assign o_RUDIInvalid= (r21_State==stRX_INVALID && i3_Xmit==`cXmitCONFIG)?1'b1:1'b0;
246
247			`always@(posedge i_Clk or negedge i_ARst_L)`
248			`if(i_ARst_L==1'b0) begin`
249			`o_Receiving <= 1'b0;`
250			`o_RxDV <= 1'b0;`
251			`o_RxER <= 1'b0;`
252			`o8_RxD <= 8'h0;`
253			`o16_RxConfigReg <= 16'h00;`
254			`end else begin`
255
256			`case(r21_NxtState)`
257			`//stWAIT_FOR_K :`
258			`stRX_K : begin`
259			`o_Receiving <= 1'b0;`
260			`o_RxDV <= 1'b0;`
261			`o_RxER <= 1'b0;`
262			`end`
263			`//stRX_CB :`
264			`stRX_CC : o16_RxConfigReg[07:00] <= i8_RxCodeGroupIn;`
265			`stRX_CD : o16_RxConfigReg[15:08] <= i8_RxCodeGroupIn;`
266			stRX_INVALID : if(i3_Xmit==`cXmitDATA) o_Receiving <= 1'b1;
267			`stIDLE_D : begin`
268			`o_Receiving <= 1'b0;`
269			`o_RxDV <= 1'b0;`
270			`o_RxER <= 1'b0;`
271			`end`
272
273			`//stCARRIER_DTEC: o_Receiving <= 1'b1;`
274			`stFALSE_CARRIER : begin`
275			`o_RxER <= 1'b1;`
276			`o8_RxD <= 8'h0E;`
277			`end`
278			`stSTART_OF_PKT : begin`
279			`o_Receiving <= 1'b1;`
280			`o_RxDV <= 1'b1;`
281			`o_RxER <= 1'b0;`
282			`o8_RxD <= 8'h55;`
283			`end`
284			`//stRECEIVE :`
285			`stEARLY_END : o_RxER <= 1'b1;`
286			`stTRI_RRI : begin`
287			`o_Receiving <= 1'b0;`
288			`o_RxER <= 1'b0;`
289			`o_RxDV <= 1'b0;`
290			`end`
291			`stTRR_EXTEND : begin`
292			`o_RxER <= 1'b1;`
293			`o_RxDV <= 1'b0;`
294			`o8_RxD <= 8'h0F;`
295			`end`
296			`//stEPD2_CHK_END :`
297			`stPKT_BURST_RRS : begin`
298			`o_RxDV <= 1'b0;`
299			`o8_RxD <= 8'b0000_1111;`
300			`end`
301			`stRX_DATA_ERR : o_RxER <= 1'b1;`
302			`stRX_DATA : begin`
303			`o_RxER <= 1'b0;`
304			`o8_RxD <= i8_RxCodeGroupIn;`
305			`end`
306			`stEARLY_END_EXT : o_RxER <= 1'b1;`
307			`stEXT_ERROR : begin`
308			`o_RxDV <= 1'b0;`
309			`o8_RxD <= 8'b0001_1111;`
310			`end`
311			`stLINK_FAILED : begin`
312			`if(o_Receiving==1'b1)`
313			`begin`
314			`o_Receiving <= 1'b0;`
315			`o_RxER <= 1'b1;`
316			`end else`
317			`begin`
318			`o_RxDV <= 1'b0;`
319			`o_RxER <= 1'b0;`
320			`end`
321			if(i3_Xmit!=`cXmitDATA) o_Invalid <= 1'b1;
322			`end`
323			`endcase`
324			`end`
325
326			`endmodule`