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[/] [sgmii/] [trunk/] [src/] [mSGMII.v] - Blame information for rev 11

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/*
Developed By Jeff Lieu (lieumychuong@gmail.com)
File            :
Description     :
        This core implements:
        B1000-X Standard
        PCS/PMA of SGMII MAC Side
Remarks         :
Revision        :
        Date    Author          Description
02/09/12        Jefflieu
*/
 
`timescale 1ns/10ps
`include "SGMIIDefs.v"
 
module mSGMII
(
        //Tranceiver Interface
        input   i_SerRx,
        output  o_SerTx,
        input   i_CalClk,
        input   i_RefClk125M,
        input   i_ARstHardware_L,
 
        //Local BUS interface
        //Wishbonebus, single transaction mode (non-pipeline slave)
        input   i_Cyc,
        input   i_Stb,
        input   i_WEn,
        input   [31:00]         i32_WrData,
        input   [07:00]         iv_Addr,
        output  [31:00]         o32_RdData,
        output  o_Ack,
 
        input   i_Mdc,
        inout   io_Mdio,
 
        output  o_Linkup,
        output  o_ANDone,
        //This is used in Phy-Side SGMII 
        input   i_PhyLink,
        input   i_PhyDuplex,
        input   [1:0] i2_PhySpeed,
 
 
        output  [1:0] o2_SGMIISpeed,
        output  o_SGMIIDuplex,
 
        //GMII Interface
        input   [07:00] i8_TxD,
        input   i_TxEN,
        input   i_TxER,
        output  [07:00] o8_RxD,
        output  o_RxDV,
        output  o_RxER,
        output  o_GMIIClk,
        output  o_MIIClk,
        output  o_Col,
        output  o_Crs);
 
        wire    w_ClkSys;
        wire    w_Loopback;
        reg             r_RestartAN;
        wire    w_ANEnable;
        wire    [15:00] w16_Status;
        wire    w_MIIRst_L;
        wire    w_ANComplete;
 
        wire    [07:00] w8_RxCG_SyncToRxver;
        wire    w_RxCGInv_SyncToRxver;
        wire    w_RxCGCtrl_SyncToRxver;
        wire    w_SyncStatus,w_RxEven,w_IsComma,w_OSValid;
        wire    w_IsI1Set,w_IsI2Set,w_IsC1Set,w_IsC2Set,w_IsTSet,w_IsVSet,w_IsSSet,w_IsRSet;
 
        wire    w_Receiving;
        wire    w_Transmitting;
        wire    w_CheckEndKDK,w_CheckEndKD21_5D0_0,w_CheckEndKD2_2D0_0,w_CheckEndTRK,w_CheckEndTRR,w_CheckEndRRR,w_CheckEndRRK,w_CheckEndRRS;
        reg             r_CheckEndKDK,r_CheckEndKD21_5D0_0,r_CheckEndKD2_2D0_0,r_CheckEndTRK,r_CheckEndTRR,r_CheckEndRRR,r_CheckEndRRK,r_CheckEndRRS;
 
        wire    [2:0] w3_XmitState;
        wire    [16:01] w16_TxConfigReg;
        wire    [15:00] w16_RxConfigReg;
        wire    [15:00] w16_LcAdvAbility;
        wire    [15:00] w16_LpAdvAbility;
        wire    w_RUDIConfig;
        wire    w_RUDIIdle;
        wire    w_RUDIInvalid;
        wire    w_ARstLogic_L;
        wire    w_MIIReset_L;
        wire    w_ANRestart;
        //This delay stage is for the function checkend
        reg     [07:00] r8_RxCodeGroup[0:2];
        reg     r_RxCgInvalid[0:2];
        reg     r_RxCgCtrl[0:2];
        wire    [2:0] w3_PreCheckIsSSet;
        wire    [2:0] w3_PreCheckIsTSet;
        wire    [2:0] w3_PreCheckIsRSet;
        wire    [2:0] w3_PreCheckIsComma;
        wire    [2:0] w3_PreCheckIsD21_5;
        wire    [2:0] w3_PreCheckIsD2_2;
        wire    [2:0] w3_PreCheckIsD;
        wire    [2:0] w3_PreCheckIsD0_0;
        wire    w_GxBPowerDown;
        wire    w_TxCodeCtrl, w_TxCodeValid, w_RxCodeInvalid, w_RxCodeCtrl;
        wire    [07:00] w8_TxCode, w8_RxCode;
        wire    w_SignalDetect;
        wire    w_TxForceNegDisp;
        wire    w_PllLocked;
        wire    [20:00] w21_LinkTimer;
        wire    w_TxEN,w_TxER,w_RxER, w_RxDV;
        wire    [07:00] w8_RxD, w8_TxD;
 
        //MII Clock Gen
        reg [6:0]        r7_Cntr;
        reg r_MIIClk;
        reg r_MIIClk_D;
        wire w_SamplingClk;
 
        integer DELAY;
 
        assign o_Linkup = w_SyncStatus;
        assign o_ANDone = w_ANComplete;
 
        mRateAdapter    u0RateAdapter(
        //MAC Side signal
        .i_TxClk                (o_MIIClk),
        .i_TxEN                 (i_TxEN ),
        .i_TxER                 (i_TxER ),
        .i8_TxD                 (i8_TxD ),
        .i_RxClk                (o_MIIClk),
        .o_RxEN                 (o_RxDV),
        .o_RxER                 (o_RxER),
        .o8_RxD                 (o8_RxD),
        .i2_Speed               (o2_SGMIISpeed),
        //SGMII PHY side
        .i_SamplingClk  (w_SamplingClk),
        .i_GClk                 (w_ClkSys),
        .o_TxEN                 (w_TxEN),
        .o_TxER                 (w_TxER),
        .o8_TxD                 (w8_TxD),
        .i_RxEN                 (w_RxDV),
        .i_RxER                 (w_RxER),
        .i8_RxD                 (w8_RxD));
 
        generate
                genvar STAGE;
                for(STAGE=0;STAGE<3;STAGE=STAGE+1)
                begin
                        assign w3_PreCheckIsComma[STAGE]        = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b1 && r8_RxCodeGroup[STAGE]==`K28_5)?1'b1:1'b0;
                        assign w3_PreCheckIsTSet[STAGE]         = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b1 && r8_RxCodeGroup[STAGE]==`K29_7)?1'b1:1'b0;
                        assign w3_PreCheckIsRSet[STAGE]         = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b1 && r8_RxCodeGroup[STAGE]==`K23_7)?1'b1:1'b0;
                        assign w3_PreCheckIsD21_5[STAGE]        = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b0 && r8_RxCodeGroup[STAGE]==`D21_5)?1'b1:1'b0;
                        assign w3_PreCheckIsD2_2[STAGE]         = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b0 && r8_RxCodeGroup[STAGE]==`D2_2)?1'b1:1'b0;
                        assign w3_PreCheckIsD[STAGE]            = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b0)?1'b1:1'b0;
                        assign w3_PreCheckIsD0_0[STAGE]         = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b0 && r8_RxCodeGroup[STAGE]==`D0_0)?1'b1:1'b0;
                        assign w3_PreCheckIsSSet[STAGE]         = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b1 && r8_RxCodeGroup[STAGE]==`K27_7)?1'b1:1'b0;
                end
        endgenerate
 
        assign w_CheckEndKDK            = w3_PreCheckIsComma[2] & w3_PreCheckIsD[1]&w3_PreCheckIsComma[0];
        assign w_CheckEndRRR            = &(w3_PreCheckIsRSet);
        assign w_CheckEndTRK            = w3_PreCheckIsTSet[2] & w3_PreCheckIsRSet[1] & w3_PreCheckIsComma[0];
        assign w_CheckEndTRR            = w3_PreCheckIsTSet[2] & w3_PreCheckIsRSet[1] & w3_PreCheckIsRSet[0];
        assign w_CheckEndKD21_5D0_0     = w3_PreCheckIsComma[2] & w3_PreCheckIsD21_5[1] & w3_PreCheckIsD2_2[0];
        assign w_CheckEndKD2_2D0_0      = w3_PreCheckIsComma[2] & w3_PreCheckIsD2_2[1] & w3_PreCheckIsD2_2[0];
        assign w_CheckEndRRK            = w3_PreCheckIsRSet[2] & w3_PreCheckIsRSet[1] & w3_PreCheckIsComma[0];
        assign w_CheckEndRRS            = w3_PreCheckIsRSet[2] & w3_PreCheckIsRSet[1] & w3_PreCheckIsSSet[0];
 
        always@(posedge w_ClkSys)
                begin
                        r8_RxCodeGroup[0]        <= w8_RxCode;
                        r_RxCgCtrl[0]            <= w_RxCodeCtrl;
                        r_RxCgInvalid[0]         <= w_RxCodeInvalid;
                        for(DELAY=1;DELAY<3;DELAY=DELAY+1)
                                begin
                                r8_RxCodeGroup[DELAY]   <= r8_RxCodeGroup[DELAY-1];
                                r_RxCgInvalid[DELAY]    <= r_RxCgInvalid[DELAY-1];
                                r_RxCgCtrl[DELAY]               <= r_RxCgCtrl[DELAY-1];
                                end
                end
 
        assign o_Col = w_Transmitting & w_Receiving;
        assign o_Crs = 1'b0;
        assign w_ARstLogic_L    = w_PllLocked & i_ARstHardware_L & (w_MIIRst_L);
        mRegisters      u0Registers(
        .w_ARstLogic_L  (w_ARstLogic_L),
        .i_Clk                  (w_ClkSys),
        .i_Cyc                  (i_Cyc),
        .i_Stb                  (i_Stb),
        .i_WEn                  (i_WEn),
        .i8_Addr                (iv_Addr),
        .i32_WrData             (i32_WrData),
        .o32_RdData             (o32_RdData),
        .o_Ack                  (o_Ack),
        .o_Stall                (o_Stall),
 
        .io_Mdio                (io_Mdio),
        .i_Mdc                  (i_Mdc),
 
        //Register in and out,
 
        //MAC-Side SGMII
        .o2_SGMIISpeed          (o2_SGMIISpeed),
        .o_SGMIIDuplex          (o_SGMIIDuplex),
 
        //Phy-Side SGMII
        .i_PhyLink                      (i_PhyLink      ),
        .i_PhyDuplex            (i_PhyDuplex),
        .i2_PhySpeed            (i2_PhySpeed),
        .o21_LinkTimer          (w21_LinkTimer),
 
        .i16_TxConfigReg        (w16_TxConfigReg),
        .o_MIIRst_L                     (w_MIIRst_L),
        .o_ANEnable                     (w_ANEnable),
        .o_ANRestart            (w_ANRestart),
        .o_Loopback                     (w_Loopback),
        .o_GXBPowerDown         (w_GxBPowerDown),
        .o16_LcAdvAbility       (w16_LcAdvAbility),
        .i3_XmitState           (w3_XmitState),
        .i_SyncStatus           (w_SyncStatus),
        .i_ANComplete           (w_ANComplete),
        .i16_LpAdvAbility       (w16_LpAdvAbility));
 
         mSyncCtrl u0SyncCtrl(
        .i_Clk                          (w_ClkSys               ),
        .i_Cke                          ((~w_GxBPowerDown)      ),
        .i_ARst_L                       (w_ARstLogic_L  ),
        .i_CtrlLoopBack         (w_Loopback             ),
 
        .i8_RxCodeGroupIn       (r8_RxCodeGroup[2]      ),
        .i_RxCodeInvalid        (r_RxCgInvalid[2]       ),
        .i_RxCodeCtrl           (r_RxCgCtrl[2]          ),
        .i_SignalDetect         (w_SignalDetect         ),
 
        .o8_RxCodeGroupOut      (w8_RxCG_SyncToRxver    ),
        .o_RxCodeInvalid        (w_RxCGInv_SyncToRxver  ),
        .o_RxCodeCtrl           (w_RxCGCtrl_SyncToRxver ),
        .o_RxEven                       (w_RxEven                               ),
        .o_SyncStatus           (w_SyncStatus                   ),
        .o_BitSlip                      (),
        .o_IsComma                      (w_IsComma      ),
        .o_OrderedSetValid      (w_OSValid      ),
        .o_IsI1Set                      (w_IsI1Set      ),
        .o_IsI2Set                      (w_IsI2Set      ),
        .o_IsC1Set                      (w_IsC1Set      ),
        .o_IsC2Set                      (w_IsC2Set      ),
        .o_IsTSet                       (w_IsTSet       ),
        .o_IsVSet                       (w_IsVSet       ),
        .o_IsSSet                       (w_IsSSet       ),
        .o_IsRSet                       (w_IsRSet       ));
 
        always@(posedge w_ClkSys)
        begin
        r_CheckEndKDK                   <= w_CheckEndKDK;
        r_CheckEndKD21_5D0_0    <= w_CheckEndKD21_5D0_0;
        r_CheckEndKD2_2D0_0         <= w_CheckEndKD2_2D0_0;
        r_CheckEndTRK                   <= w_CheckEndTRK;
        r_CheckEndTRR                   <= w_CheckEndTRR;
        r_CheckEndRRR                   <= w_CheckEndRRR;
        r_CheckEndRRK                   <= w_CheckEndRRK;
        r_CheckEndRRS                   <= w_CheckEndRRS;
        end
 
        mReceive        u0Receive(
        .i8_RxCodeGroupIn               (w8_RxCG_SyncToRxver    ),
        .i_RxCodeInvalid        (w_RxCGInv_SyncToRxver  ),
        .i_RxCodeCtrl           (w_RxCGCtrl_SyncToRxver ),
        .i_RxEven                       (w_RxEven                               ),
 
        .i3_Xmit                                (w3_XmitState),
 
        .i_IsComma                              (w_IsComma      ),
        .i_OrderedSetValid      (w_OSValid      ),
        .i_IsI1Set              (w_IsI1Set      ),
        .i_IsI2Set              (w_IsI2Set      ),
        .i_IsC1Set              (w_IsC1Set      ),
        .i_IsC2Set              (w_IsC2Set      ),
        .i_IsTSet               (w_IsTSet       ),
        .i_IsVSet               (w_IsVSet       ),
        .i_IsSSet               (w_IsSSet       ),
        .i_IsRSet               (w_IsRSet       ),
 
        .i_CheckEndKDK                  (r_CheckEndKDK                  ),
        .i_CheckEndKD21_5D0_0   (r_CheckEndKD21_5D0_0   ),
        .i_CheckEndKD2_2D0_0    (r_CheckEndKD2_2D0_0    ),
        .i_CheckEndTRK                  (r_CheckEndTRK                  ),
        .i_CheckEndTRR                  (r_CheckEndTRR                  ),
        .i_CheckEndRRR                  (r_CheckEndRRR                  ),
        .i_CheckEndRRK                  (r_CheckEndRRK                  ),
        .i_CheckEndRRS                  (r_CheckEndRRS                  ),
 
        .o16_RxConfigReg        (w16_RxConfigReg),
        .o_RUDIConfig           (w_RUDIConfig),
        .o_RUDIIdle                     (w_RUDIIdle),
        .o_RUDIInvalid          (w_RUDIInvalid),
 
        .o_RxDV                         (w_RxDV ),
        .o_RxER                         (w_RxER ),
        .o8_RxD                         (w8_RxD ),
        .o_Invalid                      (o_Invalid),
        .o_Receiving            (w_Receiving),
        .i_Clk                          (w_ClkSys),
        .i_ARst_L                       (w_ARstLogic_L));
 
        mANCtrl u0ANCtrl(
        .i_Clk                          (w_ClkSys                       ),
        .i_ARst_L                       (w_ARstLogic_L          ),
        .i_Cke                          ((~i_PwrDown)           ),
        .i_RestartAN            (w_ANRestart            ),
        .i_SyncStatus           (w_SyncStatus           ),
        .i_ANEnable                     (w_ANEnable                     ),
        .i21_LinkTimer          (w21_LinkTimer          ),
        .i16_LcAdvAbility       (w16_LcAdvAbility       ),
        .o16_LpAdvAbility       (w16_LpAdvAbility       ),
        .o_ANComplete           (w_ANComplete           ),
        .i16_RxConfigReg        (w16_RxConfigReg        ),
        .i_RUDIConfig           (w_RUDIConfig           ),
        .i_RUDIIdle                     (w_RUDIIdle                     ),
        .i_RUDIInvalid          (w_RUDIInvalid          ),
        .o3_Xmit                        (w3_XmitState           ),
        .o16_TxConfigReg        (w16_TxConfigReg        ));
 
        mTransmit       u0Transmit(
        .i3_Xmit                        (w3_XmitState           ),
        .i16_ConfigReg          (w16_TxConfigReg        ),
 
        .i_TxEN                         (w_TxEN                         ),
        .i_TxER                         (w_TxER                         ),
        .i8_TxD                         (w8_TxD                         ),
 
 
        .o_Xmitting                     (w_Transmitting         ),
        .o_TxEven                       (w_TxEven                       ),
        .o8_TxCodeGroupOut      (w8_TxCode                      ),
        .o_TxCodeValid          (w_TxCodeValid          ),
        .o_TxCodeCtrl           (w_TxCodeCtrl           ),
        .i_CurrentParity        (w_CurrentParity        ),
 
        .i_Clk                          (w_ClkSys                       ),
        .i_ARst_L                       (w_ARstLogic_L          ));
 
        assign w_SignalDetect=~w_RxCodeInvalid;
 
        mXcver u0Xcver(
 
        .i_SerRx                        (i_SerRx                        ),
        .o_SerTx                        (o_SerTx                        ),
 
        .i_RefClk125M           (i_RefClk125M           ),
        .o_TxClk                        (w_ClkSys                       ),
        .i_CalClk                       (i_CalClk                       ),
        .i_GxBPwrDwn            (w_GxBPowerDown         ),
        .i_XcverDigitalRst      (~w_ARstLogic_L         ),
        .o_PllLocked            (w_PllLocked            ),
 
        .o_SignalDetect         (),
        .o8_RxCodeGroup         (w8_RxCode                      ),
        .o_RxCodeInvalid        (w_RxCodeInvalid        ),
        .o_RxCodeCtrl           (w_RxCodeCtrl           ),
 
        .i8_TxCodeGroup         (w8_TxCode                      ),
        .i_TxCodeValid          (w_TxCodeValid          ),
        .i_TxCodeCtrl           (w_TxCodeCtrl           ),
        .i_TxForceNegDisp       (w_TxForceNegDisp       ),
        .o_RunningDisparity     (w_CurrentParity));
 
        assign o_GMIIClk = w_ClkSys;
 
        always@(posedge w_ClkSys or negedge i_ARstHardware_L )
        if(~i_ARstHardware_L)
        begin
                r7_Cntr         <= 7'h0;
                r_MIIClk        <= 1'b0;
        end else
        begin
                if(o2_SGMIISpeed==2'b01)
                        begin
                        if(r7_Cntr==7'h4) r7_Cntr<=7'h0; else r7_Cntr<=r7_Cntr+7'h1;
                        if(r7_Cntr==7'h4) r_MIIClk<=1'b1; else if(r7_Cntr==7'h1) r_MIIClk<=1'b0;
                        end
                else if(o2_SGMIISpeed==2'b00)
                        begin
                        if(r7_Cntr==7'h49) r7_Cntr<=7'h0; else r7_Cntr<=r7_Cntr+7'h1;
                        if(r7_Cntr==7'h49) r_MIIClk<=1'b1; else if(r7_Cntr==7'h24) r_MIIClk<=1'b0;
                        end
                r_MIIClk_D <= r_MIIClk;
        end
        assign w_SamplingClk = (r_MIIClk_D & (~r_MIIClk));
 
        //Insert Clock Buffer or PLL if necessary
        mClkBuf u0ClkBuf(.i_Clk(r_MIIClk),.o_Clk(o_MIIClk));
 
endmodule
 
 
 
 
 

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Subversion Repositories sgmii

[/] [sgmii/] [trunk/] [src/] [mSGMII.v] - Blame information for rev 11

Line No.	Rev	Author	Line
1	2	jefflieu	`/*`
2	3	jefflieu	`Developed By Jeff Lieu (lieumychuong@gmail.com)`
3	2	jefflieu	`File :`
4			`Description :`
5			`This core implements:`
6			`B1000-X Standard`
7			`PCS/PMA of SGMII MAC Side`
8			`Remarks :`
9			`Revision :`
10			`Date Author Description`
11			`02/09/12 Jefflieu`
12			`*/`
13
14			`timescale 1ns/10ps
15			`include "SGMIIDefs.v"
16
17			`module mSGMII`
18			`(`
19			`//Tranceiver Interface`
20			`input i_SerRx,`
21			`output o_SerTx,`
22			`input i_CalClk,`
23			`input i_RefClk125M,`
24			`input i_ARstHardware_L,`
25
26			`//Local BUS interface`
27			`//Wishbonebus, single transaction mode (non-pipeline slave)`
28			`input i_Cyc,`
29			`input i_Stb,`
30			`input i_WEn,`
31			`input [31:00] i32_WrData,`
32			`input [07:00] iv_Addr,`
33			`output [31:00] o32_RdData,`
34			`output o_Ack,`
35
36			`input i_Mdc,`
37			`inout io_Mdio,`
38
39			`output o_Linkup,`
40			`output o_ANDone,`
41	5	jefflieu	`//This is used in Phy-Side SGMII`
42			`input i_PhyLink,`
43			`input i_PhyDuplex,`
44			`input [1:0] i2_PhySpeed,`
45	2	jefflieu
46	5	jefflieu
47	2	jefflieu	`output [1:0] o2_SGMIISpeed,`
48			`output o_SGMIIDuplex,`
49
50			`//GMII Interface`
51			`input [07:00] i8_TxD,`
52			`input i_TxEN,`
53			`input i_TxER,`
54			`output [07:00] o8_RxD,`
55			`output o_RxDV,`
56			`output o_RxER,`
57			`output o_GMIIClk,`
58			`output o_MIIClk,`
59			`output o_Col,`
60			`output o_Crs);`
61
62			`wire w_ClkSys;`
63			`wire w_Loopback;`
64			`reg r_RestartAN;`
65			`wire w_ANEnable;`
66			`wire [15:00] w16_Status;`
67			`wire w_MIIRst_L;`
68			`wire w_ANComplete;`
69
70			`wire [07:00] w8_RxCG_SyncToRxver;`
71			`wire w_RxCGInv_SyncToRxver;`
72			`wire w_RxCGCtrl_SyncToRxver;`
73			`wire w_SyncStatus,w_RxEven,w_IsComma,w_OSValid;`
74			`wire w_IsI1Set,w_IsI2Set,w_IsC1Set,w_IsC2Set,w_IsTSet,w_IsVSet,w_IsSSet,w_IsRSet;`
75
76			`wire w_Receiving;`
77			`wire w_Transmitting;`
78			`wire w_CheckEndKDK,w_CheckEndKD21_5D0_0,w_CheckEndKD2_2D0_0,w_CheckEndTRK,w_CheckEndTRR,w_CheckEndRRR,w_CheckEndRRK,w_CheckEndRRS;`
79			`reg r_CheckEndKDK,r_CheckEndKD21_5D0_0,r_CheckEndKD2_2D0_0,r_CheckEndTRK,r_CheckEndTRR,r_CheckEndRRR,r_CheckEndRRK,r_CheckEndRRS;`
80
81			`wire [2:0] w3_XmitState;`
82			`wire [16:01] w16_TxConfigReg;`
83			`wire [15:00] w16_RxConfigReg;`
84			`wire [15:00] w16_LcAdvAbility;`
85			`wire [15:00] w16_LpAdvAbility;`
86			`wire w_RUDIConfig;`
87			`wire w_RUDIIdle;`
88			`wire w_RUDIInvalid;`
89			`wire w_ARstLogic_L;`
90			`wire w_MIIReset_L;`
91			`wire w_ANRestart;`
92			`//This delay stage is for the function checkend`
93			`reg [07:00] r8_RxCodeGroup[0:2];`
94			`reg r_RxCgInvalid[0:2];`
95			`reg r_RxCgCtrl[0:2];`
96			`wire [2:0] w3_PreCheckIsSSet;`
97			`wire [2:0] w3_PreCheckIsTSet;`
98			`wire [2:0] w3_PreCheckIsRSet;`
99			`wire [2:0] w3_PreCheckIsComma;`
100			`wire [2:0] w3_PreCheckIsD21_5;`
101			`wire [2:0] w3_PreCheckIsD2_2;`
102			`wire [2:0] w3_PreCheckIsD;`
103			`wire [2:0] w3_PreCheckIsD0_0;`
104			`wire w_GxBPowerDown;`
105			`wire w_TxCodeCtrl, w_TxCodeValid, w_RxCodeInvalid, w_RxCodeCtrl;`
106			`wire [07:00] w8_TxCode, w8_RxCode;`
107			`wire w_SignalDetect;`
108			`wire w_TxForceNegDisp;`
109			`wire w_PllLocked;`
110			`wire [20:00] w21_LinkTimer;`
111			`wire w_TxEN,w_TxER,w_RxER, w_RxDV;`
112			`wire [07:00] w8_RxD, w8_TxD;`
113
114			`//MII Clock Gen`
115			`reg [6:0] r7_Cntr;`
116			`reg r_MIIClk;`
117			`reg r_MIIClk_D;`
118			`wire w_SamplingClk;`
119
120			`integer DELAY;`
121
122			`assign o_Linkup = w_SyncStatus;`
123			`assign o_ANDone = w_ANComplete;`
124
125			`mRateAdapter u0RateAdapter(`
126			`//MAC Side signal`
127			`.i_TxClk (o_MIIClk),`
128			`.i_TxEN (i_TxEN ),`
129			`.i_TxER (i_TxER ),`
130			`.i8_TxD (i8_TxD ),`
131			`.i_RxClk (o_MIIClk),`
132			`.o_RxEN (o_RxDV),`
133			`.o_RxER (o_RxER),`
134			`.o8_RxD (o8_RxD),`
135			`.i2_Speed (o2_SGMIISpeed),`
136			`//SGMII PHY side`
137			`.i_SamplingClk (w_SamplingClk),`
138			`.i_GClk (w_ClkSys),`
139			`.o_TxEN (w_TxEN),`
140			`.o_TxER (w_TxER),`
141			`.o8_TxD (w8_TxD),`
142			`.i_RxEN (w_RxDV),`
143			`.i_RxER (w_RxER),`
144			`.i8_RxD (w8_RxD));`
145
146			`generate`
147			`genvar STAGE;`
148			`for(STAGE=0;STAGE<3;STAGE=STAGE+1)`
149			`begin`
150			assign w3_PreCheckIsComma[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b1 && r8_RxCodeGroup[STAGE]==`K28_5)?1'b1:1'b0;
151			assign w3_PreCheckIsTSet[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b1 && r8_RxCodeGroup[STAGE]==`K29_7)?1'b1:1'b0;
152			assign w3_PreCheckIsRSet[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b1 && r8_RxCodeGroup[STAGE]==`K23_7)?1'b1:1'b0;
153			assign w3_PreCheckIsD21_5[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b0 && r8_RxCodeGroup[STAGE]==`D21_5)?1'b1:1'b0;
154			assign w3_PreCheckIsD2_2[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b0 && r8_RxCodeGroup[STAGE]==`D2_2)?1'b1:1'b0;
155			`assign w3_PreCheckIsD[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b0)?1'b1:1'b0;`
156			assign w3_PreCheckIsD0_0[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b0 && r8_RxCodeGroup[STAGE]==`D0_0)?1'b1:1'b0;
157			assign w3_PreCheckIsSSet[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b1 && r8_RxCodeGroup[STAGE]==`K27_7)?1'b1:1'b0;
158			`end`
159			`endgenerate`
160
161			`assign w_CheckEndKDK = w3_PreCheckIsComma[2] & w3_PreCheckIsD[1]&w3_PreCheckIsComma[0];`
162			`assign w_CheckEndRRR = &(w3_PreCheckIsRSet);`
163			`assign w_CheckEndTRK = w3_PreCheckIsTSet[2] & w3_PreCheckIsRSet[1] & w3_PreCheckIsComma[0];`
164			`assign w_CheckEndTRR = w3_PreCheckIsTSet[2] & w3_PreCheckIsRSet[1] & w3_PreCheckIsRSet[0];`
165			`assign w_CheckEndKD21_5D0_0 = w3_PreCheckIsComma[2] & w3_PreCheckIsD21_5[1] & w3_PreCheckIsD2_2[0];`
166			`assign w_CheckEndKD2_2D0_0 = w3_PreCheckIsComma[2] & w3_PreCheckIsD2_2[1] & w3_PreCheckIsD2_2[0];`
167			`assign w_CheckEndRRK = w3_PreCheckIsRSet[2] & w3_PreCheckIsRSet[1] & w3_PreCheckIsComma[0];`
168			`assign w_CheckEndRRS = w3_PreCheckIsRSet[2] & w3_PreCheckIsRSet[1] & w3_PreCheckIsSSet[0];`
169
170			`always@(posedge w_ClkSys)`
171			`begin`
172			`r8_RxCodeGroup[0] <= w8_RxCode;`
173			`r_RxCgCtrl[0] <= w_RxCodeCtrl;`
174			`r_RxCgInvalid[0] <= w_RxCodeInvalid;`
175			`for(DELAY=1;DELAY<3;DELAY=DELAY+1)`
176			`begin`
177			`r8_RxCodeGroup[DELAY] <= r8_RxCodeGroup[DELAY-1];`
178			`r_RxCgInvalid[DELAY] <= r_RxCgInvalid[DELAY-1];`
179			`r_RxCgCtrl[DELAY] <= r_RxCgCtrl[DELAY-1];`
180			`end`
181			`end`
182
183			`assign o_Col = w_Transmitting & w_Receiving;`
184			`assign o_Crs = 1'b0;`
185			`assign w_ARstLogic_L = w_PllLocked & i_ARstHardware_L & (w_MIIRst_L);`
186			`mRegisters u0Registers(`
187			`.w_ARstLogic_L (w_ARstLogic_L),`
188			`.i_Clk (w_ClkSys),`
189			`.i_Cyc (i_Cyc),`
190			`.i_Stb (i_Stb),`
191			`.i_WEn (i_WEn),`
192			`.i8_Addr (iv_Addr),`
193			`.i32_WrData (i32_WrData),`
194			`.o32_RdData (o32_RdData),`
195			`.o_Ack (o_Ack),`
196			`.o_Stall (o_Stall),`
197
198			`.io_Mdio (io_Mdio),`
199			`.i_Mdc (i_Mdc),`
200
201			`//Register in and out,`
202
203			`//MAC-Side SGMII`
204			`.o2_SGMIISpeed (o2_SGMIISpeed),`
205			`.o_SGMIIDuplex (o_SGMIIDuplex),`
206
207			`//Phy-Side SGMII`
208			`.i_PhyLink (i_PhyLink ),`
209			`.i_PhyDuplex (i_PhyDuplex),`
210			`.i2_PhySpeed (i2_PhySpeed),`
211			`.o21_LinkTimer (w21_LinkTimer),`
212
213			`.i16_TxConfigReg (w16_TxConfigReg),`
214			`.o_MIIRst_L (w_MIIRst_L),`
215			`.o_ANEnable (w_ANEnable),`
216			`.o_ANRestart (w_ANRestart),`
217			`.o_Loopback (w_Loopback),`
218			`.o_GXBPowerDown (w_GxBPowerDown),`
219			`.o16_LcAdvAbility (w16_LcAdvAbility),`
220			`.i3_XmitState (w3_XmitState),`
221			`.i_SyncStatus (w_SyncStatus),`
222			`.i_ANComplete (w_ANComplete),`
223			`.i16_LpAdvAbility (w16_LpAdvAbility));`
224
225			`mSyncCtrl u0SyncCtrl(`
226			`.i_Clk (w_ClkSys ),`
227			`.i_Cke ((~w_GxBPowerDown) ),`
228			`.i_ARst_L (w_ARstLogic_L ),`
229			`.i_CtrlLoopBack (w_Loopback ),`
230
231			`.i8_RxCodeGroupIn (r8_RxCodeGroup[2] ),`
232			`.i_RxCodeInvalid (r_RxCgInvalid[2] ),`
233			`.i_RxCodeCtrl (r_RxCgCtrl[2] ),`
234			`.i_SignalDetect (w_SignalDetect ),`
235
236			`.o8_RxCodeGroupOut (w8_RxCG_SyncToRxver ),`
237			`.o_RxCodeInvalid (w_RxCGInv_SyncToRxver ),`
238			`.o_RxCodeCtrl (w_RxCGCtrl_SyncToRxver ),`
239			`.o_RxEven (w_RxEven ),`
240			`.o_SyncStatus (w_SyncStatus ),`
241			`.o_BitSlip (),`
242			`.o_IsComma (w_IsComma ),`
243			`.o_OrderedSetValid (w_OSValid ),`
244			`.o_IsI1Set (w_IsI1Set ),`
245			`.o_IsI2Set (w_IsI2Set ),`
246			`.o_IsC1Set (w_IsC1Set ),`
247			`.o_IsC2Set (w_IsC2Set ),`
248			`.o_IsTSet (w_IsTSet ),`
249			`.o_IsVSet (w_IsVSet ),`
250			`.o_IsSSet (w_IsSSet ),`
251			`.o_IsRSet (w_IsRSet ));`
252
253			`always@(posedge w_ClkSys)`
254			`begin`
255			`r_CheckEndKDK <= w_CheckEndKDK;`
256			`r_CheckEndKD21_5D0_0 <= w_CheckEndKD21_5D0_0;`
257			`r_CheckEndKD2_2D0_0 <= w_CheckEndKD2_2D0_0;`
258			`r_CheckEndTRK <= w_CheckEndTRK;`
259			`r_CheckEndTRR <= w_CheckEndTRR;`
260			`r_CheckEndRRR <= w_CheckEndRRR;`
261			`r_CheckEndRRK <= w_CheckEndRRK;`
262			`r_CheckEndRRS <= w_CheckEndRRS;`
263			`end`
264
265			`mReceive u0Receive(`
266			`.i8_RxCodeGroupIn (w8_RxCG_SyncToRxver ),`
267			`.i_RxCodeInvalid (w_RxCGInv_SyncToRxver ),`
268			`.i_RxCodeCtrl (w_RxCGCtrl_SyncToRxver ),`
269			`.i_RxEven (w_RxEven ),`
270
271			`.i3_Xmit (w3_XmitState),`
272
273			`.i_IsComma (w_IsComma ),`
274			`.i_OrderedSetValid (w_OSValid ),`
275			`.i_IsI1Set (w_IsI1Set ),`
276			`.i_IsI2Set (w_IsI2Set ),`
277			`.i_IsC1Set (w_IsC1Set ),`
278			`.i_IsC2Set (w_IsC2Set ),`
279			`.i_IsTSet (w_IsTSet ),`
280			`.i_IsVSet (w_IsVSet ),`
281			`.i_IsSSet (w_IsSSet ),`
282			`.i_IsRSet (w_IsRSet ),`
283
284			`.i_CheckEndKDK (r_CheckEndKDK ),`
285			`.i_CheckEndKD21_5D0_0 (r_CheckEndKD21_5D0_0 ),`
286			`.i_CheckEndKD2_2D0_0 (r_CheckEndKD2_2D0_0 ),`
287			`.i_CheckEndTRK (r_CheckEndTRK ),`
288			`.i_CheckEndTRR (r_CheckEndTRR ),`
289			`.i_CheckEndRRR (r_CheckEndRRR ),`
290			`.i_CheckEndRRK (r_CheckEndRRK ),`
291			`.i_CheckEndRRS (r_CheckEndRRS ),`
292
293			`.o16_RxConfigReg (w16_RxConfigReg),`
294			`.o_RUDIConfig (w_RUDIConfig),`
295			`.o_RUDIIdle (w_RUDIIdle),`
296			`.o_RUDIInvalid (w_RUDIInvalid),`
297
298			`.o_RxDV (w_RxDV ),`
299			`.o_RxER (w_RxER ),`
300			`.o8_RxD (w8_RxD ),`
301			`.o_Invalid (o_Invalid),`
302			`.o_Receiving (w_Receiving),`
303			`.i_Clk (w_ClkSys),`
304			`.i_ARst_L (w_ARstLogic_L));`
305
306			`mANCtrl u0ANCtrl(`
307			`.i_Clk (w_ClkSys ),`
308			`.i_ARst_L (w_ARstLogic_L ),`
309			`.i_Cke ((~i_PwrDown) ),`
310			`.i_RestartAN (w_ANRestart ),`
311			`.i_SyncStatus (w_SyncStatus ),`
312			`.i_ANEnable (w_ANEnable ),`
313			`.i21_LinkTimer (w21_LinkTimer ),`
314			`.i16_LcAdvAbility (w16_LcAdvAbility ),`
315			`.o16_LpAdvAbility (w16_LpAdvAbility ),`
316			`.o_ANComplete (w_ANComplete ),`
317			`.i16_RxConfigReg (w16_RxConfigReg ),`
318			`.i_RUDIConfig (w_RUDIConfig ),`
319			`.i_RUDIIdle (w_RUDIIdle ),`
320			`.i_RUDIInvalid (w_RUDIInvalid ),`
321			`.o3_Xmit (w3_XmitState ),`
322			`.o16_TxConfigReg (w16_TxConfigReg ));`
323
324			`mTransmit u0Transmit(`
325			`.i3_Xmit (w3_XmitState ),`
326			`.i16_ConfigReg (w16_TxConfigReg ),`
327
328			`.i_TxEN (w_TxEN ),`
329			`.i_TxER (w_TxER ),`
330			`.i8_TxD (w8_TxD ),`
331
332
333			`.o_Xmitting (w_Transmitting ),`
334			`.o_TxEven (w_TxEven ),`
335			`.o8_TxCodeGroupOut (w8_TxCode ),`
336			`.o_TxCodeValid (w_TxCodeValid ),`
337			`.o_TxCodeCtrl (w_TxCodeCtrl ),`
338			`.i_CurrentParity (w_CurrentParity ),`
339
340			`.i_Clk (w_ClkSys ),`
341			`.i_ARst_L (w_ARstLogic_L ));`
342
343	3	jefflieu	`assign w_SignalDetect=~w_RxCodeInvalid;`
344	2	jefflieu
345			`mXcver u0Xcver(`
346
347			`.i_SerRx (i_SerRx ),`
348			`.o_SerTx (o_SerTx ),`
349
350			`.i_RefClk125M (i_RefClk125M ),`
351			`.o_TxClk (w_ClkSys ),`
352			`.i_CalClk (i_CalClk ),`
353			`.i_GxBPwrDwn (w_GxBPowerDown ),`
354			`.i_XcverDigitalRst (~w_ARstLogic_L ),`
355			`.o_PllLocked (w_PllLocked ),`
356
357	3	jefflieu	`.o_SignalDetect (),`
358	2	jefflieu	`.o8_RxCodeGroup (w8_RxCode ),`
359			`.o_RxCodeInvalid (w_RxCodeInvalid ),`
360			`.o_RxCodeCtrl (w_RxCodeCtrl ),`
361
362			`.i8_TxCodeGroup (w8_TxCode ),`
363			`.i_TxCodeValid (w_TxCodeValid ),`
364			`.i_TxCodeCtrl (w_TxCodeCtrl ),`
365			`.i_TxForceNegDisp (w_TxForceNegDisp ),`
366			`.o_RunningDisparity (w_CurrentParity));`
367
368			`assign o_GMIIClk = w_ClkSys;`
369
370	11	jefflieu	`always@(posedge w_ClkSys or negedge i_ARstHardware_L )`
371			`if(~i_ARstHardware_L)`
372	2	jefflieu	`begin`
373	11	jefflieu	`r7_Cntr <= 7'h0;`
374			`r_MIIClk <= 1'b0;`
375			`end else`
376			`begin`
377	2	jefflieu	`if(o2_SGMIISpeed==2'b01)`
378			`begin`
379			`if(r7_Cntr==7'h4) r7_Cntr<=7'h0; else r7_Cntr<=r7_Cntr+7'h1;`
380			`if(r7_Cntr==7'h4) r_MIIClk<=1'b1; else if(r7_Cntr==7'h1) r_MIIClk<=1'b0;`
381			`end`
382			`else if(o2_SGMIISpeed==2'b00)`
383			`begin`
384			`if(r7_Cntr==7'h49) r7_Cntr<=7'h0; else r7_Cntr<=r7_Cntr+7'h1;`
385			`if(r7_Cntr==7'h49) r_MIIClk<=1'b1; else if(r7_Cntr==7'h24) r_MIIClk<=1'b0;`
386			`end`
387			`r_MIIClk_D <= r_MIIClk;`
388			`end`
389			`assign w_SamplingClk = (r_MIIClk_D & (~r_MIIClk));`
390
391			`//Insert Clock Buffer or PLL if necessary`
392			`mClkBuf u0ClkBuf(.i_Clk(r_MIIClk),.o_Clk(o_MIIClk));`
393
394			`endmodule`
395
396
397
398
399