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jefflieu |
/*
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jefflieu |
Developed By Jeff Lieu (lieumychuong@gmail.com)
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jefflieu |
File :
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Description :
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This core implements:
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B1000-X Standard
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PCS/PMA of SGMII MAC Side
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Remarks :
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Revision :
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Date Author Description
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02/09/12 Jefflieu
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*/
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`timescale 1ns/10ps
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`include "SGMIIDefs.v"
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module mSGMII
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(
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//Tranceiver Interface
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input i_SerRx,
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output o_SerTx,
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input i_CalClk,
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input i_RefClk125M,
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input i_ARstHardware_L,
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//Local BUS interface
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//Wishbonebus, single transaction mode (non-pipeline slave)
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input i_Cyc,
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input i_Stb,
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input i_WEn,
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input [31:00] i32_WrData,
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input [07:00] iv_Addr,
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output [31:00] o32_RdData,
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output o_Ack,
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input i_Mdc,
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inout io_Mdio,
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output o_Linkup,
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output o_ANDone,
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jefflieu |
//This is used in Phy-Side SGMII
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input i_PhyLink,
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input i_PhyDuplex,
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input [1:0] i2_PhySpeed,
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output [1:0] o2_SGMIISpeed,
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output o_SGMIIDuplex,
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//GMII Interface
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input [07:00] i8_TxD,
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input i_TxEN,
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input i_TxER,
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output [07:00] o8_RxD,
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output o_RxDV,
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output o_RxER,
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output o_GMIIClk,
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output o_MIIClk,
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output o_Col,
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output o_Crs);
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wire w_ClkSys;
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wire w_Loopback;
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reg r_RestartAN;
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wire w_ANEnable;
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wire [15:00] w16_Status;
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wire w_MIIRst_L;
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wire w_ANComplete;
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wire [07:00] w8_RxCG_SyncToRxver;
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wire w_RxCGInv_SyncToRxver;
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wire w_RxCGCtrl_SyncToRxver;
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wire w_SyncStatus,w_RxEven,w_IsComma,w_OSValid;
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wire w_IsI1Set,w_IsI2Set,w_IsC1Set,w_IsC2Set,w_IsTSet,w_IsVSet,w_IsSSet,w_IsRSet;
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wire w_Receiving;
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wire w_Transmitting;
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wire w_CheckEndKDK,w_CheckEndKD21_5D0_0,w_CheckEndKD2_2D0_0,w_CheckEndTRK,w_CheckEndTRR,w_CheckEndRRR,w_CheckEndRRK,w_CheckEndRRS;
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reg r_CheckEndKDK,r_CheckEndKD21_5D0_0,r_CheckEndKD2_2D0_0,r_CheckEndTRK,r_CheckEndTRR,r_CheckEndRRR,r_CheckEndRRK,r_CheckEndRRS;
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wire [2:0] w3_XmitState;
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wire [16:01] w16_TxConfigReg;
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wire [15:00] w16_RxConfigReg;
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wire [15:00] w16_LcAdvAbility;
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wire [15:00] w16_LpAdvAbility;
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wire w_RUDIConfig;
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wire w_RUDIIdle;
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wire w_RUDIInvalid;
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wire w_ARstLogic_L;
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wire w_MIIReset_L;
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wire w_ANRestart;
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//This delay stage is for the function checkend
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reg [07:00] r8_RxCodeGroup[0:2];
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reg r_RxCgInvalid[0:2];
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reg r_RxCgCtrl[0:2];
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wire [2:0] w3_PreCheckIsSSet;
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wire [2:0] w3_PreCheckIsTSet;
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wire [2:0] w3_PreCheckIsRSet;
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wire [2:0] w3_PreCheckIsComma;
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wire [2:0] w3_PreCheckIsD21_5;
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wire [2:0] w3_PreCheckIsD2_2;
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wire [2:0] w3_PreCheckIsD;
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wire [2:0] w3_PreCheckIsD0_0;
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wire w_GxBPowerDown;
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wire w_TxCodeCtrl, w_TxCodeValid, w_RxCodeInvalid, w_RxCodeCtrl;
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wire [07:00] w8_TxCode, w8_RxCode;
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wire w_SignalDetect;
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wire w_TxForceNegDisp;
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wire w_PllLocked;
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wire [20:00] w21_LinkTimer;
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wire w_TxEN,w_TxER,w_RxER, w_RxDV;
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wire [07:00] w8_RxD, w8_TxD;
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//MII Clock Gen
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reg [6:0] r7_Cntr;
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reg r_MIIClk;
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reg r_MIIClk_D;
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wire w_SamplingClk;
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integer DELAY;
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assign o_Linkup = w_SyncStatus;
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assign o_ANDone = w_ANComplete;
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mRateAdapter u0RateAdapter(
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//MAC Side signal
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.i_TxClk (o_MIIClk),
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.i_TxEN (i_TxEN ),
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.i_TxER (i_TxER ),
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.i8_TxD (i8_TxD ),
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.i_RxClk (o_MIIClk),
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.o_RxEN (o_RxDV),
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.o_RxER (o_RxER),
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.o8_RxD (o8_RxD),
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.i2_Speed (o2_SGMIISpeed),
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//SGMII PHY side
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.i_SamplingClk (w_SamplingClk),
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.i_GClk (w_ClkSys),
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.o_TxEN (w_TxEN),
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.o_TxER (w_TxER),
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.o8_TxD (w8_TxD),
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.i_RxEN (w_RxDV),
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.i_RxER (w_RxER),
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.i8_RxD (w8_RxD));
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generate
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genvar STAGE;
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for(STAGE=0;STAGE<3;STAGE=STAGE+1)
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begin
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assign w3_PreCheckIsComma[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b1 && r8_RxCodeGroup[STAGE]==`K28_5)?1'b1:1'b0;
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assign w3_PreCheckIsTSet[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b1 && r8_RxCodeGroup[STAGE]==`K29_7)?1'b1:1'b0;
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assign w3_PreCheckIsRSet[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b1 && r8_RxCodeGroup[STAGE]==`K23_7)?1'b1:1'b0;
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assign w3_PreCheckIsD21_5[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b0 && r8_RxCodeGroup[STAGE]==`D21_5)?1'b1:1'b0;
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assign w3_PreCheckIsD2_2[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b0 && r8_RxCodeGroup[STAGE]==`D2_2)?1'b1:1'b0;
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assign w3_PreCheckIsD[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b0)?1'b1:1'b0;
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assign w3_PreCheckIsD0_0[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b0 && r8_RxCodeGroup[STAGE]==`D0_0)?1'b1:1'b0;
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assign w3_PreCheckIsSSet[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b1 && r8_RxCodeGroup[STAGE]==`K27_7)?1'b1:1'b0;
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end
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endgenerate
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assign w_CheckEndKDK = w3_PreCheckIsComma[2] & w3_PreCheckIsD[1]&w3_PreCheckIsComma[0];
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assign w_CheckEndRRR = &(w3_PreCheckIsRSet);
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assign w_CheckEndTRK = w3_PreCheckIsTSet[2] & w3_PreCheckIsRSet[1] & w3_PreCheckIsComma[0];
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assign w_CheckEndTRR = w3_PreCheckIsTSet[2] & w3_PreCheckIsRSet[1] & w3_PreCheckIsRSet[0];
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assign w_CheckEndKD21_5D0_0 = w3_PreCheckIsComma[2] & w3_PreCheckIsD21_5[1] & w3_PreCheckIsD2_2[0];
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assign w_CheckEndKD2_2D0_0 = w3_PreCheckIsComma[2] & w3_PreCheckIsD2_2[1] & w3_PreCheckIsD2_2[0];
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assign w_CheckEndRRK = w3_PreCheckIsRSet[2] & w3_PreCheckIsRSet[1] & w3_PreCheckIsComma[0];
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assign w_CheckEndRRS = w3_PreCheckIsRSet[2] & w3_PreCheckIsRSet[1] & w3_PreCheckIsSSet[0];
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always@(posedge w_ClkSys)
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begin
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r8_RxCodeGroup[0] <= w8_RxCode;
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r_RxCgCtrl[0] <= w_RxCodeCtrl;
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r_RxCgInvalid[0] <= w_RxCodeInvalid;
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for(DELAY=1;DELAY<3;DELAY=DELAY+1)
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begin
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r8_RxCodeGroup[DELAY] <= r8_RxCodeGroup[DELAY-1];
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r_RxCgInvalid[DELAY] <= r_RxCgInvalid[DELAY-1];
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r_RxCgCtrl[DELAY] <= r_RxCgCtrl[DELAY-1];
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end
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end
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assign o_Col = w_Transmitting & w_Receiving;
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assign o_Crs = 1'b0;
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assign w_ARstLogic_L = w_PllLocked & i_ARstHardware_L & (w_MIIRst_L);
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mRegisters u0Registers(
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.w_ARstLogic_L (w_ARstLogic_L),
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.i_Clk (w_ClkSys),
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.i_Cyc (i_Cyc),
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.i_Stb (i_Stb),
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.i_WEn (i_WEn),
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.i8_Addr (iv_Addr),
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.i32_WrData (i32_WrData),
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.o32_RdData (o32_RdData),
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.o_Ack (o_Ack),
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.o_Stall (o_Stall),
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.io_Mdio (io_Mdio),
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.i_Mdc (i_Mdc),
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//Register in and out,
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//MAC-Side SGMII
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.o2_SGMIISpeed (o2_SGMIISpeed),
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.o_SGMIIDuplex (o_SGMIIDuplex),
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//Phy-Side SGMII
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.i_PhyLink (i_PhyLink ),
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.i_PhyDuplex (i_PhyDuplex),
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.i2_PhySpeed (i2_PhySpeed),
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.o21_LinkTimer (w21_LinkTimer),
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.i16_TxConfigReg (w16_TxConfigReg),
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.o_MIIRst_L (w_MIIRst_L),
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.o_ANEnable (w_ANEnable),
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.o_ANRestart (w_ANRestart),
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.o_Loopback (w_Loopback),
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.o_GXBPowerDown (w_GxBPowerDown),
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.o16_LcAdvAbility (w16_LcAdvAbility),
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.i3_XmitState (w3_XmitState),
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.i_SyncStatus (w_SyncStatus),
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.i_ANComplete (w_ANComplete),
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.i16_LpAdvAbility (w16_LpAdvAbility));
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mSyncCtrl u0SyncCtrl(
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.i_Clk (w_ClkSys ),
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.i_Cke ((~w_GxBPowerDown) ),
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.i_ARst_L (w_ARstLogic_L ),
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.i_CtrlLoopBack (w_Loopback ),
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.i8_RxCodeGroupIn (r8_RxCodeGroup[2] ),
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.i_RxCodeInvalid (r_RxCgInvalid[2] ),
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.i_RxCodeCtrl (r_RxCgCtrl[2] ),
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.i_SignalDetect (w_SignalDetect ),
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.o8_RxCodeGroupOut (w8_RxCG_SyncToRxver ),
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.o_RxCodeInvalid (w_RxCGInv_SyncToRxver ),
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.o_RxCodeCtrl (w_RxCGCtrl_SyncToRxver ),
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.o_RxEven (w_RxEven ),
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.o_SyncStatus (w_SyncStatus ),
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.o_BitSlip (),
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.o_IsComma (w_IsComma ),
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.o_OrderedSetValid (w_OSValid ),
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.o_IsI1Set (w_IsI1Set ),
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.o_IsI2Set (w_IsI2Set ),
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.o_IsC1Set (w_IsC1Set ),
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.o_IsC2Set (w_IsC2Set ),
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.o_IsTSet (w_IsTSet ),
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.o_IsVSet (w_IsVSet ),
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.o_IsSSet (w_IsSSet ),
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.o_IsRSet (w_IsRSet ));
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always@(posedge w_ClkSys)
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begin
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r_CheckEndKDK <= w_CheckEndKDK;
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r_CheckEndKD21_5D0_0 <= w_CheckEndKD21_5D0_0;
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r_CheckEndKD2_2D0_0 <= w_CheckEndKD2_2D0_0;
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r_CheckEndTRK <= w_CheckEndTRK;
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r_CheckEndTRR <= w_CheckEndTRR;
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r_CheckEndRRR <= w_CheckEndRRR;
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r_CheckEndRRK <= w_CheckEndRRK;
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r_CheckEndRRS <= w_CheckEndRRS;
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end
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mReceive u0Receive(
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.i8_RxCodeGroupIn (w8_RxCG_SyncToRxver ),
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.i_RxCodeInvalid (w_RxCGInv_SyncToRxver ),
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.i_RxCodeCtrl (w_RxCGCtrl_SyncToRxver ),
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.i_RxEven (w_RxEven ),
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.i3_Xmit (w3_XmitState),
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.i_IsComma (w_IsComma ),
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.i_OrderedSetValid (w_OSValid ),
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.i_IsI1Set (w_IsI1Set ),
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.i_IsI2Set (w_IsI2Set ),
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.i_IsC1Set (w_IsC1Set ),
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.i_IsC2Set (w_IsC2Set ),
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.i_IsTSet (w_IsTSet ),
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.i_IsVSet (w_IsVSet ),
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.i_IsSSet (w_IsSSet ),
|
| 282 |
|
|
.i_IsRSet (w_IsRSet ),
|
| 283 |
|
|
|
| 284 |
|
|
.i_CheckEndKDK (r_CheckEndKDK ),
|
| 285 |
|
|
.i_CheckEndKD21_5D0_0 (r_CheckEndKD21_5D0_0 ),
|
| 286 |
|
|
.i_CheckEndKD2_2D0_0 (r_CheckEndKD2_2D0_0 ),
|
| 287 |
|
|
.i_CheckEndTRK (r_CheckEndTRK ),
|
| 288 |
|
|
.i_CheckEndTRR (r_CheckEndTRR ),
|
| 289 |
|
|
.i_CheckEndRRR (r_CheckEndRRR ),
|
| 290 |
|
|
.i_CheckEndRRK (r_CheckEndRRK ),
|
| 291 |
|
|
.i_CheckEndRRS (r_CheckEndRRS ),
|
| 292 |
|
|
|
| 293 |
|
|
.o16_RxConfigReg (w16_RxConfigReg),
|
| 294 |
|
|
.o_RUDIConfig (w_RUDIConfig),
|
| 295 |
|
|
.o_RUDIIdle (w_RUDIIdle),
|
| 296 |
|
|
.o_RUDIInvalid (w_RUDIInvalid),
|
| 297 |
|
|
|
| 298 |
|
|
.o_RxDV (w_RxDV ),
|
| 299 |
|
|
.o_RxER (w_RxER ),
|
| 300 |
|
|
.o8_RxD (w8_RxD ),
|
| 301 |
|
|
.o_Invalid (o_Invalid),
|
| 302 |
|
|
.o_Receiving (w_Receiving),
|
| 303 |
|
|
.i_Clk (w_ClkSys),
|
| 304 |
|
|
.i_ARst_L (w_ARstLogic_L));
|
| 305 |
|
|
|
| 306 |
|
|
mANCtrl u0ANCtrl(
|
| 307 |
|
|
.i_Clk (w_ClkSys ),
|
| 308 |
|
|
.i_ARst_L (w_ARstLogic_L ),
|
| 309 |
|
|
.i_Cke ((~i_PwrDown) ),
|
| 310 |
|
|
.i_RestartAN (w_ANRestart ),
|
| 311 |
|
|
.i_SyncStatus (w_SyncStatus ),
|
| 312 |
|
|
.i_ANEnable (w_ANEnable ),
|
| 313 |
|
|
.i21_LinkTimer (w21_LinkTimer ),
|
| 314 |
|
|
.i16_LcAdvAbility (w16_LcAdvAbility ),
|
| 315 |
|
|
.o16_LpAdvAbility (w16_LpAdvAbility ),
|
| 316 |
|
|
.o_ANComplete (w_ANComplete ),
|
| 317 |
|
|
.i16_RxConfigReg (w16_RxConfigReg ),
|
| 318 |
|
|
.i_RUDIConfig (w_RUDIConfig ),
|
| 319 |
|
|
.i_RUDIIdle (w_RUDIIdle ),
|
| 320 |
|
|
.i_RUDIInvalid (w_RUDIInvalid ),
|
| 321 |
|
|
.o3_Xmit (w3_XmitState ),
|
| 322 |
|
|
.o16_TxConfigReg (w16_TxConfigReg ));
|
| 323 |
|
|
|
| 324 |
|
|
mTransmit u0Transmit(
|
| 325 |
|
|
.i3_Xmit (w3_XmitState ),
|
| 326 |
|
|
.i16_ConfigReg (w16_TxConfigReg ),
|
| 327 |
|
|
|
| 328 |
|
|
.i_TxEN (w_TxEN ),
|
| 329 |
|
|
.i_TxER (w_TxER ),
|
| 330 |
|
|
.i8_TxD (w8_TxD ),
|
| 331 |
|
|
|
| 332 |
|
|
|
| 333 |
|
|
.o_Xmitting (w_Transmitting ),
|
| 334 |
|
|
.o_TxEven (w_TxEven ),
|
| 335 |
|
|
.o8_TxCodeGroupOut (w8_TxCode ),
|
| 336 |
|
|
.o_TxCodeValid (w_TxCodeValid ),
|
| 337 |
|
|
.o_TxCodeCtrl (w_TxCodeCtrl ),
|
| 338 |
|
|
.i_CurrentParity (w_CurrentParity ),
|
| 339 |
|
|
|
| 340 |
|
|
.i_Clk (w_ClkSys ),
|
| 341 |
|
|
.i_ARst_L (w_ARstLogic_L ));
|
| 342 |
|
|
|
| 343 |
3 |
jefflieu |
assign w_SignalDetect=~w_RxCodeInvalid;
|
| 344 |
2 |
jefflieu |
|
| 345 |
|
|
mXcver u0Xcver(
|
| 346 |
|
|
|
| 347 |
|
|
.i_SerRx (i_SerRx ),
|
| 348 |
|
|
.o_SerTx (o_SerTx ),
|
| 349 |
|
|
|
| 350 |
|
|
.i_RefClk125M (i_RefClk125M ),
|
| 351 |
|
|
.o_TxClk (w_ClkSys ),
|
| 352 |
|
|
.i_CalClk (i_CalClk ),
|
| 353 |
|
|
.i_GxBPwrDwn (w_GxBPowerDown ),
|
| 354 |
|
|
.i_XcverDigitalRst (~w_ARstLogic_L ),
|
| 355 |
|
|
.o_PllLocked (w_PllLocked ),
|
| 356 |
|
|
|
| 357 |
3 |
jefflieu |
.o_SignalDetect (),
|
| 358 |
2 |
jefflieu |
.o8_RxCodeGroup (w8_RxCode ),
|
| 359 |
|
|
.o_RxCodeInvalid (w_RxCodeInvalid ),
|
| 360 |
|
|
.o_RxCodeCtrl (w_RxCodeCtrl ),
|
| 361 |
|
|
|
| 362 |
|
|
.i8_TxCodeGroup (w8_TxCode ),
|
| 363 |
|
|
.i_TxCodeValid (w_TxCodeValid ),
|
| 364 |
|
|
.i_TxCodeCtrl (w_TxCodeCtrl ),
|
| 365 |
|
|
.i_TxForceNegDisp (w_TxForceNegDisp ),
|
| 366 |
|
|
.o_RunningDisparity (w_CurrentParity));
|
| 367 |
|
|
|
| 368 |
|
|
assign o_GMIIClk = w_ClkSys;
|
| 369 |
|
|
|
| 370 |
|
|
always@(posedge w_ClkSys)
|
| 371 |
|
|
begin
|
| 372 |
|
|
if(o2_SGMIISpeed==2'b01)
|
| 373 |
|
|
begin
|
| 374 |
|
|
if(r7_Cntr==7'h4) r7_Cntr<=7'h0; else r7_Cntr<=r7_Cntr+7'h1;
|
| 375 |
|
|
if(r7_Cntr==7'h4) r_MIIClk<=1'b1; else if(r7_Cntr==7'h1) r_MIIClk<=1'b0;
|
| 376 |
|
|
end
|
| 377 |
|
|
else if(o2_SGMIISpeed==2'b00)
|
| 378 |
|
|
begin
|
| 379 |
|
|
if(r7_Cntr==7'h49) r7_Cntr<=7'h0; else r7_Cntr<=r7_Cntr+7'h1;
|
| 380 |
|
|
if(r7_Cntr==7'h49) r_MIIClk<=1'b1; else if(r7_Cntr==7'h24) r_MIIClk<=1'b0;
|
| 381 |
|
|
end
|
| 382 |
|
|
r_MIIClk_D <= r_MIIClk;
|
| 383 |
|
|
end
|
| 384 |
|
|
assign w_SamplingClk = (r_MIIClk_D & (~r_MIIClk));
|
| 385 |
|
|
|
| 386 |
|
|
//Insert Clock Buffer or PLL if necessary
|
| 387 |
|
|
mClkBuf u0ClkBuf(.i_Clk(r_MIIClk),.o_Clk(o_MIIClk));
|
| 388 |
|
|
|
| 389 |
|
|
endmodule
|
| 390 |
|
|
|
| 391 |
|
|
|
| 392 |
|
|
|
| 393 |
|
|
|
| 394 |
|
|
|
