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[/] [sgmii/] [trunk/] [src/] [mSyncCtrl.v] - Blame information for rev 13

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1 2 jefflieu
/*
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Developed By Subtleware Corporation Pte Ltd 2011
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File            :
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Description     :
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Remarks         :
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Revision        :
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        Date    Author          Description
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02/09/12        Jefflieu
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*/
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`include "SGMIIDefs.v"
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module mSyncCtrl (
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        input   i_Clk,
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        input   i_Cke,
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        input   i_ARst_L,
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        input   i_CtrlLoopBack,
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        input   [07:00] i8_RxCodeGroupIn,
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        input   i_RxCodeInvalid,
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        input   i_RxCodeCtrl,
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        input   i_SignalDetect,
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        output reg      [07:00] o8_RxCodeGroupOut,
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        output  o_RxEven,
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        output  reg o_RxCodeInvalid,
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        output  reg o_RxCodeCtrl,
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        output reg      o_SyncStatus,
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        output  o_BitSlip,
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        output  o_IsComma,
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        output  o_OrderedSetValid,
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        output  o_IsI1Set,
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        output  o_IsI2Set,
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        output  o_IsC1Set,
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        output  o_IsC2Set,
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        output  reg o_IsTSet,
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        output  reg o_IsVSet,
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        output  reg o_IsSSet,
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        output  reg o_IsRSet);
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localparam stLOSS_OF_SYNC               =       13'h0001;
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localparam stCOMMA_DTEC_1               =       13'h0002;
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localparam stACQ_SYNC_1                 =       13'h0004;
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localparam stCOMMA_DTEC_2               =       13'h0008;
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localparam stACQ_SYNC_2                 =       13'h0010;
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localparam stCOMMA_DTEC_3               =       13'h0020;
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localparam stSYNC_ACQUIRED_1    =       13'h0040;
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localparam stSYNC_ACQUIRED_2    =       13'h0080;
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localparam stSYNC_ACQUIRED_2A   =       13'h0100;
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localparam stSYNC_ACQUIRED_3    =       13'h0100;
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localparam stSYNC_ACQUIRED_3A   =       13'h0400;
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localparam stSYNC_ACQUIRED_4    =       13'h0800;
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localparam stSYNC_ACQUIRED_4A   =       13'h1000;
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reg     [12:00] r13_State;
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reg             r_RxEven;
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wire    w_SignalDetectChange;
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reg             r_LastSignalDetect;
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reg     [02:00] r3_GoodCgs;
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wire    w_CgBad;
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wire    w_IsComma;
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wire    w_IsData;
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reg             r_IsComma;
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wire    w_IsC1Set;
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wire    w_IsC2Set;
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wire    w_IsI1Set;
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wire    w_IsI2Set;
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wire    w_IsRSet;
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wire    w_IsSSet;
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wire    w_IsTSet;
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wire    w_IsVSet;
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reg             r_IsRSTV;
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wire [3:0] w4_ID1;
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reg      [3:0] r4_ID2;
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        //MainStatemachine
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        assign w_IsComma = (~i_RxCodeInvalid) && (i_RxCodeCtrl) && (i8_RxCodeGroupIn==8'hBC||i8_RxCodeGroupIn==8'h3C||i8_RxCodeGroupIn==8'hFC);
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        assign w_IsData  = (~i_RxCodeInvalid) && (~i_RxCodeCtrl);
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        assign w_CgBad  = i_RxCodeInvalid|(w_IsComma & r_RxEven);
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        assign w_SignalDetectChange = r_LastSignalDetect^i_SignalDetect;
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        always@(posedge i_Clk or negedge i_ARst_L)
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        begin: MainStatemachine
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                if(i_ARst_L==1'b0) begin
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                        r13_State <= stLOSS_OF_SYNC;
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                end
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                else if(i_Cke) begin
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                        r_LastSignalDetect <= i_SignalDetect;
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                        if(w_SignalDetectChange & (~i_RxCodeInvalid) & ~i_CtrlLoopBack)
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                                r13_State <= stLOSS_OF_SYNC;
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                        else
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                                case(r13_State)
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                                stLOSS_OF_SYNC          :       if(w_IsComma && (i_SignalDetect||i_CtrlLoopBack)) r13_State <= stCOMMA_DTEC_1;
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                                stCOMMA_DTEC_1          :       if(w_IsData) r13_State <= stACQ_SYNC_1; else r13_State <= stLOSS_OF_SYNC;
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                                stACQ_SYNC_1            :       if(w_CgBad) r13_State <= stLOSS_OF_SYNC; else
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                                                                                        if(r_RxEven==1'b0 && w_IsComma) r13_State <= stCOMMA_DTEC_2;
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                                stCOMMA_DTEC_2          :       if(w_IsData) r13_State <= stACQ_SYNC_2; else r13_State <= stLOSS_OF_SYNC;
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                                stACQ_SYNC_2            :       if(w_CgBad) r13_State <= stLOSS_OF_SYNC; else
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                                                                                        if(r_RxEven==1'b0 && w_IsComma) r13_State <= stCOMMA_DTEC_3;
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                                stCOMMA_DTEC_3          :       if(w_IsData) r13_State <= stSYNC_ACQUIRED_1; else r13_State <= stLOSS_OF_SYNC;
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                                stSYNC_ACQUIRED_1       :       if(w_CgBad) r13_State <= stSYNC_ACQUIRED_2;
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                                stSYNC_ACQUIRED_2       :       if(w_CgBad) r13_State <= stSYNC_ACQUIRED_3; else r13_State <= stSYNC_ACQUIRED_2A;
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                                stSYNC_ACQUIRED_2A      :       if(w_CgBad) r13_State <= stSYNC_ACQUIRED_3; else
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                                                                                        if(r3_GoodCgs==3) r13_State <= stSYNC_ACQUIRED_1;
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                                stSYNC_ACQUIRED_3       :       if(w_CgBad) r13_State <= stSYNC_ACQUIRED_4; else r13_State <= stSYNC_ACQUIRED_3A;
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                                stSYNC_ACQUIRED_3A      :       if(w_CgBad) r13_State <= stSYNC_ACQUIRED_4; else
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                                                                                        if(r3_GoodCgs==3) r13_State <= stSYNC_ACQUIRED_2;
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                                stSYNC_ACQUIRED_4       :       if(w_CgBad) r13_State <= stLOSS_OF_SYNC; else r13_State <= stSYNC_ACQUIRED_4A;
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                                stSYNC_ACQUIRED_4A      :       if(w_CgBad) r13_State <= stLOSS_OF_SYNC; else
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                                                                                        if(r3_GoodCgs==3) r13_State <= stSYNC_ACQUIRED_3;
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                                endcase
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                end
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        end
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        always@(posedge i_Clk or negedge i_ARst_L)
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        begin: SignalControl
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                if(i_ARst_L==1'b0) begin
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                        r_RxEven <= 1'b0;
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                end
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                else if(i_Cke) begin
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                        if((r13_State==stLOSS_OF_SYNC&&(w_IsComma && (i_SignalDetect||i_CtrlLoopBack)))||
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                                        ((r13_State==stACQ_SYNC_1||r13_State==stACQ_SYNC_2)&&(r_RxEven==1'b0 && w_IsComma)))
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                                        r_RxEven<=1'b1;
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                        else
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                                r_RxEven <= ~r_RxEven;
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                        if(r13_State==stSYNC_ACQUIRED_1)
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                                o_SyncStatus <= 1'b1;
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                        else if(r13_State==stLOSS_OF_SYNC)
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                                o_SyncStatus <= 1'b0;
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                        if(r13_State==stSYNC_ACQUIRED_2A||r13_State==stSYNC_ACQUIRED_3A||r13_State==stSYNC_ACQUIRED_4A)
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                                r3_GoodCgs <= r3_GoodCgs+3'h1;
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                        else if(r13_State==stSYNC_ACQUIRED_2||r13_State==stSYNC_ACQUIRED_3||r13_State==stSYNC_ACQUIRED_4)
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                                r3_GoodCgs <= 3'h0;
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                        o8_RxCodeGroupOut <= i8_RxCodeGroupIn;
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                        o_RxCodeInvalid <= i_RxCodeInvalid;
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                        o_RxCodeCtrl    <= i_RxCodeCtrl;
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                end
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        end
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        assign o_RxEven = r_RxEven;
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        //ordered set detection
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        assign o_OrderedSetValid = r_IsComma | r_IsRSTV;
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        assign w_IsC1Set = r_IsComma && w_IsData && (i8_RxCodeGroupIn==`D21_5);
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        assign w_IsC2Set = r_IsComma && w_IsData && (i8_RxCodeGroupIn==`D2_2);
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        assign w_IsI1Set = r_IsComma && w_IsData && (i8_RxCodeGroupIn==`D5_6);
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        assign w_IsI2Set = r_IsComma && w_IsData && (i8_RxCodeGroupIn==`D16_2);
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        assign w_IsRSet  = i_RxCodeCtrl && (~i_RxCodeInvalid) && (i8_RxCodeGroupIn==`K23_7);
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        assign w_IsSSet  = i_RxCodeCtrl && (~i_RxCodeInvalid) && (i8_RxCodeGroupIn==`K27_7);
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        assign w_IsTSet  = i_RxCodeCtrl && (~i_RxCodeInvalid) && (i8_RxCodeGroupIn==`K29_7);
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        assign w_IsVSet  = i_RxCodeCtrl && (~i_RxCodeInvalid) && (i8_RxCodeGroupIn==`K30_7);
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        assign o_IsC1Set = w_IsC1Set;
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        assign o_IsC2Set = w_IsC2Set;
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        assign o_IsI1Set = w_IsI1Set;
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        assign o_IsI2Set = w_IsI2Set;
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        assign o_IsComma = r_IsComma;
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        always@(posedge i_Clk or negedge i_ARst_L )
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        if(!i_ARst_L) begin
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                r_IsComma <= 1'b0;
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                r_IsRSTV <= 1'b0;
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        end else begin
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                r_IsComma <= w_IsComma;
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                r_IsRSTV <= w_IsRSet | w_IsSSet | w_IsTSet | w_IsVSet;
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                o_IsRSet <= w_IsRSet;
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                o_IsSSet <= w_IsSSet;
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                o_IsTSet <= w_IsTSet;
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                o_IsVSet <= w_IsVSet;
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        end
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        //synthesis translate_off
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        reg [239:0] r240_SyncStateName;
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        always@(*)
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        case(r13_State)
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        stLOSS_OF_SYNC          : r240_SyncStateName<="stLOSS_OF_SYNC           ";
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        stCOMMA_DTEC_1          : r240_SyncStateName<="stCOMMA_DTEC_1           ";
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        stACQ_SYNC_1            : r240_SyncStateName<="stACQ_SYNC_1                     ";
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        stCOMMA_DTEC_2          : r240_SyncStateName<="stCOMMA_DTEC_2           ";
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        stACQ_SYNC_2            : r240_SyncStateName<="stACQ_SYNC_2                     ";
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        stCOMMA_DTEC_3          : r240_SyncStateName<="stCOMMA_DTEC_3           ";
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        stSYNC_ACQUIRED_1       : r240_SyncStateName<="stSYNC_ACQUIRED_1        ";
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        stSYNC_ACQUIRED_2       : r240_SyncStateName<="stSYNC_ACQUIRED_2        ";
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        stSYNC_ACQUIRED_2A      : r240_SyncStateName<="stSYNC_ACQUIRED_2A       ";
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        stSYNC_ACQUIRED_3       : r240_SyncStateName<="stSYNC_ACQUIRED_3        ";
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        stSYNC_ACQUIRED_3A      : r240_SyncStateName<="stSYNC_ACQUIRED_3A       ";
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        stSYNC_ACQUIRED_4       : r240_SyncStateName<="stSYNC_ACQUIRED_4        ";
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        stSYNC_ACQUIRED_4A      : r240_SyncStateName<="stSYNC_ACQUIRED_4A       ";
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        endcase
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        //synthesis translate_on
190 13 jefflieu
        reg [3:0] r7_SlipTmr =0;
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        always@(posedge i_Clk or negedge i_ARst_L)
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        if(~i_ARst_L)
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                r7_SlipTmr  <= 7'h0;
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        else begin
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                if(r13_State==stLOSS_OF_SYNC) begin
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                        if(w_IsComma) r7_SlipTmr <= 0;
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                        else r7_SlipTmr <= r7_SlipTmr+7'h1;
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                        end
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                else r7_SlipTmr <= 0;
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                end
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        assign o_BitSlip = &r7_SlipTmr[3:0];
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204 2 jefflieu
endmodule

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