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/*
Developed By Subtleware Corporation Pte Ltd 2011
File            :
Description     :
Remarks         :
Revision        :
        Date    Author          Description
02/09/12        Jefflieu
*/
 
`include "SGMIIDefs.v"
module mSyncCtrl (
        input   i_Clk,
        input   i_Cke,
        input   i_ARst_L,
        input   i_CtrlLoopBack,
 
        input   [07:00] i8_RxCodeGroupIn,
        input   i_RxCodeInvalid,
        input   i_RxCodeCtrl,
        input   i_SignalDetect,
        output reg      [07:00] o8_RxCodeGroupOut,
        output  o_RxEven,
        output  reg o_RxCodeInvalid,
        output  reg o_RxCodeCtrl,
        output reg      o_SyncStatus,
        output  o_BitSlip,
        output  o_IsComma,
        output  o_OrderedSetValid,
        output  o_IsI1Set,
        output  o_IsI2Set,
        output  o_IsC1Set,
        output  o_IsC2Set,
        output  reg o_IsTSet,
        output  reg o_IsVSet,
        output  reg o_IsSSet,
        output  reg o_IsRSet);
 
localparam stLOSS_OF_SYNC               =       13'h0001;
localparam stCOMMA_DTEC_1               =       13'h0002;
localparam stACQ_SYNC_1                 =       13'h0004;
localparam stCOMMA_DTEC_2               =       13'h0008;
localparam stACQ_SYNC_2                 =       13'h0010;
localparam stCOMMA_DTEC_3               =       13'h0020;
localparam stSYNC_ACQUIRED_1    =       13'h0040;
localparam stSYNC_ACQUIRED_2    =       13'h0080;
localparam stSYNC_ACQUIRED_2A   =       13'h0100;
localparam stSYNC_ACQUIRED_3    =       13'h0100;
localparam stSYNC_ACQUIRED_3A   =       13'h0400;
localparam stSYNC_ACQUIRED_4    =       13'h0800;
localparam stSYNC_ACQUIRED_4A   =       13'h1000;
 
reg     [12:00] r13_State;
reg             r_RxEven;
wire    w_SignalDetectChange;
reg             r_LastSignalDetect;
reg     [02:00] r3_GoodCgs;
wire    w_CgBad;
wire    w_IsComma;
wire    w_IsData;
reg             r_IsComma;
wire    w_IsC1Set;
wire    w_IsC2Set;
wire    w_IsI1Set;
wire    w_IsI2Set;
wire    w_IsRSet;
wire    w_IsSSet;
wire    w_IsTSet;
wire    w_IsVSet;
reg             r_IsRSTV;
wire [3:0] w4_ID1;
reg      [3:0] r4_ID2;
 
        //MainStatemachine
        assign w_IsComma = (~i_RxCodeInvalid) && (i_RxCodeCtrl) && (i8_RxCodeGroupIn==8'hBC||i8_RxCodeGroupIn==8'h3C||i8_RxCodeGroupIn==8'hFC);
        assign w_IsData  = (~i_RxCodeInvalid) && (~i_RxCodeCtrl);
        assign w_CgBad  = i_RxCodeInvalid|(w_IsComma & r_RxEven);
        assign w_SignalDetectChange = r_LastSignalDetect^i_SignalDetect;
        always@(posedge i_Clk or negedge i_ARst_L)
        begin: MainStatemachine
                if(i_ARst_L==1'b0) begin
                        r13_State <= stLOSS_OF_SYNC;
                end
                else if(i_Cke) begin
                        r_LastSignalDetect <= i_SignalDetect;
                        if(w_SignalDetectChange & (~i_RxCodeInvalid) & ~i_CtrlLoopBack)
                                r13_State <= stLOSS_OF_SYNC;
                        else
                                case(r13_State)
                                stLOSS_OF_SYNC          :       if(w_IsComma && (i_SignalDetect||i_CtrlLoopBack)) r13_State <= stCOMMA_DTEC_1;
                                stCOMMA_DTEC_1          :       if(w_IsData) r13_State <= stACQ_SYNC_1; else r13_State <= stLOSS_OF_SYNC;
                                stACQ_SYNC_1            :       if(w_CgBad) r13_State <= stLOSS_OF_SYNC; else
                                                                                        if(r_RxEven==1'b0 && w_IsComma) r13_State <= stCOMMA_DTEC_2;
                                stCOMMA_DTEC_2          :       if(w_IsData) r13_State <= stACQ_SYNC_2; else r13_State <= stLOSS_OF_SYNC;
                                stACQ_SYNC_2            :       if(w_CgBad) r13_State <= stLOSS_OF_SYNC; else
                                                                                        if(r_RxEven==1'b0 && w_IsComma) r13_State <= stCOMMA_DTEC_3;
                                stCOMMA_DTEC_3          :       if(w_IsData) r13_State <= stSYNC_ACQUIRED_1; else r13_State <= stLOSS_OF_SYNC;
                                stSYNC_ACQUIRED_1       :       if(w_CgBad) r13_State <= stSYNC_ACQUIRED_2;
                                stSYNC_ACQUIRED_2       :       if(w_CgBad) r13_State <= stSYNC_ACQUIRED_3; else r13_State <= stSYNC_ACQUIRED_2A;
                                stSYNC_ACQUIRED_2A      :       if(w_CgBad) r13_State <= stSYNC_ACQUIRED_3; else
                                                                                        if(r3_GoodCgs==3) r13_State <= stSYNC_ACQUIRED_1;
                                stSYNC_ACQUIRED_3       :       if(w_CgBad) r13_State <= stSYNC_ACQUIRED_4; else r13_State <= stSYNC_ACQUIRED_3A;
                                stSYNC_ACQUIRED_3A      :       if(w_CgBad) r13_State <= stSYNC_ACQUIRED_4; else
                                                                                        if(r3_GoodCgs==3) r13_State <= stSYNC_ACQUIRED_2;
                                stSYNC_ACQUIRED_4       :       if(w_CgBad) r13_State <= stLOSS_OF_SYNC; else r13_State <= stSYNC_ACQUIRED_4A;
                                stSYNC_ACQUIRED_4A      :       if(w_CgBad) r13_State <= stLOSS_OF_SYNC; else
                                                                                        if(r3_GoodCgs==3) r13_State <= stSYNC_ACQUIRED_3;
                                endcase
                end
        end
 
        always@(posedge i_Clk or negedge i_ARst_L)
        begin: SignalControl
                if(i_ARst_L==1'b0) begin
                        r_RxEven <= 1'b0;
                end
                else if(i_Cke) begin
                        if((r13_State==stLOSS_OF_SYNC&&(w_IsComma && (i_SignalDetect||i_CtrlLoopBack)))||
                                        ((r13_State==stACQ_SYNC_1||r13_State==stACQ_SYNC_2)&&(r_RxEven==1'b0 && w_IsComma)))
                                        r_RxEven<=1'b1;
                        else
                                r_RxEven <= ~r_RxEven;
                        if(r13_State==stSYNC_ACQUIRED_1)
                                o_SyncStatus <= 1'b1;
                        else if(r13_State==stLOSS_OF_SYNC)
                                o_SyncStatus <= 1'b0;
 
                        if(r13_State==stSYNC_ACQUIRED_2A||r13_State==stSYNC_ACQUIRED_3A||r13_State==stSYNC_ACQUIRED_4A)
                                r3_GoodCgs <= r3_GoodCgs+3'h1;
                        else if(r13_State==stSYNC_ACQUIRED_2||r13_State==stSYNC_ACQUIRED_3||r13_State==stSYNC_ACQUIRED_4)
                                r3_GoodCgs <= 3'h0;
 
                        o8_RxCodeGroupOut <= i8_RxCodeGroupIn;
                        o_RxCodeInvalid <= i_RxCodeInvalid;
                        o_RxCodeCtrl    <= i_RxCodeCtrl;
                end
        end
 
        assign o_RxEven = r_RxEven;
 
        //ordered set detection
        assign o_OrderedSetValid = r_IsComma | r_IsRSTV;
        assign w_IsC1Set = r_IsComma && w_IsData && (i8_RxCodeGroupIn==`D21_5);
        assign w_IsC2Set = r_IsComma && w_IsData && (i8_RxCodeGroupIn==`D2_2);
        assign w_IsI1Set = r_IsComma && w_IsData && (i8_RxCodeGroupIn==`D5_6);
        assign w_IsI2Set = r_IsComma && w_IsData && (i8_RxCodeGroupIn==`D16_2);
        assign w_IsRSet  = i_RxCodeCtrl && (~i_RxCodeInvalid) && (i8_RxCodeGroupIn==`K23_7);
        assign w_IsSSet  = i_RxCodeCtrl && (~i_RxCodeInvalid) && (i8_RxCodeGroupIn==`K27_7);
        assign w_IsTSet  = i_RxCodeCtrl && (~i_RxCodeInvalid) && (i8_RxCodeGroupIn==`K29_7);
        assign w_IsVSet  = i_RxCodeCtrl && (~i_RxCodeInvalid) && (i8_RxCodeGroupIn==`K30_7);
 
        assign o_IsC1Set = w_IsC1Set;
        assign o_IsC2Set = w_IsC2Set;
        assign o_IsI1Set = w_IsI1Set;
        assign o_IsI2Set = w_IsI2Set;
        assign o_IsComma = r_IsComma;
 
        always@(posedge i_Clk or negedge i_ARst_L )
        if(!i_ARst_L) begin
                r_IsComma <= 1'b0;
                r_IsRSTV <= 1'b0;
        end else begin
                r_IsComma <= w_IsComma;
                r_IsRSTV <= w_IsRSet | w_IsSSet | w_IsTSet | w_IsVSet;
                o_IsRSet <= w_IsRSet;
                o_IsSSet <= w_IsSSet;
                o_IsTSet <= w_IsTSet;
                o_IsVSet <= w_IsVSet;
        end
 
        //synthesis translate_off
        reg [239:0] r240_SyncStateName;
        always@(*)
        case(r13_State)
        stLOSS_OF_SYNC          : r240_SyncStateName<="stLOSS_OF_SYNC           ";
        stCOMMA_DTEC_1          : r240_SyncStateName<="stCOMMA_DTEC_1           ";
        stACQ_SYNC_1            : r240_SyncStateName<="stACQ_SYNC_1                     ";
        stCOMMA_DTEC_2          : r240_SyncStateName<="stCOMMA_DTEC_2           ";
        stACQ_SYNC_2            : r240_SyncStateName<="stACQ_SYNC_2                     ";
        stCOMMA_DTEC_3          : r240_SyncStateName<="stCOMMA_DTEC_3           ";
        stSYNC_ACQUIRED_1       : r240_SyncStateName<="stSYNC_ACQUIRED_1        ";
        stSYNC_ACQUIRED_2       : r240_SyncStateName<="stSYNC_ACQUIRED_2        ";
        stSYNC_ACQUIRED_2A      : r240_SyncStateName<="stSYNC_ACQUIRED_2A       ";
        stSYNC_ACQUIRED_3       : r240_SyncStateName<="stSYNC_ACQUIRED_3        ";
        stSYNC_ACQUIRED_3A      : r240_SyncStateName<="stSYNC_ACQUIRED_3A       ";
        stSYNC_ACQUIRED_4       : r240_SyncStateName<="stSYNC_ACQUIRED_4        ";
        stSYNC_ACQUIRED_4A      : r240_SyncStateName<="stSYNC_ACQUIRED_4A       ";
        endcase
        //synthesis translate_on
 
endmodule

Line No.	Rev	Author	Line
1	2	jefflieu	`/*`
2			`Developed By Subtleware Corporation Pte Ltd 2011`
3			`File :`
4			`Description :`
5			`Remarks :`
6			`Revision :`
7			`Date Author Description`
8			`02/09/12 Jefflieu`
9			`*/`
10
11			`include "SGMIIDefs.v"
12			`module mSyncCtrl (`
13			`input i_Clk,`
14			`input i_Cke,`
15			`input i_ARst_L,`
16			`input i_CtrlLoopBack,`
17
18			`input [07:00] i8_RxCodeGroupIn,`
19			`input i_RxCodeInvalid,`
20			`input i_RxCodeCtrl,`
21			`input i_SignalDetect,`
22			`output reg [07:00] o8_RxCodeGroupOut,`
23			`output o_RxEven,`
24			`output reg o_RxCodeInvalid,`
25			`output reg o_RxCodeCtrl,`
26			`output reg o_SyncStatus,`
27			`output o_BitSlip,`
28			`output o_IsComma,`
29			`output o_OrderedSetValid,`
30			`output o_IsI1Set,`
31			`output o_IsI2Set,`
32			`output o_IsC1Set,`
33			`output o_IsC2Set,`
34			`output reg o_IsTSet,`
35			`output reg o_IsVSet,`
36			`output reg o_IsSSet,`
37			`output reg o_IsRSet);`
38
39			`localparam stLOSS_OF_SYNC = 13'h0001;`
40			`localparam stCOMMA_DTEC_1 = 13'h0002;`
41			`localparam stACQ_SYNC_1 = 13'h0004;`
42			`localparam stCOMMA_DTEC_2 = 13'h0008;`
43			`localparam stACQ_SYNC_2 = 13'h0010;`
44			`localparam stCOMMA_DTEC_3 = 13'h0020;`
45			`localparam stSYNC_ACQUIRED_1 = 13'h0040;`
46			`localparam stSYNC_ACQUIRED_2 = 13'h0080;`
47			`localparam stSYNC_ACQUIRED_2A = 13'h0100;`
48			`localparam stSYNC_ACQUIRED_3 = 13'h0100;`
49			`localparam stSYNC_ACQUIRED_3A = 13'h0400;`
50			`localparam stSYNC_ACQUIRED_4 = 13'h0800;`
51			`localparam stSYNC_ACQUIRED_4A = 13'h1000;`
52
53			`reg [12:00] r13_State;`
54			`reg r_RxEven;`
55			`wire w_SignalDetectChange;`
56			`reg r_LastSignalDetect;`
57			`reg [02:00] r3_GoodCgs;`
58			`wire w_CgBad;`
59			`wire w_IsComma;`
60			`wire w_IsData;`
61			`reg r_IsComma;`
62			`wire w_IsC1Set;`
63			`wire w_IsC2Set;`
64			`wire w_IsI1Set;`
65			`wire w_IsI2Set;`
66			`wire w_IsRSet;`
67			`wire w_IsSSet;`
68			`wire w_IsTSet;`
69			`wire w_IsVSet;`
70			`reg r_IsRSTV;`
71			`wire [3:0] w4_ID1;`
72			`reg [3:0] r4_ID2;`
73
74			`//MainStatemachine`
75			`assign w_IsComma = (~i_RxCodeInvalid) && (i_RxCodeCtrl) && (i8_RxCodeGroupIn==8'hBC\|\|i8_RxCodeGroupIn==8'h3C\|\|i8_RxCodeGroupIn==8'hFC);`
76			`assign w_IsData = (~i_RxCodeInvalid) && (~i_RxCodeCtrl);`
77			`assign w_CgBad = i_RxCodeInvalid\|(w_IsComma & r_RxEven);`
78			`assign w_SignalDetectChange = r_LastSignalDetect^i_SignalDetect;`
79			`always@(posedge i_Clk or negedge i_ARst_L)`
80			`begin: MainStatemachine`
81			`if(i_ARst_L==1'b0) begin`
82			`r13_State <= stLOSS_OF_SYNC;`
83			`end`
84			`else if(i_Cke) begin`
85			`r_LastSignalDetect <= i_SignalDetect;`
86			`if(w_SignalDetectChange & (~i_RxCodeInvalid) & ~i_CtrlLoopBack)`
87			`r13_State <= stLOSS_OF_SYNC;`
88			`else`
89			`case(r13_State)`
90			`stLOSS_OF_SYNC : if(w_IsComma && (i_SignalDetect\|\|i_CtrlLoopBack)) r13_State <= stCOMMA_DTEC_1;`
91			`stCOMMA_DTEC_1 : if(w_IsData) r13_State <= stACQ_SYNC_1; else r13_State <= stLOSS_OF_SYNC;`
92			`stACQ_SYNC_1 : if(w_CgBad) r13_State <= stLOSS_OF_SYNC; else`
93			`if(r_RxEven==1'b0 && w_IsComma) r13_State <= stCOMMA_DTEC_2;`
94			`stCOMMA_DTEC_2 : if(w_IsData) r13_State <= stACQ_SYNC_2; else r13_State <= stLOSS_OF_SYNC;`
95			`stACQ_SYNC_2 : if(w_CgBad) r13_State <= stLOSS_OF_SYNC; else`
96			`if(r_RxEven==1'b0 && w_IsComma) r13_State <= stCOMMA_DTEC_3;`
97			`stCOMMA_DTEC_3 : if(w_IsData) r13_State <= stSYNC_ACQUIRED_1; else r13_State <= stLOSS_OF_SYNC;`
98			`stSYNC_ACQUIRED_1 : if(w_CgBad) r13_State <= stSYNC_ACQUIRED_2;`
99			`stSYNC_ACQUIRED_2 : if(w_CgBad) r13_State <= stSYNC_ACQUIRED_3; else r13_State <= stSYNC_ACQUIRED_2A;`
100			`stSYNC_ACQUIRED_2A : if(w_CgBad) r13_State <= stSYNC_ACQUIRED_3; else`
101			`if(r3_GoodCgs==3) r13_State <= stSYNC_ACQUIRED_1;`
102			`stSYNC_ACQUIRED_3 : if(w_CgBad) r13_State <= stSYNC_ACQUIRED_4; else r13_State <= stSYNC_ACQUIRED_3A;`
103			`stSYNC_ACQUIRED_3A : if(w_CgBad) r13_State <= stSYNC_ACQUIRED_4; else`
104			`if(r3_GoodCgs==3) r13_State <= stSYNC_ACQUIRED_2;`
105			`stSYNC_ACQUIRED_4 : if(w_CgBad) r13_State <= stLOSS_OF_SYNC; else r13_State <= stSYNC_ACQUIRED_4A;`
106			`stSYNC_ACQUIRED_4A : if(w_CgBad) r13_State <= stLOSS_OF_SYNC; else`
107			`if(r3_GoodCgs==3) r13_State <= stSYNC_ACQUIRED_3;`
108			`endcase`
109			`end`
110			`end`
111
112			`always@(posedge i_Clk or negedge i_ARst_L)`
113			`begin: SignalControl`
114			`if(i_ARst_L==1'b0) begin`
115			`r_RxEven <= 1'b0;`
116			`end`
117			`else if(i_Cke) begin`
118			`if((r13_State==stLOSS_OF_SYNC&&(w_IsComma && (i_SignalDetect\|\|i_CtrlLoopBack)))\|\|`
119			`((r13_State==stACQ_SYNC_1\|\|r13_State==stACQ_SYNC_2)&&(r_RxEven==1'b0 && w_IsComma)))`
120			`r_RxEven<=1'b1;`
121			`else`
122			`r_RxEven <= ~r_RxEven;`
123			`if(r13_State==stSYNC_ACQUIRED_1)`
124			`o_SyncStatus <= 1'b1;`
125			`else if(r13_State==stLOSS_OF_SYNC)`
126			`o_SyncStatus <= 1'b0;`
127
128			`if(r13_State==stSYNC_ACQUIRED_2A\|\|r13_State==stSYNC_ACQUIRED_3A\|\|r13_State==stSYNC_ACQUIRED_4A)`
129			`r3_GoodCgs <= r3_GoodCgs+3'h1;`
130			`else if(r13_State==stSYNC_ACQUIRED_2\|\|r13_State==stSYNC_ACQUIRED_3\|\|r13_State==stSYNC_ACQUIRED_4)`
131			`r3_GoodCgs <= 3'h0;`
132
133			`o8_RxCodeGroupOut <= i8_RxCodeGroupIn;`
134			`o_RxCodeInvalid <= i_RxCodeInvalid;`
135			`o_RxCodeCtrl <= i_RxCodeCtrl;`
136			`end`
137			`end`
138
139			`assign o_RxEven = r_RxEven;`
140
141			`//ordered set detection`
142			`assign o_OrderedSetValid = r_IsComma \| r_IsRSTV;`
143			assign w_IsC1Set = r_IsComma && w_IsData && (i8_RxCodeGroupIn==`D21_5);
144			assign w_IsC2Set = r_IsComma && w_IsData && (i8_RxCodeGroupIn==`D2_2);
145			assign w_IsI1Set = r_IsComma && w_IsData && (i8_RxCodeGroupIn==`D5_6);
146			assign w_IsI2Set = r_IsComma && w_IsData && (i8_RxCodeGroupIn==`D16_2);
147			assign w_IsRSet = i_RxCodeCtrl && (~i_RxCodeInvalid) && (i8_RxCodeGroupIn==`K23_7);
148			assign w_IsSSet = i_RxCodeCtrl && (~i_RxCodeInvalid) && (i8_RxCodeGroupIn==`K27_7);
149			assign w_IsTSet = i_RxCodeCtrl && (~i_RxCodeInvalid) && (i8_RxCodeGroupIn==`K29_7);
150			assign w_IsVSet = i_RxCodeCtrl && (~i_RxCodeInvalid) && (i8_RxCodeGroupIn==`K30_7);
151
152			`assign o_IsC1Set = w_IsC1Set;`
153			`assign o_IsC2Set = w_IsC2Set;`
154			`assign o_IsI1Set = w_IsI1Set;`
155			`assign o_IsI2Set = w_IsI2Set;`
156			`assign o_IsComma = r_IsComma;`
157
158			`always@(posedge i_Clk or negedge i_ARst_L )`
159			`if(!i_ARst_L) begin`
160			`r_IsComma <= 1'b0;`
161			`r_IsRSTV <= 1'b0;`
162			`end else begin`
163			`r_IsComma <= w_IsComma;`
164			`r_IsRSTV <= w_IsRSet \| w_IsSSet \| w_IsTSet \| w_IsVSet;`
165			`o_IsRSet <= w_IsRSet;`
166			`o_IsSSet <= w_IsSSet;`
167			`o_IsTSet <= w_IsTSet;`
168			`o_IsVSet <= w_IsVSet;`
169			`end`
170
171			`//synthesis translate_off`
172			`reg [239:0] r240_SyncStateName;`
173			`always@(*)`
174			`case(r13_State)`
175			`stLOSS_OF_SYNC : r240_SyncStateName<="stLOSS_OF_SYNC ";`
176			`stCOMMA_DTEC_1 : r240_SyncStateName<="stCOMMA_DTEC_1 ";`
177			`stACQ_SYNC_1 : r240_SyncStateName<="stACQ_SYNC_1 ";`
178			`stCOMMA_DTEC_2 : r240_SyncStateName<="stCOMMA_DTEC_2 ";`
179			`stACQ_SYNC_2 : r240_SyncStateName<="stACQ_SYNC_2 ";`
180			`stCOMMA_DTEC_3 : r240_SyncStateName<="stCOMMA_DTEC_3 ";`
181			`stSYNC_ACQUIRED_1 : r240_SyncStateName<="stSYNC_ACQUIRED_1 ";`
182			`stSYNC_ACQUIRED_2 : r240_SyncStateName<="stSYNC_ACQUIRED_2 ";`
183			`stSYNC_ACQUIRED_2A : r240_SyncStateName<="stSYNC_ACQUIRED_2A ";`
184			`stSYNC_ACQUIRED_3 : r240_SyncStateName<="stSYNC_ACQUIRED_3 ";`
185			`stSYNC_ACQUIRED_3A : r240_SyncStateName<="stSYNC_ACQUIRED_3A ";`
186			`stSYNC_ACQUIRED_4 : r240_SyncStateName<="stSYNC_ACQUIRED_4 ";`
187			`stSYNC_ACQUIRED_4A : r240_SyncStateName<="stSYNC_ACQUIRED_4A ";`
188			`endcase`
189			`//synthesis translate_on`
190
191			`endmodule`

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[/] [sgmii/] [trunk/] [src/] [mSyncCtrl.v] - Blame information for rev 2