| 1 |
2 |
jefflieu |
/*
|
| 2 |
|
|
Developed By Subtleware Corporation Pte Ltd 2011
|
| 3 |
|
|
File :
|
| 4 |
|
|
Description :
|
| 5 |
|
|
Remarks :
|
| 6 |
|
|
Revision :
|
| 7 |
|
|
Date Author Description
|
| 8 |
|
|
*/
|
| 9 |
|
|
|
| 10 |
|
|
module mXcver #(parameter pXcverName="AltCycIV") (
|
| 11 |
|
|
|
| 12 |
|
|
input i_SerRx,
|
| 13 |
|
|
output o_SerTx,
|
| 14 |
|
|
|
| 15 |
|
|
input i_RefClk125M,
|
| 16 |
|
|
output o_TxClk,
|
| 17 |
|
|
input i_CalClk,
|
| 18 |
|
|
input i_GxBPwrDwn,
|
| 19 |
|
|
input i_XcverDigitalRst,
|
| 20 |
|
|
output o_PllLocked,
|
| 21 |
|
|
output o_SignalDetect,
|
| 22 |
|
|
output [07:00] o8_RxCodeGroup,
|
| 23 |
|
|
output o_RxCodeInvalid,
|
| 24 |
|
|
output o_RxCodeCtrl,
|
| 25 |
|
|
|
| 26 |
|
|
input [07:00] i8_TxCodeGroup,
|
| 27 |
|
|
input i_TxCodeValid,
|
| 28 |
|
|
input i_TxCodeCtrl,
|
| 29 |
|
|
input i_TxForceNegDisp,
|
| 30 |
|
|
output o_RunningDisparity);
|
| 31 |
|
|
|
| 32 |
|
|
|
| 33 |
|
|
|
| 34 |
|
|
generate
|
| 35 |
16 |
jefflieu |
if(pXcverName=="AltCycIV")
|
| 36 |
|
|
begin:AltCycIVXcver
|
| 37 |
2 |
jefflieu |
wire [04:00] w5_ReconfigFromGxb;
|
| 38 |
|
|
wire [03:00] w4_ReconfigToGxb;
|
| 39 |
|
|
wire w_Reconfiguring;
|
| 40 |
|
|
mAltGX u0AltGX (
|
| 41 |
|
|
.cal_blk_clk (i_CalClk),
|
| 42 |
|
|
.gxb_powerdown (i_GxBPwrDwn),
|
| 43 |
|
|
.pll_inclk (i_RefClk125M),
|
| 44 |
|
|
.reconfig_clk (i_CalClk),
|
| 45 |
|
|
.reconfig_togxb (w4_ReconfigToGxb),
|
| 46 |
|
|
.rx_analogreset (1'b0),
|
| 47 |
|
|
.pll_locked (o_PllLocked),
|
| 48 |
|
|
.reconfig_fromgxb (w5_ReconfigFromGxb),
|
| 49 |
|
|
|
| 50 |
|
|
.rx_digitalreset (i_XcverDigitalRst),
|
| 51 |
|
|
.rx_datain (i_SerRx),
|
| 52 |
|
|
.tx_dataout (o_SerTx),
|
| 53 |
|
|
|
| 54 |
|
|
.tx_ctrlenable (i_TxCodeCtrl),
|
| 55 |
|
|
.tx_datain (i8_TxCodeGroup),
|
| 56 |
|
|
.tx_digitalreset (i_XcverDigitalRst),
|
| 57 |
|
|
|
| 58 |
|
|
.rx_errdetect (o_RxCodeInvalid),
|
| 59 |
|
|
.rx_ctrldetect (o_RxCodeCtrl),
|
| 60 |
|
|
.rx_dataout (o8_RxCodeGroup),
|
| 61 |
|
|
.rx_disperr (),
|
| 62 |
|
|
.rx_patterndetect (),
|
| 63 |
|
|
.rx_rlv (),
|
| 64 |
|
|
.rx_syncstatus (o_SignalDetect),
|
| 65 |
|
|
.tx_clkout (o_TxClk));
|
| 66 |
|
|
|
| 67 |
|
|
assign o_RunningDisparity = 1'b0;
|
| 68 |
|
|
|
| 69 |
|
|
mAltGXReconfig u0AltGXReconfig(
|
| 70 |
|
|
.reconfig_clk (i_CalClk),
|
| 71 |
|
|
.reconfig_fromgxb (w5_ReconfigFromGxb),
|
| 72 |
|
|
.busy (w_Reconfiguring),
|
| 73 |
|
|
.reconfig_togxb (w4_ReconfigToGxb));
|
| 74 |
|
|
end
|
| 75 |
|
|
endgenerate
|
| 76 |
|
|
|
| 77 |
|
|
|
| 78 |
16 |
jefflieu |
generate
|
| 79 |
|
|
if(pXcverName=="AltArriaV")
|
| 80 |
|
|
begin:AltArriaVXcver
|
| 81 |
|
|
wire [091:00] w92_ReconfigFromGxb;
|
| 82 |
|
|
wire [139:00] w140_ReconfigToGxb;
|
| 83 |
|
|
wire w_Reconfiguring;
|
| 84 |
|
|
mAltAvgxXcver uAltXCver(
|
| 85 |
|
|
.phy_mgmt_clk (i_RefClk125M), // phy_mgmt_clk.clk
|
| 86 |
|
|
.phy_mgmt_clk_reset (1'b0), // phy_mgmt_clk_reset.reset
|
| 87 |
|
|
.phy_mgmt_address (8'h0), // phy_mgmt.address
|
| 88 |
|
|
.phy_mgmt_read (1'b0), // .read
|
| 89 |
|
|
.phy_mgmt_readdata (), // .readdata
|
| 90 |
|
|
.phy_mgmt_waitrequest (), // .waitrequest
|
| 91 |
|
|
.phy_mgmt_write (1'b0), // .write
|
| 92 |
|
|
.phy_mgmt_writedata (32'h0), // .writedata
|
| 93 |
|
|
.tx_ready (), // tx_ready.export
|
| 94 |
|
|
.rx_ready (), // rx_ready.export
|
| 95 |
|
|
.pll_ref_clk (i_RefClk125M), // pll_ref_clk.clk
|
| 96 |
|
|
.tx_serial_data (o_SerTx), // tx_serial_data.export
|
| 97 |
|
|
.pll_locked (o_PllLocked), // pll_locked.export
|
| 98 |
|
|
.rx_serial_data (i_SerRx), // rx_serial_data.export
|
| 99 |
|
|
.rx_runningdisp (o_RunningDisparity), // rx_runningdisp.export
|
| 100 |
|
|
.rx_patterndetect (w_PatternDtec), // rx_patterndetect.export
|
| 101 |
|
|
.rx_disperr (w_DispErr), // rx_disperr.export
|
| 102 |
|
|
.rx_errdetect (w_ErrDtec), // rx_errdetect.export
|
| 103 |
|
|
.rx_syncstatus (w_SyncStatus), // rx_syncstatus.export
|
| 104 |
|
|
.tx_clkout (o_TxClk), // tx_clkout.export
|
| 105 |
|
|
.rx_clkout (), // rx_clkout.export
|
| 106 |
|
|
.tx_parallel_data (i8_TxCodeGroup), // tx_parallel_data.export
|
| 107 |
|
|
.tx_datak (i_TxCodeCtrl), // tx_datak.export
|
| 108 |
|
|
.rx_parallel_data (o8_RxCodeGroup), // rx_parallel_data.export
|
| 109 |
|
|
.rx_datak (o_RxCodeCtrl), // rx_datak.export
|
| 110 |
|
|
.reconfig_from_xcvr (w92_ReconfigFromGxb), // reconfig_from_xcvr.reconfig_from_xcvr
|
| 111 |
|
|
.reconfig_to_xcvr (w140_ReconfigToGxb) // reconfig_to_xcvr.reconfig_to_xcvr
|
| 112 |
|
|
);
|
| 113 |
|
|
assign o_SignalDetect = ~(w_ErrDtec|w_DispErr);
|
| 114 |
|
|
assign o_RxCodeInvalid = w_ErrDtec;
|
| 115 |
|
|
|
| 116 |
|
|
mAltAvgxReconfig uReconfig(
|
| 117 |
|
|
.reconfig_busy (w_Reconfiguring), // reconfig_busy.reconfig_busy
|
| 118 |
|
|
.mgmt_clk_clk (i_CalClk), // mgmt_clk_clk.clk
|
| 119 |
|
|
.mgmt_rst_reset (i_XcverDigitalRst), // mgmt_rst_reset.reset
|
| 120 |
|
|
.reconfig_mgmt_address (8'h0), // reconfig_mgmt.address
|
| 121 |
|
|
.reconfig_mgmt_read (1'b0), // .read
|
| 122 |
|
|
.reconfig_mgmt_readdata (), // .readdata
|
| 123 |
|
|
.reconfig_mgmt_waitrequest (), // .waitrequest
|
| 124 |
|
|
.reconfig_mgmt_write (1'b0), // .write
|
| 125 |
|
|
.reconfig_mgmt_writedata (32'h0), // .writedata
|
| 126 |
|
|
.reconfig_to_xcvr (w140_ReconfigToGxb),// reconfig_to_xcvr.reconfig_to_xcvr
|
| 127 |
|
|
.reconfig_from_xcvr (w92_ReconfigFromGxb)// reconfig_from_xcvr.reconfig_from_xcvr
|
| 128 |
|
|
);
|
| 129 |
|
|
|
| 130 |
|
|
end
|
| 131 |
|
|
endgenerate
|
| 132 |
2 |
jefflieu |
|
| 133 |
|
|
|
| 134 |
|
|
|
| 135 |
|
|
endmodule
|
