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[/] [sha256_hash_core/] [trunk/] [syn/] [.Xil/] [PlanAhead-2528-WIN-AQV6D9G23CA/] [ngc2edif/] [ngc2edif.log] - Blame information for rev 2

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Line No. Rev Author Line
1 2 jdoin 
Release 14.7 - ngc2edif P.20131013 (nt64)
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Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
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Reading design spi_master_atlys_top.ngc ...
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WARNING:NetListWriters:298 - No output is written to spi_master_atlys_top.xncf,
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   ignored.
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Processing design ...
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   Preping design's networks ...
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   Preping design's macros ...
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WARNING:NetListWriters:306 - Signal bus m_rx_data_3_reg<7 : 1> on block
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   spi_master_atlys_top is not reconstructed, because there are some missing bus
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   signals.
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WARNING:NetListWriters:306 - Signal bus s_rx_data_3_reg<7 : 1> on block
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   spi_master_atlys_top is not reconstructed, because there are some missing bus
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   signals.
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  finished :Prep
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Writing EDIF netlist file spi_master_atlys_top.edif ...
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ngc2edif: Total memory usage is 80108 kilobytes
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