URL https://opencores.org/ocsvn/sha256_hash_core/sha256_hash_core/trunk

Subversion Repositories sha256_hash_core

[/] [sha256_hash_core/] [trunk/] [syn/] [sha256/] [iseconfig/] [spi_master_atlys.projectmgr] - Blame information for rev 2

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         2
      
      
         spi_master_atlys_top - rtl (Z:/Dropbox/develop/fpga/spi_master_slave/trunk/syn/spi_master_atlys/spi_master_atlys_top.vhd)
      
      0
      0
      000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000031d000000020000000000000000000000000200000064ffffffff0000008100000003000000020000031d0000000100000003000000000000000100000003
      true
      spi_master_atlys_top - rtl (Z:/Dropbox/develop/fpga/spi_master_slave/trunk/syn/spi_master_atlys/spi_master_atlys_top.vhd)
   
   
      
         1
         Design Utilities
      
      
         
      
      0
      0
      000000ff0000000000000001000000010000000000000000000000000000000000000000000000018f000000010000000100000000000000000000000064ffffffff0000008100000000000000010000018f0000000100000000
      false
      
   
   
      
         1
      
      
         Z:\Dropbox\develop\fpga\spi_master_slave\trunk\syn\spi_master_atlys\gray_counter.vhd
      
      0
      0
      000000ff000000000000000100000000000000000100000000000000000000000000000000000003c5000000040101000100000000000000000000000064ffffffff0000008100000000000000040000021b00000001000000000000009d0000000100000000000000660000000100000000000000a70000000100000000
      false
      Z:\Dropbox\develop\fpga\spi_master_slave\trunk\syn\spi_master_atlys\gray_counter.vhd
   
   
      
         1
      
      
         Z:\Dropbox\develop\fpga\spi_master_slave\trunk\syn\spi_master_atlys\spi_master.vhd
      
      0
      0
      000000ff000000000000000100000000000000000100000000000000000000000000000000000003c5000000010001000100000000000000000000000064ffffffff000000810000000000000001000003c50000000100000000
      false
      Z:\Dropbox\develop\fpga\spi_master_slave\trunk\syn\spi_master_atlys\spi_master.vhd
   
   
      
         1
         User Constraints
      
      
         
      
      0
      0
      000000ff0000000000000001000000010000000000000000000000000000000000000000000000018f000000010000000100000000000000000000000064ffffffff0000008100000000000000010000018f0000000100000000
      false
      
   
   
      
         1
         Implement Design/Map/Generate Post-Map Static Timing
         Implement Design/Place & Route/Back-annotate Pin Locations
         Implement Design/Place & Route/Generate IBIS Model
      
      
         I/O Pin Planning (PlanAhead) - Post-Synthesis
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000000000000000003b4000000010000000100000000000000000000000064ffffffff000000810000000000000001000003b40000000100000000
      false
      I/O Pin Planning (PlanAhead) - Post-Synthesis
   
   000000ff00000000000000020000011b0000011b01000000050100000002
   Behavioral Simulation
   
      
         2
      
      
         testbench - behavior (Z:/Dropbox/develop/fpga/spi_master_slave/trunk/syn/spi_master_atlys/spi_master_atlys_test.vhd)
      
      0
      0
      000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000372000000020000000000000000000000000200000064ffffffff000000810000000300000002000003720000000100000003000000000000000100000003
      false
      testbench - behavior (Z:/Dropbox/develop/fpga/spi_master_slave/trunk/syn/spi_master_atlys/spi_master_atlys_test.vhd)
   
   
      
         1
      
      
         
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000000000000000003c5000000010000000100000000000000000000000064ffffffff000000810000000000000001000003c50000000100000000
      false
      
   
   
      
         1
      
      
         
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000000000000000003c5000000010000000100000000000000000000000064ffffffff000000810000000000000001000003c50000000100000000
      false
      
   


Line No.	Rev	Author	Line
1	2	jdoin
2
3
4
5
6
7
8
9			`2`
10
11
12			`spi_master_atlys_top - rtl (Z:/Dropbox/develop/fpga/spi_master_slave/trunk/syn/spi_master_atlys/spi_master_atlys_top.vhd)`
13
14			`0`
15			`0`
16			`000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000031d000000020000000000000000000000000200000064ffffffff0000008100000003000000020000031d0000000100000003000000000000000100000003`
17			`true`
18			`spi_master_atlys_top - rtl (Z:/Dropbox/develop/fpga/spi_master_slave/trunk/syn/spi_master_atlys/spi_master_atlys_top.vhd)`
19
20
21
22			`1`
23			`Design Utilities`
24
25
26
27
28			`0`
29			`0`
30			`000000ff0000000000000001000000010000000000000000000000000000000000000000000000018f000000010000000100000000000000000000000064ffffffff0000008100000000000000010000018f0000000100000000`
31			`false`
32
33
34
35
36			`1`
37
38
39			`Z:\Dropbox\develop\fpga\spi_master_slave\trunk\syn\spi_master_atlys\gray_counter.vhd`
40
41			`0`
42			`0`
43			`000000ff000000000000000100000000000000000100000000000000000000000000000000000003c5000000040101000100000000000000000000000064ffffffff0000008100000000000000040000021b00000001000000000000009d0000000100000000000000660000000100000000000000a70000000100000000`
44			`false`
45			`Z:\Dropbox\develop\fpga\spi_master_slave\trunk\syn\spi_master_atlys\gray_counter.vhd`
46
47
48
49			`1`
50
51
52			`Z:\Dropbox\develop\fpga\spi_master_slave\trunk\syn\spi_master_atlys\spi_master.vhd`
53
54			`0`
55			`0`
56			`000000ff000000000000000100000000000000000100000000000000000000000000000000000003c5000000010001000100000000000000000000000064ffffffff000000810000000000000001000003c50000000100000000`
57			`false`
58			`Z:\Dropbox\develop\fpga\spi_master_slave\trunk\syn\spi_master_atlys\spi_master.vhd`
59
60
61
62			`1`
63			`User Constraints`
64
65
66
67
68			`0`
69			`0`
70			`000000ff0000000000000001000000010000000000000000000000000000000000000000000000018f000000010000000100000000000000000000000064ffffffff0000008100000000000000010000018f0000000100000000`
71			`false`
72
73
74
75
76			`1`
77			`Implement Design/Map/Generate Post-Map Static Timing`
78			`Implement Design/Place & Route/Back-annotate Pin Locations`
79			`Implement Design/Place & Route/Generate IBIS Model`
80
81
82			`I/O Pin Planning (PlanAhead) - Post-Synthesis`
83
84			`0`
85			`0`
86			`000000ff000000000000000100000001000000000000000000000000000000000000000000000003b4000000010000000100000000000000000000000064ffffffff000000810000000000000001000003b40000000100000000`
87			`false`
88			`I/O Pin Planning (PlanAhead) - Post-Synthesis`
89
90			`000000ff00000000000000020000011b0000011b01000000050100000002`
91			`Behavioral Simulation`
92
93
94			`2`
95
96
97			`testbench - behavior (Z:/Dropbox/develop/fpga/spi_master_slave/trunk/syn/spi_master_atlys/spi_master_atlys_test.vhd)`
98
99			`0`
100			`0`
101			`000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000372000000020000000000000000000000000200000064ffffffff000000810000000300000002000003720000000100000003000000000000000100000003`
102			`false`
103			`testbench - behavior (Z:/Dropbox/develop/fpga/spi_master_slave/trunk/syn/spi_master_atlys/spi_master_atlys_test.vhd)`
104
105
106
107			`1`
108
109
110
111
112			`0`
113			`0`
114			`000000ff000000000000000100000001000000000000000000000000000000000000000000000003c5000000010000000100000000000000000000000064ffffffff000000810000000000000001000003c50000000100000000`
115			`false`
116
117
118
119
120			`1`
121
122
123
124
125			`0`
126			`0`
127			`000000ff000000000000000100000001000000000000000000000000000000000000000000000003c5000000010000000100000000000000000000000064ffffffff000000810000000000000001000003c50000000100000000`
128			`false`
129
130
131

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Subversion Repositories sha256_hash_core

[/] [sha256_hash_core/] [trunk/] [syn/] [sha256/] [iseconfig/] [spi_master_atlys.projectmgr] - Blame information for rev 2