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-- Author: Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com
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--
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-- Create Date: 09:56:30 07/06/2011
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-- Module Name: sha256_msg_sch - RTL
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-- Project Name: sha256 processor
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-- Target Devices: Spartan-6
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-- Tool versions: ISE 14.7
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-- Description:
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--
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-- This is the message scheduler datapath for the sha256 processor.
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--
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------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
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--
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--
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-- Author(s): Jonny Doin, jonnydoin@gridvortex.com, jonnydoin@gmail.com
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--
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-- Copyright (C) 2016 GridVortex, All Rights Reserved
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-- --------------------------------------------------
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--
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------------------------------ REVISION HISTORY -----------------------------------------------------------------------
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--
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-- 2016/05/22 v0.01.0010 [JD] started development. design of blocks and port interfaces.
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-- 2016/06/05 v0.01.0090 [JD] all modules integrated. testbench for basic test vectors verification.
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-- 2016/06/05 v0.01.0095 [JD] verification failed. misalignment of words in the datapath.
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-- 2016/06/06 v0.01.0100 [JD] first simulation verification against NIST-FIPS-180-4 test vectors passed.
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--
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-----------------------------------------------------------------------------------------------------------------------
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-- TODO
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-- ====
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--
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-----------------------------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity sha256_msg_sch is
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port (
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clk_i : in std_logic := 'U'; -- system clock
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ce_i : in std_logic := 'U'; -- clock enable from control logic
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ld_i : in std_logic := 'U'; -- internal mux selection from control logic
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M_i : in std_logic_vector (31 downto 0) := (others => 'U'); -- big endian input message words
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Wt_o : out std_logic_vector (31 downto 0) -- message schedule output words
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);
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end sha256_msg_sch;
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architecture rtl of sha256_msg_sch is
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-- datapath pipeline
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signal r0 : unsigned (31 downto 0) := (others => '0'); -- internal message register
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signal r1 : unsigned (31 downto 0) := (others => '0'); -- internal message register
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signal r2 : unsigned (31 downto 0) := (others => '0'); -- internal message register
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signal r3 : unsigned (31 downto 0) := (others => '0'); -- internal message register
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signal r4 : unsigned (31 downto 0) := (others => '0'); -- internal message register
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signal r5 : unsigned (31 downto 0) := (others => '0'); -- internal message register
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signal r6 : unsigned (31 downto 0) := (others => '0'); -- internal message register
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signal r7 : unsigned (31 downto 0) := (others => '0'); -- internal message register
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signal r8 : unsigned (31 downto 0) := (others => '0'); -- internal message register
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signal r9 : unsigned (31 downto 0) := (others => '0'); -- internal message register
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signal r10 : unsigned (31 downto 0) := (others => '0'); -- internal message register
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signal r11 : unsigned (31 downto 0) := (others => '0'); -- internal message register
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signal r12 : unsigned (31 downto 0) := (others => '0'); -- internal message register
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signal r13 : unsigned (31 downto 0) := (others => '0'); -- internal message register
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signal r14 : unsigned (31 downto 0) := (others => '0'); -- internal message register
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signal r15 : unsigned (31 downto 0) := (others => '0'); -- internal message register
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-- input mux feedback
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signal next_M : unsigned (31 downto 0); -- sum feedback
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-- word shifter wires
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signal next_r0 : unsigned (31 downto 0);
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signal next_r1 : unsigned (31 downto 0);
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signal next_r2 : unsigned (31 downto 0);
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signal next_r3 : unsigned (31 downto 0);
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signal next_r4 : unsigned (31 downto 0);
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signal next_r5 : unsigned (31 downto 0);
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signal next_r6 : unsigned (31 downto 0);
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signal next_r7 : unsigned (31 downto 0);
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signal next_r8 : unsigned (31 downto 0);
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signal next_r9 : unsigned (31 downto 0);
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signal next_r10 : unsigned (31 downto 0);
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signal next_r11 : unsigned (31 downto 0);
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signal next_r12 : unsigned (31 downto 0);
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signal next_r13 : unsigned (31 downto 0);
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signal next_r14 : unsigned (31 downto 0);
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signal next_r15 : unsigned (31 downto 0);
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-- internal modulo adders
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signal sum0 : unsigned (31 downto 0); -- modulo adder r1 + sum1
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signal sum1 : unsigned (31 downto 0); -- modulo adder s0 + sum2
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signal sum2 : unsigned (31 downto 0); -- modulo adder s1 + r10
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-- lower sigma functions
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signal s0 : unsigned (31 downto 0); -- lower sigma0 function
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signal s1 : unsigned (31 downto 0); -- lower sigma1 function
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begin
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--=============================================================================================
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-- MESSAGE SCHEDULER LOGIC
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--=============================================================================================
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-- This logic implements the 256 bytes message schedule as a folded 16 word circular word shifter.
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-- The Add-Rotate-Xor functions s0 and s1 are implemented and fed back to the word shifter.
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-- To avoid a datapath pipeline delay insertion, the output is taken from the r0 input, rather than
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-- the registered r0 output. This lookahead reduces one clock cycle in the overall hash computation,
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-- but increases the combinational path from the input to the processor core.
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-- The next_r0 combinational function has 5 layers of logic, including 3 carry chains.
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-- word shifter register transfer logic
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word_shifter_proc: process (clk_i, ce_i) is
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begin
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if clk_i'event and clk_i = '1' then
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if ce_i = '1' then
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r0 <= next_r0;
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r1 <= next_r1;
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r2 <= next_r2;
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r3 <= next_r3;
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r4 <= next_r4;
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r5 <= next_r5;
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r6 <= next_r6;
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r7 <= next_r7;
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r8 <= next_r8;
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r9 <= next_r9;
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r10 <= next_r10;
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r11 <= next_r11;
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r12 <= next_r12;
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r13 <= next_r13;
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r14 <= next_r14;
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r15 <= next_r15;
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end if;
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end if;
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end process word_shifter_proc;
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-- input mux
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next_r0_proc: next_r0 <= unsigned(M_i) when ld_i = '1' else next_M;
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next_m_proc: next_M <= sum0;
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-- word shifter wires
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next_r15_proc: next_r15 <= r0;
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next_r14_proc: next_r14 <= r15;
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next_r13_proc: next_r13 <= r14;
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next_r12_proc: next_r12 <= r13;
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next_r11_proc: next_r11 <= r12;
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next_r10_proc: next_r10 <= r11;
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next_r9_proc: next_r9 <= r10;
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next_r8_proc: next_r8 <= r9;
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next_r7_proc: next_r7 <= r8;
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next_r6_proc: next_r6 <= r7;
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next_r5_proc: next_r5 <= r6;
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next_r4_proc: next_r4 <= r5;
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next_r3_proc: next_r3 <= r4;
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next_r2_proc: next_r2 <= r3;
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next_r1_proc: next_r1 <= r2;
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-- adders
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sum0_proc: sum0 <= sum1 + r1;
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sum1_proc: sum1 <= sum2 + s0;
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sum2_proc: sum2 <= r10 + s1;
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-- lower sigma functions
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s0_proc: s0 <= (B"000" & r2(31 downto 3)) xor (r2(17 downto 0) & r2(31 downto 18)) xor (r2(6 downto 0) & r2(31 downto 7));
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s1_proc: s1 <= (B"0000000000" & r15(31 downto 10)) xor (r15(18 downto 0) & r15(31 downto 19)) xor (r15(16 downto 0) & r15(31 downto 17));
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--=============================================================================================
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-- OUTPUT LOGIC
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--=============================================================================================
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-- connect output ports
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Wt_o_proc: Wt_o <= std_logic_vector(next_r0); -- message scheduler output look ahead
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end rtl;
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