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-- Author: Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com
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--
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-- Create Date: 09:56:30 07/06/2011
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-- Module Name: sha256_regs - RTL
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-- Project Name: sha256 processor
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-- Target Devices: Spartan-6
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-- Tool versions: ISE 14.7
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-- Description:
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--
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-- The regs block has the output result registers for the SHA256 processor.
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-- It is a single-cycle 256bit Accumulator for the block hash results, and can be implemented
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-- as a 32bit MUX and a 32bit carry chain for each register.
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--
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------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
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--
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--
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-- Author(s): Jonny Doin, jonnydoin@gridvortex.com, jonnydoin@gmail.com
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--
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-- Copyright (C) 2016 GridVortex, All Rights Reserved
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-- --------------------------------------------------
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--
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------------------------------ REVISION HISTORY -----------------------------------------------------------------------
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--
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-- 2016/05/22 v0.01.0010 [JD] started development. design of blocks and port interfaces.
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-- 2016/06/05 v0.01.0090 [JD] all modules integrated. testbench for basic test vectors verification.
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-- 2016/06/05 v0.01.0095 [JD] verification failed. misalignment of words in the datapath.
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-- 2016/06/06 v0.01.0100 [JD] first simulation verification against NIST-FIPS-180-4 test vectors passed.
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--
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-----------------------------------------------------------------------------------------------------------------------
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-- TODO
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-- ====
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--
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-----------------------------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity sha256_regs is
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port (
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clk_i : in std_logic := 'X'; -- system clock
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ce_i : in std_logic := 'X'; -- clock enable from control logic
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ld_i : in std_logic := 'X'; -- internal mux selection from control logic
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A_i : in std_logic_vector (31 downto 0) := (others => 'X');
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B_i : in std_logic_vector (31 downto 0) := (others => 'X');
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C_i : in std_logic_vector (31 downto 0) := (others => 'X');
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D_i : in std_logic_vector (31 downto 0) := (others => 'X');
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E_i : in std_logic_vector (31 downto 0) := (others => 'X');
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F_i : in std_logic_vector (31 downto 0) := (others => 'X');
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G_i : in std_logic_vector (31 downto 0) := (others => 'X');
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H_i : in std_logic_vector (31 downto 0) := (others => 'X');
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K0_i : in std_logic_vector (31 downto 0) := (others => 'X');
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K1_i : in std_logic_vector (31 downto 0) := (others => 'X');
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K2_i : in std_logic_vector (31 downto 0) := (others => 'X');
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K3_i : in std_logic_vector (31 downto 0) := (others => 'X');
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K4_i : in std_logic_vector (31 downto 0) := (others => 'X');
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K5_i : in std_logic_vector (31 downto 0) := (others => 'X');
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K6_i : in std_logic_vector (31 downto 0) := (others => 'X');
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K7_i : in std_logic_vector (31 downto 0) := (others => 'X');
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N0_o : out std_logic_vector (31 downto 0) := (others => 'X');
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N1_o : out std_logic_vector (31 downto 0) := (others => 'X');
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N2_o : out std_logic_vector (31 downto 0) := (others => 'X');
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N3_o : out std_logic_vector (31 downto 0) := (others => 'X');
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N4_o : out std_logic_vector (31 downto 0) := (others => 'X');
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N5_o : out std_logic_vector (31 downto 0) := (others => 'X');
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N6_o : out std_logic_vector (31 downto 0) := (others => 'X');
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N7_o : out std_logic_vector (31 downto 0) := (others => 'X');
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H0_o : out std_logic_vector (31 downto 0) := (others => 'X');
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H1_o : out std_logic_vector (31 downto 0) := (others => 'X');
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H2_o : out std_logic_vector (31 downto 0) := (others => 'X');
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H3_o : out std_logic_vector (31 downto 0) := (others => 'X');
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H4_o : out std_logic_vector (31 downto 0) := (others => 'X');
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H5_o : out std_logic_vector (31 downto 0) := (others => 'X');
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H6_o : out std_logic_vector (31 downto 0) := (others => 'X');
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H7_o : out std_logic_vector (31 downto 0) := (others => 'X')
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);
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end sha256_regs;
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architecture rtl of sha256_regs is
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-- output result registers
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signal reg_H0 : unsigned (31 downto 0) := (others => '0');
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signal reg_H1 : unsigned (31 downto 0) := (others => '0');
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signal reg_H2 : unsigned (31 downto 0) := (others => '0');
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signal reg_H3 : unsigned (31 downto 0) := (others => '0');
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signal reg_H4 : unsigned (31 downto 0) := (others => '0');
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signal reg_H5 : unsigned (31 downto 0) := (others => '0');
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signal reg_H6 : unsigned (31 downto 0) := (others => '0');
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signal reg_H7 : unsigned (31 downto 0) := (others => '0');
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-- word shifter wires
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signal next_reg_H0 : unsigned (31 downto 0) := (others => '0');
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signal next_reg_H1 : unsigned (31 downto 0) := (others => '0');
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signal next_reg_H2 : unsigned (31 downto 0) := (others => '0');
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signal next_reg_H3 : unsigned (31 downto 0) := (others => '0');
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signal next_reg_H4 : unsigned (31 downto 0) := (others => '0');
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signal next_reg_H5 : unsigned (31 downto 0) := (others => '0');
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signal next_reg_H6 : unsigned (31 downto 0) := (others => '0');
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signal next_reg_H7 : unsigned (31 downto 0) := (others => '0');
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-- internal modulo adders
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signal sum0 : unsigned (31 downto 0) := (others => '0');
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signal sum1 : unsigned (31 downto 0) := (others => '0');
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signal sum2 : unsigned (31 downto 0) := (others => '0');
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signal sum3 : unsigned (31 downto 0) := (others => '0');
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signal sum4 : unsigned (31 downto 0) := (others => '0');
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signal sum5 : unsigned (31 downto 0) := (others => '0');
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signal sum6 : unsigned (31 downto 0) := (others => '0');
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signal sum7 : unsigned (31 downto 0) := (others => '0');
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begin
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--=============================================================================================
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-- OUTPUT RESULT REGISTERS LOGIC
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--=============================================================================================
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-- The output result registers hold the intermediate values for the hash update blocks, and also the final 256bit hash value.
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--
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-- output register transfer logic
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out_regs_proc: process (clk_i, ce_i) is
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begin
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if clk_i'event and clk_i = '1' then
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if ce_i = '1' then
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reg_H0 <= next_reg_H0;
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reg_H1 <= next_reg_H1;
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reg_H2 <= next_reg_H2;
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reg_H3 <= next_reg_H3;
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reg_H4 <= next_reg_H4;
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reg_H5 <= next_reg_H5;
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reg_H6 <= next_reg_H6;
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reg_H7 <= next_reg_H7;
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end if;
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end if;
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end process out_regs_proc;
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-- input muxes
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next_reg_H0_proc: next_reg_H0 <= unsigned(K0_i) when ld_i = '1' else sum0;
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next_reg_H1_proc: next_reg_H1 <= unsigned(K1_i) when ld_i = '1' else sum1;
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next_reg_H2_proc: next_reg_H2 <= unsigned(K2_i) when ld_i = '1' else sum2;
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next_reg_H3_proc: next_reg_H3 <= unsigned(K3_i) when ld_i = '1' else sum3;
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next_reg_H4_proc: next_reg_H4 <= unsigned(K4_i) when ld_i = '1' else sum4;
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next_reg_H5_proc: next_reg_H5 <= unsigned(K5_i) when ld_i = '1' else sum5;
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next_reg_H6_proc: next_reg_H6 <= unsigned(K6_i) when ld_i = '1' else sum6;
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next_reg_H7_proc: next_reg_H7 <= unsigned(K7_i) when ld_i = '1' else sum7;
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-- adders
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sum0_proc: sum0 <= reg_H0 + unsigned(A_i);
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sum1_proc: sum1 <= reg_H1 + unsigned(B_i);
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sum2_proc: sum2 <= reg_H2 + unsigned(C_i);
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sum3_proc: sum3 <= reg_H3 + unsigned(D_i);
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sum4_proc: sum4 <= reg_H4 + unsigned(E_i);
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sum5_proc: sum5 <= reg_H5 + unsigned(F_i);
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sum6_proc: sum6 <= reg_H6 + unsigned(G_i);
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sum7_proc: sum7 <= reg_H7 + unsigned(H_i);
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--=============================================================================================
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-- OUTPUT LOGIC
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--=============================================================================================
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-- connect output ports
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H0_o_proc: H0_o <= std_logic_vector(reg_H0);
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H1_o_proc: H1_o <= std_logic_vector(reg_H1);
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H2_o_proc: H2_o <= std_logic_vector(reg_H2);
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H3_o_proc: H3_o <= std_logic_vector(reg_H3);
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H4_o_proc: H4_o <= std_logic_vector(reg_H4);
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H5_o_proc: H5_o <= std_logic_vector(reg_H5);
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H6_o_proc: H6_o <= std_logic_vector(reg_H6);
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H7_o_proc: H7_o <= std_logic_vector(reg_H7);
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N0_o_proc: N0_o <= std_logic_vector(next_reg_H0);
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N1_o_proc: N1_o <= std_logic_vector(next_reg_H1);
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N2_o_proc: N2_o <= std_logic_vector(next_reg_H2);
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N3_o_proc: N3_o <= std_logic_vector(next_reg_H3);
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N4_o_proc: N4_o <= std_logic_vector(next_reg_H4);
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N5_o_proc: N5_o <= std_logic_vector(next_reg_H5);
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N6_o_proc: N6_o <= std_logic_vector(next_reg_H6);
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N7_o_proc: N7_o <= std_logic_vector(next_reg_H7);
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end rtl;
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