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-- Author: Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com, jonnydoin@gridvortex.com
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--
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-- Create Date: 09:56:30 05/22/2016
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-- Module Name: sha256_test.vhd
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-- Project Name: sha256 engine
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-- Target Devices: Spartan-6
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-- Tool versions: ISE 14.7
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-- Description:
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--
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-- Testbench for the GV_SHA256 engine.
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-- This is the testbench for the GV_SHA256 engine. It exercises all the input control signals and error generation,
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-- and tests the GV_SHA256 engine with the NIST SHA256 test vectors, including the additional NIST test vectors up to the
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-- 1 million chars.
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--
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-- The logic implements a fast engine, with 66 cycles per 512-bit block.
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--
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-- The following waveforms describe the operation of the engine control signals for message start, update and end.
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--
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-- BEGIN BLOCK (1st block)
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-- ======================
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--
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-- The hash operation starts with a 'begin' sync pulse, which causes the RESET of the processor. The processor comes out of RESET only after 'begin' is
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-- released.
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-- The DATA_INPUT state is signalled by the data request signal 'di_req' going HIGH. The processor will latch 16 words from the 'di' port, at every
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-- rising edge of the system clock. At the end of the block input, the 'di_req' signal goes LOW.
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-- The input data can be held by bringing the 'ack' input LOW. When the 'ack' input is held LOW, it includes a wait state in the whole processor, to
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-- cope with slow inputs or to allow periodic fetches of input data from multiple data sources.
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--
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-- state |reset| data |wait | | process
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-- __ |__ |__ __ __ __ __ __ __ |__ |__ __ __ __ __ __ __ __ __ |__ __ __
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-- clk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \... -- system clock
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-- _____
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-- start_i ______/ \_\_______________________________________________________________________________________________________________________... -- 'start_i' resets the processor and starts a new hash
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--
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-- end_i ____________________________________________________________________________________________________________________________________... -- 'end_i' marks end of last block data input
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-- __ _ _ _ _____________________________________________________________________________________________________
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-- di_req_o __ _ _ _\_____/ \_______________... -- 'di_req_o' asserted during data input
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-- ___________________________________________ _________________________________________________________
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-- wr_i __________/____/ \_____/ \_____________... -- 'wr_i' can hold the core for slow data
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-- __________ _________ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ ______ ______________...
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-- di_i __________\___\_W0__\__W1_\__W2_\__W3_\__W4_\__W5_\\\\\\\__W6_\__W7_\__W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15__\______X_______... -- user words on 'di_i' are latched on 'clk_i' rising edge
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-- ____________________ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ _____________________...
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-- st_cnt_reg ________/__0__/__0__/__1__/__2__/__3__/__4__/__5__/___6_______/__7__/__8__/__9__/__10_/__11_/__12_/__13_/__14_/__15_/__16_/__17_/_18... -- internal state counter value
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-- __________ ___ _____ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ _____________________...
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-- Wt_i@core __________\___\__W0_\__W1_\__W2_\__W3_\__W4_\__W5_\\\\\\\__W6_\__W7_\__W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15_________________... -- msg scheduler lookahead output for Wt_i at core
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-- ______________ _____ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ _____________________...
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-- Kt_i@core ______________/__K0_/__K1_/__K2_/__K3_/__K4_/__K5_/__K6_______/__K7_/__K8_/__K9_/_K10_/_K11_/_K12_/_K13_/_K14_/_K15_________________... -- Kt rom synchronous with scheduler for Kt_i at core
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-- __ _ _ _
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-- error_o __ _ _ _\___________________________________________________________________________________________________________________________... -- 'start_i' clears any error condition
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-- __ _ _ _
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-- do_valid_o __ _ _ _\___________________________________________________________________________________________________________________________... -- 'start_i' invalidates any previous results
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--
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--
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-- UPDATE BLOCK (preload)
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-- =====================
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--
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-- At the start of each block, the 'di_req' signal is raised to request new data.
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--
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-- state ... process |next | data |wait | | process
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-- __ __ __ __ __ __ __ __ __ __ |__ |__ __ __ __ __ __ __ __ __ __
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-- clk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \... -- system clock
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--
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-- end_i ______________________________________________________________________________________________________________________________... -- 'end_i' marks end of last block data input
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-- _____________________________________________________________________________________________________
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-- di_req_o ____________________/ \___... -- 'di_req_o' asserted during data input
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-- ___________________________________________________ _________________________________________________________
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-- wr_i ________/__________/ \_____/ \_... -- 'wr_i' can hold the core for slow data
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-- _________________ _ ______ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ _____ ____...
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-- di_i _________________\\\___W0_\__W1_\__W2_\__W3_\__W4_\__W5_\\\\\\\\_W6_\__W7_\__W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15_\\_X_... -- user words on 'di_i' are latched on 'clk_i' rising edge
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--
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--
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-- UPDATE BLOCK (delayed start)
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-- ===========================
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--
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-- The data for the new block can be delayed, by keeping the 'ack' signal low until the data is present at the data input port.
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--
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-- state ..|next | data |wait | | process
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-- __ __ __ __ __ __ __ __ __ __ __ __ __ |__ |__ __ __ __ __ __ __ __
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-- clk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \... -- system clock
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--
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-- end_i ____________________________________________________________________________________________________________________________________... -- 'end_i' marks end of last block data input
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-- _______ _ _ ___________________________________________________________________________________________________________
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-- di_req_o ________/ \___... -- 'di_req_o' asserted during data input
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-- __________________________________________________ _____________________________________________
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-- wr_i ________________ _ _ ______/ \_____/ \_... -- 'wr_i' valid on rising edge of 'clk_i'
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-- ________________ _ _ ___________ _____ _____ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ ____...
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-- di_i ________________ _ _ ______\_W0_\__W1_\__W2_\__W3_\__W4_\__W5_\__W6_\__W7_\\\\_____W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15_\__Z_... -- user words on 'di_i' are latched on 'clk_i' rising edge
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--
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--
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-- END BLOCK (success)
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-- ==================
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--
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-- At the end of the last block the signal 'end' must be raised for at least one clock cycle.
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-- The 'bytes' input marks the number of valid bytes in the last word.
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-- A PADDING state completes the last data block and a BLK_PROCESS finishes the hash computation.
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-- The 'do_valid' remains HIGH until the next RESET.
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--
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-- state ..|next | data | padding | process |next | valid |reset| data
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-- __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __
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-- clk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \_ _ _ __/ \__/ \__/ \_ _ _ __/ \__/ \__/ \__/ \__/ \__/ \__/ \_... -- system clock
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-- ______
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-- start_i ____________________________________________________________________________________________________________/ \__\___________... -- 'start_i' resets the processor and starts a new hash
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-- ______
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-- end_i _________________________________________/ \______ _ _ ___________________ _ _ ___________________________________________... -- 'end_i' marks end of last block data input
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-- ___________________________________ __________
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-- di_req_o ________/ \__________ _ _ ___________________ _ _ ________________________________/ ... -- 'di_req_o' asserted during data input
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-- ______________________________________ _________
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-- wr_i _________/ \\\______ _ _ ___________________ _ _ _________________________________/ ... -- 'wr_i' can hold the core for slow data
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-- ______________ _____ _____ _____ _____ _____ __________ _ _ ___________________ _ _ ______________________________________ ____...
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-- di_i _________\_W0_\__W1_\__W2_\__W3_\__W4_\__W5_\__________ _ _ ___________________ _ _ _________________________________\_W0_\__W1... -- words after the end_i assertion are ignored
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-- __ _____ _____ _____ _____ _____ _____ _____ _____ ____ _ ____ _____ _____ ____ _ _ ______________________________________ ____
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-- st_cnt_reg __/_64__/__0__/__1__/__2__/__3__/__4__/__5__/__6__/__7_ _ _15_/__16_/__17_/__18 _ _ __/__63_/__64_/______0__________/__0__/__1_... -- internal state counter value
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-- _____ _____ _____ _____ _____ _____ _____ ____
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-- bytes_i --------<__0__\__0__\__0__\__0__\__0__\__3__>-----------------------------------------------------------------------<__0__\__0_... -- bytes_i mark number of valid bytes in each word
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--
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-- error_o _______________________________________________________ _ _ ___________________ _ _ ___________________________________________... -- 'error_o' goes high on an invalid computation
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-- ___________
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-- do_valid_o _______________________________________________________ _ _ ___________________ _ _ ______________/ \________________... -- 'do_valid_o' goes high at the end of a computation
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-- ___________
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-- H0_o _______________________________________________________ _ _ ___________________ _ _ ______________/___H0______\________________... -- H0 holds the bytes 0..3 of the output
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-- ___________
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-- H1_o _______________________________________________________ _ _ ___________________ _ _ ______________/___H1______\________________... -- H1 holds the bytes 4..7 of the output
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-- ___________
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-- H2_o _______________________________________________________ _ _ ___________________ _ _ ______________/___H2______\________________... -- H2 holds the bytes 8..11 of the output
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-- ___________
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-- H3_o _______________________________________________________ _ _ ___________________ _ _ ______________/___H3______\________________... -- H3 holds the bytes 12..15 of the output
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-- ___________
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-- H4_o _______________________________________________________ _ _ ___________________ _ _ ______________/___H4______\________________... -- H4 holds the bytes 16..19 of the output
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-- ___________
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-- H5_o _______________________________________________________ _ _ ___________________ _ _ ______________/___H5______\________________... -- H5 holds the bytes 20..23 of the output
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-- ___________
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-- H6_o _______________________________________________________ _ _ ___________________ _ _ ______________/___H6______\________________... -- H6 holds the bytes 24..27 of the output
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-- ___________
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-- H7_o _______________________________________________________ _ _ ___________________ _ _ ______________/___H7______\________________... -- H7 holds the bytes 28..31 of the output
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--
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--
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-- END BLOCK (full last block)
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-- ==================
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--
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-- If the last block has exactly 16 full words, the controller inserts a dummy PADDING cycle, processes the input block, and inserts a
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-- last PADDING block followed by a last BLK_PROCESS block.
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--
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-- state ... data |pad | process |next | pad | process |next | valid |reset| data
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-- __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __
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-- clk_i \__/ \__/ \__/ \__/ \_ _ _ __/ \__/ \__/ \_ _ _ __/ \__/ \_ _ _ __/ \__/ \__/ \__/ \__/ \__/ \_... -- system clock
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-- ______
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-- start_i _____________________________________________________________________________________________/ \__\___________... -- 'start_i' resets the processor and starts a new hash
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-- ______
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-- end_i ______________/ \______ _ _ ___________________ _ _ _____________ _ _ _____________________________________... -- 'end_i' marks end of last block data input
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-- _________________ __________
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-- di_req_o \__________ _ _ ___________________ _ _ _____________ _ _ __________________________/ ... -- 'di_req_o' asserted on rising edge of 'clk_i'
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-- ____________________ _________
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-- wr_i \\\_______ _ _ ___________________ _ _ _____________ _ _ ___________________________/ ... -- 'wr_i' valid on rising edge of 'clk_i'
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-- _____ _____ _____ __________ _ _ ___________________ _ _ _____________ _ _ ________________________________ ____...
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-- di_i _W13_\_W14_\_W15_\__________ _ _ ___________________ _ _ _____________ _ _ ___________________________\_W0_\__W1... -- words after the end_i assertion are ignored
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-- _____ _____ _____ _____ ____ _ ____ _____ _____ ____ _ _ ________ ____ _ ____ _____ _______________________ ____
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-- st_cnt_reg _13__/_14__/_15__/_16__/_16_ _ _63_/__64_/__0__/__1_ _ _ __/_15__/_16_ _ _63_/__64_/_____0_____/__0__/__0__/__1_... -- internal state counter value
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-- _____ _____ _____ _____ ____
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-- bytes_i __0__/__0__/__0__>-----------------------------------------------------------------------------------<__0__/__0_... -- bytes_i mark number of valid bytes in each word
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-- ___________
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-- do_valid_o ____________________________ _ _ ___________________ _ _ __________________________/ \________________... -- 'do_valid_o' goes high at the end of a computation
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--
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------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
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--
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-- This file is part of the SHA256 HASH CORE project http://opencores.org/project,sha256_hash_core
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--
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-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gridvortex.com, jonnydoin@gmail.com
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--
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-- Copyright (C) 2016 Jonny Doin
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-- -----------------------------
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--
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-- This source file may be used and distributed without restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains the original copyright notice and the associated
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-- disclaimer.
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--
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-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser
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-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or
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-- (at your option) any later version.
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--
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-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download
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-- it from http://www.gnu.org/licenses/lgpl.txt
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--
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------------------------------ REVISION HISTORY -----------------------------------------------------------------------
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--
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-- 2016/05/22 v0.01.0010 [JD] started development. design of blocks and port interfaces.
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-- 2016/06/05 v0.01.0090 [JD] all modules integrated. testbench for basic test vectors verification.
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-- 2016/06/05 v0.01.0095 [JD] verification failed. misalignment of words in the datapath.
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-- 2016/06/06 v0.01.0100 [JD] first simulation verification against NIST-FIPS-180-4 test vectors "abc" passed.
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-- 2016/06/07 v0.01.0101 [JD] failed 2-block test for "abcdbcdecd..." vector. Fixed padding control logic.
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-- 2016/06/07 v0.01.0105 [JD] sha256 verification against all NIST-FIPS-180-4 test vectors passed.
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-- 2016/06/11 v0.01.0105 [JD] verification against NIST-SHA2_Additional test vectors #1 to #10 passed.
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-- 2016/06/11 v0.01.0110 [JD] optimized controller states, reduced 2 clocks per block.
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-- 2016/06/18 v0.01.0120 [JD] implemented error detection on 'bytes_i' input.
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-- 2016/09/25 v0.01.0220 [JD] changed 'di_ack_i' name to 'di_wr_i', and changed semantics to 'data write'.
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--
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-----------------------------------------------------------------------------------------------------------------------
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-- TODO
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-- ====
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--
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--
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-----------------------------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity testbench is
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Generic (
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CLK_PERIOD : time := 10 ns; -- clock period for pclk_i (default 100MHz)
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START_DELAY : time := 200 ns -- start delay between each run
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);
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end testbench;
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architecture behavior of testbench is
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--=============================================================================================
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-- Constants
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--=============================================================================================
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-- clock period
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constant PCLK_PERIOD : time := CLK_PERIOD; -- parallel high-speed clock
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--=============================================================================================
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-- Signals for state machine control
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--=============================================================================================
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--=============================================================================================
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-- Signals for internal operation
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--=============================================================================================
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--- clock signals ---
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signal pclk : std_logic := '1'; -- 100MHz clock
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signal dut_ce : std_logic;
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-- input data
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signal dut_di : std_logic_vector (31 downto 0); -- big endian input message words
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signal dut_bytes : std_logic_vector (1 downto 0); -- valid bytes in input word
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-- start/end commands
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signal dut_start : std_logic; -- reset the processor and start a new hash
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signal dut_end : std_logic; -- marks end of last block data input
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-- handshake
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signal dut_di_req : std_logic; -- requests data input for next word
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signal dut_di_wr : std_logic; -- high for di_i write, low for hold
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jdoin |
signal dut_error : std_logic; -- signalizes error. output data is invalid
|
246 |
|
|
signal dut_do_valid : std_logic; -- when high, the output is valid
|
247 |
|
|
-- 256bit output registers
|
248 |
|
|
signal dut_H0 : std_logic_vector (31 downto 0);
|
249 |
|
|
signal dut_H1 : std_logic_vector (31 downto 0);
|
250 |
|
|
signal dut_H2 : std_logic_vector (31 downto 0);
|
251 |
|
|
signal dut_H3 : std_logic_vector (31 downto 0);
|
252 |
|
|
signal dut_H4 : std_logic_vector (31 downto 0);
|
253 |
|
|
signal dut_H5 : std_logic_vector (31 downto 0);
|
254 |
|
|
signal dut_H6 : std_logic_vector (31 downto 0);
|
255 |
|
|
signal dut_H7 : std_logic_vector (31 downto 0);
|
256 |
|
|
|
257 |
|
|
-- testbench control signals
|
258 |
|
|
signal words : natural;
|
259 |
|
|
signal blocks : natural;
|
260 |
|
|
signal test_case : natural;
|
261 |
|
|
begin
|
262 |
|
|
|
263 |
|
|
--=============================================================================================
|
264 |
|
|
-- INSTANTIATION FOR THE DEVICE UNDER TEST
|
265 |
|
|
--=============================================================================================
|
266 |
|
|
Inst_sha_256_dut: entity work.gv_sha256(rtl)
|
267 |
|
|
port map(
|
268 |
|
|
-- clock and core enable
|
269 |
|
|
clk_i => pclk,
|
270 |
|
|
ce_i => dut_ce,
|
271 |
|
|
-- input data
|
272 |
|
|
di_i => dut_di,
|
273 |
|
|
bytes_i => dut_bytes,
|
274 |
|
|
-- start/end commands
|
275 |
|
|
start_i => dut_start,
|
276 |
|
|
end_i => dut_end,
|
277 |
|
|
-- handshake
|
278 |
|
|
di_req_o => dut_di_req,
|
279 |
9 |
jdoin |
di_wr_i => dut_di_wr,
|
280 |
2 |
jdoin |
error_o => dut_error,
|
281 |
|
|
do_valid_o => dut_do_valid,
|
282 |
|
|
-- 256bit output registers
|
283 |
|
|
H0_o => dut_H0,
|
284 |
|
|
H1_o => dut_H1,
|
285 |
|
|
H2_o => dut_H2,
|
286 |
|
|
H3_o => dut_H3,
|
287 |
|
|
H4_o => dut_H4,
|
288 |
|
|
H5_o => dut_H5,
|
289 |
|
|
H6_o => dut_H6,
|
290 |
|
|
H7_o => dut_H7
|
291 |
|
|
);
|
292 |
|
|
|
293 |
|
|
--=============================================================================================
|
294 |
|
|
-- CLOCK GENERATION
|
295 |
|
|
--=============================================================================================
|
296 |
|
|
pclk_proc: process is
|
297 |
|
|
begin
|
298 |
|
|
loop
|
299 |
|
|
pclk <= not pclk;
|
300 |
|
|
wait for PCLK_PERIOD / 2;
|
301 |
|
|
end loop;
|
302 |
|
|
end process pclk_proc;
|
303 |
|
|
--=============================================================================================
|
304 |
|
|
-- TEST BENCH STIMULI
|
305 |
|
|
--=============================================================================================
|
306 |
|
|
-- This testbench exercises the SHA256 toplevel with the NIST-FIPS-180-4 test vectors.
|
307 |
|
|
--
|
308 |
|
|
tb1 : process is
|
309 |
|
|
variable count_words : natural := 0;
|
310 |
|
|
variable count_blocks : natural := 0;
|
311 |
|
|
variable temp_di : unsigned (31 downto 0) := (others => '0');
|
312 |
|
|
begin
|
313 |
|
|
wait for START_DELAY; -- wait until global set/reset completes
|
314 |
|
|
-------------------------------------------------------------------------------------------
|
315 |
|
|
-- test vector 1
|
316 |
|
|
-- src: NIST-FIPS-180-4
|
317 |
|
|
-- msg := "abc"
|
318 |
|
|
-- hash:= BA7816BF 8F01CFEA 414140DE 5DAE2223 B00361A3 96177A9C B410FF61 F20015AD
|
319 |
|
|
test_case <= 1;
|
320 |
|
|
dut_ce <= '0';
|
321 |
|
|
dut_di <= (others => '0');
|
322 |
|
|
dut_bytes <= b"00";
|
323 |
|
|
dut_start <= '0';
|
324 |
|
|
dut_end <= '0';
|
325 |
9 |
jdoin |
dut_di_wr <= '0';
|
326 |
2 |
jdoin |
wait until pclk'event and pclk = '1';
|
327 |
|
|
dut_ce <= '1';
|
328 |
|
|
dut_start <= '1';
|
329 |
6 |
jdoin |
dut_di <= x"61626300";
|
330 |
|
|
dut_bytes <= b"11";
|
331 |
2 |
jdoin |
wait until pclk'event and pclk = '1';
|
332 |
|
|
dut_start <= '0';
|
333 |
9 |
jdoin |
dut_di_wr <= '1';
|
334 |
|
|
if dut_di_req = '0' then
|
335 |
|
|
wait until dut_di_req = '1';
|
336 |
|
|
end if;
|
337 |
2 |
jdoin |
dut_end <= '1';
|
338 |
|
|
wait until pclk'event and pclk = '1';
|
339 |
|
|
dut_end <= '0';
|
340 |
9 |
jdoin |
dut_di_wr <= '0';
|
341 |
2 |
jdoin |
if dut_error /= '1' and dut_do_valid /= '1' then
|
342 |
|
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
343 |
|
|
wait until pclk'event and pclk = '1';
|
344 |
|
|
end loop;
|
345 |
|
|
end if;
|
346 |
|
|
wait for CLK_PERIOD*20;
|
347 |
|
|
|
348 |
|
|
-- expected: BA7816BF 8F01CFEA 414140DE 5DAE2223 B00361A3 96177A9C B410FF61 F20015AD
|
349 |
|
|
assert dut_H0 = x"BA7816BF" report "test #1 failed on H0" severity error;
|
350 |
|
|
assert dut_H1 = x"8F01CFEA" report "test #1 failed on H1" severity error;
|
351 |
|
|
assert dut_H2 = x"414140DE" report "test #1 failed on H2" severity error;
|
352 |
|
|
assert dut_H3 = x"5DAE2223" report "test #1 failed on H3" severity error;
|
353 |
|
|
assert dut_H4 = x"B00361A3" report "test #1 failed on H4" severity error;
|
354 |
|
|
assert dut_H5 = x"96177A9C" report "test #1 failed on H5" severity error;
|
355 |
|
|
assert dut_H6 = x"B410FF61" report "test #1 failed on H6" severity error;
|
356 |
|
|
assert dut_H7 = x"F20015AD" report "test #1 failed on H7" severity error;
|
357 |
|
|
|
358 |
|
|
-------------------------------------------------------------------------------------------
|
359 |
|
|
-- test vector 2
|
360 |
|
|
-- src: NIST-FIPS-180-4
|
361 |
|
|
-- msg := "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq"
|
362 |
|
|
-- hash:= 248D6A61 D20638B8 E5C02693 0C3E6039 A33CE459 64FF2167 F6ECEDD4 19DB06C1
|
363 |
|
|
test_case <= 2;
|
364 |
|
|
dut_ce <= '0';
|
365 |
|
|
dut_di <= (others => '0');
|
366 |
|
|
dut_bytes <= b"00";
|
367 |
|
|
dut_start <= '0';
|
368 |
|
|
dut_end <= '0';
|
369 |
9 |
jdoin |
dut_di_wr <= '0';
|
370 |
2 |
jdoin |
wait until pclk'event and pclk = '1';
|
371 |
|
|
dut_ce <= '1';
|
372 |
|
|
dut_start <= '1';
|
373 |
|
|
wait until pclk'event and pclk = '1'; -- 'begin' pulse minimum width is one clock
|
374 |
|
|
wait for 25 ns; -- TEST: stretch 'begin' pulse
|
375 |
|
|
dut_start <= '0';
|
376 |
9 |
jdoin |
if dut_di_req = '0' then
|
377 |
|
|
wait until dut_di_req = '1';
|
378 |
|
|
end if;
|
379 |
2 |
jdoin |
wait until pclk'event and pclk = '1';
|
380 |
9 |
jdoin |
dut_di_wr <= '1';
|
381 |
2 |
jdoin |
dut_bytes <= b"00";
|
382 |
|
|
dut_di <= x"61626364";
|
383 |
|
|
wait until pclk'event and pclk = '1';
|
384 |
|
|
dut_di <= x"62636465";
|
385 |
|
|
wait until pclk'event and pclk = '1';
|
386 |
|
|
dut_di <= x"63646566";
|
387 |
|
|
wait until pclk'event and pclk = '1';
|
388 |
|
|
dut_di <= x"64656667";
|
389 |
|
|
wait until pclk'event and pclk = '1';
|
390 |
|
|
dut_di <= x"65666768";
|
391 |
|
|
wait until pclk'event and pclk = '1';
|
392 |
|
|
dut_di <= x"66676869";
|
393 |
|
|
wait until pclk'event and pclk = '1';
|
394 |
|
|
dut_di <= x"6768696A";
|
395 |
9 |
jdoin |
dut_di_wr <= '0';
|
396 |
2 |
jdoin |
wait until pclk'event and pclk = '1';
|
397 |
|
|
wait until pclk'event and pclk = '1';
|
398 |
|
|
wait until pclk'event and pclk = '1';
|
399 |
9 |
jdoin |
dut_di_wr <= '1'; -- TEST: slow inputs with 'ack' handshake
|
400 |
2 |
jdoin |
wait until pclk'event and pclk = '1';
|
401 |
|
|
dut_di <= x"68696A6B";
|
402 |
|
|
wait until pclk'event and pclk = '1';
|
403 |
|
|
dut_di <= x"696A6B6C";
|
404 |
|
|
wait until pclk'event and pclk = '1';
|
405 |
|
|
dut_di <= x"6A6B6C6D";
|
406 |
|
|
dut_bytes <= b"01"; -- induce ERROR
|
407 |
|
|
wait until pclk'event and pclk = '1';
|
408 |
|
|
dut_di <= x"6B6C6D6E";
|
409 |
|
|
wait until pclk'event and pclk = '1';
|
410 |
|
|
dut_di <= x"6C6D6E6F";
|
411 |
|
|
wait until pclk'event and pclk = '1';
|
412 |
|
|
dut_di <= x"6D6E6F70";
|
413 |
|
|
wait until pclk'event and pclk = '1';
|
414 |
|
|
dut_di <= x"6E6F7071";
|
415 |
|
|
dut_end <= '1';
|
416 |
|
|
wait until pclk'event and pclk = '1'; -- 'end' pulse minimum width is one clock
|
417 |
|
|
dut_bytes <= b"01"; -- TEST: change 'bytes' value after END
|
418 |
|
|
wait for 75 ns; -- TEST: stretch 'end' pulse
|
419 |
|
|
dut_end <= '0';
|
420 |
9 |
jdoin |
dut_di_wr <= '0';
|
421 |
2 |
jdoin |
if dut_error /= '1' and dut_do_valid /= '1' then
|
422 |
|
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
423 |
|
|
wait until pclk'event and pclk = '1';
|
424 |
|
|
end loop;
|
425 |
|
|
end if;
|
426 |
|
|
wait for CLK_PERIOD*20;
|
427 |
|
|
-------------------------------------------------------------------------
|
428 |
|
|
-- restart test #2
|
429 |
|
|
test_case <= 0;
|
430 |
|
|
wait until pclk'event and pclk = '1';
|
431 |
|
|
test_case <= 2;
|
432 |
|
|
dut_ce <= '0';
|
433 |
|
|
dut_di <= (others => '0');
|
434 |
|
|
dut_bytes <= b"00";
|
435 |
|
|
dut_start <= '0';
|
436 |
|
|
dut_end <= '0';
|
437 |
9 |
jdoin |
dut_di_wr <= '0';
|
438 |
2 |
jdoin |
wait until pclk'event and pclk = '1';
|
439 |
|
|
dut_ce <= '1';
|
440 |
|
|
dut_start <= '1';
|
441 |
6 |
jdoin |
dut_di <= x"61626364";
|
442 |
|
|
dut_bytes <= b"00";
|
443 |
2 |
jdoin |
wait until pclk'event and pclk = '1'; -- 'begin' pulse minimum width is one clock
|
444 |
|
|
dut_start <= '0';
|
445 |
9 |
jdoin |
dut_di_wr <= '1';
|
446 |
|
|
if dut_di_req = '0' then
|
447 |
|
|
wait until dut_di_req = '1';
|
448 |
|
|
end if;
|
449 |
2 |
jdoin |
wait until pclk'event and pclk = '1';
|
450 |
|
|
dut_di <= x"62636465";
|
451 |
|
|
wait until pclk'event and pclk = '1';
|
452 |
|
|
dut_di <= x"63646566";
|
453 |
|
|
wait until pclk'event and pclk = '1';
|
454 |
|
|
dut_di <= x"64656667";
|
455 |
|
|
wait until pclk'event and pclk = '1';
|
456 |
|
|
dut_di <= x"65666768";
|
457 |
|
|
wait until pclk'event and pclk = '1';
|
458 |
|
|
dut_di <= x"66676869";
|
459 |
|
|
wait until pclk'event and pclk = '1';
|
460 |
|
|
dut_di <= x"6768696A";
|
461 |
|
|
wait until pclk'event and pclk = '1';
|
462 |
|
|
dut_di <= x"68696A6B";
|
463 |
|
|
wait until pclk'event and pclk = '1';
|
464 |
|
|
dut_di <= x"696A6B6C";
|
465 |
|
|
wait until pclk'event and pclk = '1';
|
466 |
|
|
dut_di <= x"6A6B6C6D";
|
467 |
|
|
wait until pclk'event and pclk = '1';
|
468 |
|
|
dut_di <= x"6B6C6D6E";
|
469 |
|
|
wait until pclk'event and pclk = '1';
|
470 |
|
|
dut_di <= x"6C6D6E6F";
|
471 |
|
|
wait until pclk'event and pclk = '1';
|
472 |
|
|
dut_di <= x"6D6E6F70";
|
473 |
|
|
wait until pclk'event and pclk = '1';
|
474 |
|
|
dut_di <= x"6E6F7071";
|
475 |
|
|
dut_end <= '1';
|
476 |
|
|
wait until pclk'event and pclk = '1'; -- 'end' pulse minimum width is one clock
|
477 |
|
|
dut_end <= '0';
|
478 |
9 |
jdoin |
dut_di_wr <= '0';
|
479 |
2 |
jdoin |
if dut_error /= '1' and dut_do_valid /= '1' then
|
480 |
|
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
481 |
|
|
wait until pclk'event and pclk = '1';
|
482 |
|
|
end loop;
|
483 |
|
|
end if;
|
484 |
|
|
wait for CLK_PERIOD*20;
|
485 |
|
|
|
486 |
|
|
-- expected: 248D6A61 D20638B8 E5C02693 0C3E6039 A33CE459 64FF2167 F6ECEDD4 19DB06C1
|
487 |
|
|
assert dut_H0 = x"248D6A61" report "test #2 failed on H0" severity error;
|
488 |
|
|
assert dut_H1 = x"D20638B8" report "test #2 failed on H1" severity error;
|
489 |
|
|
assert dut_H2 = x"E5C02693" report "test #2 failed on H2" severity error;
|
490 |
|
|
assert dut_H3 = x"0C3E6039" report "test #2 failed on H3" severity error;
|
491 |
|
|
assert dut_H4 = x"A33CE459" report "test #2 failed on H4" severity error;
|
492 |
|
|
assert dut_H5 = x"64FF2167" report "test #2 failed on H5" severity error;
|
493 |
|
|
assert dut_H6 = x"F6ECEDD4" report "test #2 failed on H6" severity error;
|
494 |
|
|
assert dut_H7 = x"19DB06C1" report "test #2 failed on H7" severity error;
|
495 |
|
|
|
496 |
|
|
-------------------------------------------------------------------------------------------
|
497 |
|
|
-- test vector 3
|
498 |
|
|
-- src: NIST-ADDITIONAL-SHA256
|
499 |
|
|
-- #1) 1 byte 0xbd
|
500 |
|
|
-- msg := x"bd"
|
501 |
|
|
-- hash:= 68325720 aabd7c82 f30f554b 313d0570 c95accbb 7dc4b5aa e11204c0 8ffe732b
|
502 |
|
|
test_case <= 3;
|
503 |
|
|
dut_ce <= '0';
|
504 |
|
|
dut_di <= (others => '0');
|
505 |
|
|
dut_bytes <= b"00";
|
506 |
|
|
dut_start <= '0';
|
507 |
|
|
dut_end <= '0';
|
508 |
9 |
jdoin |
dut_di_wr <= '0';
|
509 |
2 |
jdoin |
wait until pclk'event and pclk = '1';
|
510 |
|
|
dut_ce <= '1';
|
511 |
|
|
dut_start <= '1';
|
512 |
6 |
jdoin |
dut_di <= x"bd000000";
|
513 |
|
|
dut_bytes <= b"01";
|
514 |
2 |
jdoin |
wait until pclk'event and pclk = '1';
|
515 |
|
|
dut_start <= '0';
|
516 |
9 |
jdoin |
dut_di_wr <= '1';
|
517 |
|
|
if dut_di_req = '0' then
|
518 |
|
|
wait until dut_di_req = '1';
|
519 |
|
|
end if;
|
520 |
2 |
jdoin |
dut_end <= '1';
|
521 |
|
|
wait until pclk'event and pclk = '1';
|
522 |
|
|
dut_end <= '0';
|
523 |
9 |
jdoin |
dut_di_wr <= '0';
|
524 |
2 |
jdoin |
if dut_error /= '1' and dut_do_valid /= '1' then
|
525 |
|
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
526 |
|
|
wait until pclk'event and pclk = '1';
|
527 |
|
|
end loop;
|
528 |
|
|
end if;
|
529 |
|
|
wait for CLK_PERIOD*20;
|
530 |
|
|
|
531 |
|
|
-- expected: 68325720 aabd7c82 f30f554b 313d0570 c95accbb 7dc4b5aa e11204c0 8ffe732b
|
532 |
|
|
assert dut_H0 = x"68325720" report "test #3 failed on H0" severity error;
|
533 |
|
|
assert dut_H1 = x"aabd7c82" report "test #3 failed on H1" severity error;
|
534 |
|
|
assert dut_H2 = x"f30f554b" report "test #3 failed on H2" severity error;
|
535 |
|
|
assert dut_H3 = x"313d0570" report "test #3 failed on H3" severity error;
|
536 |
|
|
assert dut_H4 = x"c95accbb" report "test #3 failed on H4" severity error;
|
537 |
|
|
assert dut_H5 = x"7dc4b5aa" report "test #3 failed on H5" severity error;
|
538 |
|
|
assert dut_H6 = x"e11204c0" report "test #3 failed on H6" severity error;
|
539 |
|
|
assert dut_H7 = x"8ffe732b" report "test #3 failed on H7" severity error;
|
540 |
|
|
|
541 |
|
|
-------------------------------------------------------------------------------------------
|
542 |
|
|
-- test vector 4
|
543 |
|
|
-- src: NIST-ADDITIONAL-SHA256
|
544 |
|
|
-- #2) 4 bytes 0xc98c8e55
|
545 |
|
|
-- msg := x"c98c8e55"
|
546 |
|
|
-- hash:= 7abc22c0 ae5af26c e93dbb94 433a0e0b 2e119d01 4f8e7f65 bd56c61c cccd9504
|
547 |
|
|
test_case <= 4;
|
548 |
|
|
dut_ce <= '0';
|
549 |
|
|
dut_di <= (others => '0');
|
550 |
|
|
dut_bytes <= b"00";
|
551 |
|
|
dut_start <= '0';
|
552 |
|
|
dut_end <= '0';
|
553 |
9 |
jdoin |
dut_di_wr <= '0';
|
554 |
2 |
jdoin |
wait until pclk'event and pclk = '1';
|
555 |
|
|
dut_ce <= '1';
|
556 |
|
|
dut_start <= '1';
|
557 |
6 |
jdoin |
dut_di <= x"c98c8e55";
|
558 |
|
|
dut_bytes <= b"00";
|
559 |
2 |
jdoin |
wait until pclk'event and pclk = '1';
|
560 |
|
|
dut_start <= '0';
|
561 |
9 |
jdoin |
dut_di_wr <= '1';
|
562 |
|
|
if dut_di_req = '0' then
|
563 |
|
|
wait until dut_di_req = '1';
|
564 |
|
|
end if;
|
565 |
|
|
dut_di_wr <= '1';
|
566 |
2 |
jdoin |
dut_end <= '1';
|
567 |
|
|
wait until pclk'event and pclk = '1';
|
568 |
|
|
dut_end <= '0';
|
569 |
9 |
jdoin |
dut_di_wr <= '0';
|
570 |
2 |
jdoin |
if dut_error /= '1' and dut_do_valid /= '1' then
|
571 |
|
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
572 |
|
|
wait until pclk'event and pclk = '1';
|
573 |
|
|
end loop;
|
574 |
|
|
end if;
|
575 |
|
|
wait for CLK_PERIOD*20;
|
576 |
|
|
|
577 |
|
|
-- expected: 7abc22c0 ae5af26c e93dbb94 433a0e0b 2e119d01 4f8e7f65 bd56c61c cccd9504
|
578 |
|
|
assert dut_H0 = x"7abc22c0" report "test #4 failed on H0" severity error;
|
579 |
|
|
assert dut_H1 = x"ae5af26c" report "test #4 failed on H1" severity error;
|
580 |
|
|
assert dut_H2 = x"e93dbb94" report "test #4 failed on H2" severity error;
|
581 |
|
|
assert dut_H3 = x"433a0e0b" report "test #4 failed on H3" severity error;
|
582 |
|
|
assert dut_H4 = x"2e119d01" report "test #4 failed on H4" severity error;
|
583 |
|
|
assert dut_H5 = x"4f8e7f65" report "test #4 failed on H5" severity error;
|
584 |
|
|
assert dut_H6 = x"bd56c61c" report "test #4 failed on H6" severity error;
|
585 |
|
|
assert dut_H7 = x"cccd9504" report "test #4 failed on H7" severity error;
|
586 |
|
|
|
587 |
|
|
-------------------------------------------------------------------------------------------
|
588 |
|
|
-- test vector 5
|
589 |
|
|
-- src: NIST-ADDITIONAL-SHA256
|
590 |
|
|
-- #3) 55 bytes of zeros
|
591 |
|
|
-- msg := 55 x"00"
|
592 |
|
|
-- hash:= 02779466 cdec1638 11d07881 5c633f21 90141308 1449002f 24aa3e80 f0b88ef7
|
593 |
|
|
test_case <= 5;
|
594 |
|
|
dut_ce <= '0';
|
595 |
|
|
dut_di <= (others => '0');
|
596 |
|
|
dut_bytes <= b"00";
|
597 |
|
|
dut_start <= '0';
|
598 |
|
|
dut_end <= '0';
|
599 |
9 |
jdoin |
dut_di_wr <= '0';
|
600 |
2 |
jdoin |
wait until pclk'event and pclk = '1';
|
601 |
|
|
dut_ce <= '1';
|
602 |
|
|
dut_start <= '1';
|
603 |
6 |
jdoin |
dut_di <= x"00000000";
|
604 |
|
|
dut_bytes <= b"00";
|
605 |
2 |
jdoin |
wait until pclk'event and pclk = '1';
|
606 |
|
|
dut_start <= '0';
|
607 |
9 |
jdoin |
dut_di_wr <= '1';
|
608 |
|
|
if dut_di_req = '0' then
|
609 |
|
|
wait until dut_di_req = '1';
|
610 |
|
|
end if;
|
611 |
2 |
jdoin |
wait until pclk'event and pclk = '1';
|
612 |
|
|
wait until pclk'event and pclk = '1';
|
613 |
|
|
wait until pclk'event and pclk = '1';
|
614 |
|
|
wait until pclk'event and pclk = '1';
|
615 |
|
|
wait until pclk'event and pclk = '1';
|
616 |
|
|
wait until pclk'event and pclk = '1';
|
617 |
|
|
wait until pclk'event and pclk = '1';
|
618 |
|
|
wait until pclk'event and pclk = '1';
|
619 |
|
|
wait until pclk'event and pclk = '1';
|
620 |
|
|
wait until pclk'event and pclk = '1';
|
621 |
|
|
wait until pclk'event and pclk = '1';
|
622 |
|
|
wait until pclk'event and pclk = '1';
|
623 |
|
|
wait until pclk'event and pclk = '1';
|
624 |
|
|
dut_end <= '1';
|
625 |
|
|
dut_bytes <= b"11";
|
626 |
|
|
wait until pclk'event and pclk = '1';
|
627 |
|
|
dut_end <= '0';
|
628 |
9 |
jdoin |
dut_di_wr <= '0';
|
629 |
2 |
jdoin |
if dut_error /= '1' and dut_do_valid /= '1' then
|
630 |
|
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
631 |
|
|
wait until pclk'event and pclk = '1';
|
632 |
|
|
end loop;
|
633 |
|
|
end if;
|
634 |
|
|
wait for CLK_PERIOD*20;
|
635 |
|
|
|
636 |
|
|
-- expected: 02779466 cdec1638 11d07881 5c633f21 90141308 1449002f 24aa3e80 f0b88ef7
|
637 |
|
|
assert dut_H0 = x"02779466" report "test #5 failed on H0" severity error;
|
638 |
|
|
assert dut_H1 = x"cdec1638" report "test #5 failed on H1" severity error;
|
639 |
|
|
assert dut_H2 = x"11d07881" report "test #5 failed on H2" severity error;
|
640 |
|
|
assert dut_H3 = x"5c633f21" report "test #5 failed on H3" severity error;
|
641 |
|
|
assert dut_H4 = x"90141308" report "test #5 failed on H4" severity error;
|
642 |
|
|
assert dut_H5 = x"1449002f" report "test #5 failed on H5" severity error;
|
643 |
|
|
assert dut_H6 = x"24aa3e80" report "test #5 failed on H6" severity error;
|
644 |
|
|
assert dut_H7 = x"f0b88ef7" report "test #5 failed on H7" severity error;
|
645 |
|
|
|
646 |
|
|
-------------------------------------------------------------------------------------------
|
647 |
|
|
-- test vector 6
|
648 |
|
|
-- src: NIST-ADDITIONAL-SHA256
|
649 |
|
|
-- #4) 56 bytes of zeros
|
650 |
|
|
-- msg := 56 x"00"
|
651 |
|
|
-- hash:= d4817aa5 497628e7 c77e6b60 6107042b bba31308 88c5f47a 375e6179 be789fbb
|
652 |
|
|
test_case <= 6;
|
653 |
|
|
dut_ce <= '0';
|
654 |
|
|
dut_di <= (others => '0');
|
655 |
|
|
dut_bytes <= b"00";
|
656 |
|
|
dut_start <= '0';
|
657 |
|
|
dut_end <= '0';
|
658 |
9 |
jdoin |
dut_di_wr <= '0';
|
659 |
2 |
jdoin |
wait until pclk'event and pclk = '1';
|
660 |
|
|
dut_ce <= '1';
|
661 |
|
|
dut_start <= '1';
|
662 |
6 |
jdoin |
dut_di <= x"00000000";
|
663 |
|
|
dut_bytes <= b"00";
|
664 |
2 |
jdoin |
wait until pclk'event and pclk = '1';
|
665 |
|
|
dut_start <= '0';
|
666 |
9 |
jdoin |
dut_di_wr <= '1';
|
667 |
|
|
if dut_di_req = '0' then
|
668 |
|
|
wait until dut_di_req = '1';
|
669 |
|
|
end if;
|
670 |
2 |
jdoin |
wait until pclk'event and pclk = '1';
|
671 |
|
|
wait until pclk'event and pclk = '1';
|
672 |
|
|
wait until pclk'event and pclk = '1';
|
673 |
|
|
wait until pclk'event and pclk = '1';
|
674 |
|
|
wait until pclk'event and pclk = '1';
|
675 |
|
|
wait until pclk'event and pclk = '1';
|
676 |
|
|
wait until pclk'event and pclk = '1';
|
677 |
|
|
wait until pclk'event and pclk = '1';
|
678 |
|
|
wait until pclk'event and pclk = '1';
|
679 |
|
|
wait until pclk'event and pclk = '1';
|
680 |
|
|
wait until pclk'event and pclk = '1';
|
681 |
|
|
wait until pclk'event and pclk = '1';
|
682 |
|
|
wait until pclk'event and pclk = '1';
|
683 |
|
|
dut_end <= '1';
|
684 |
|
|
wait until pclk'event and pclk = '1';
|
685 |
|
|
dut_end <= '0';
|
686 |
9 |
jdoin |
dut_di_wr <= '0';
|
687 |
2 |
jdoin |
if dut_error /= '1' and dut_do_valid /= '1' then
|
688 |
|
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
689 |
|
|
wait until pclk'event and pclk = '1';
|
690 |
|
|
end loop;
|
691 |
|
|
end if;
|
692 |
|
|
wait for CLK_PERIOD*20;
|
693 |
|
|
|
694 |
|
|
-- expected: d4817aa5 497628e7 c77e6b60 6107042b bba31308 88c5f47a 375e6179 be789fbb
|
695 |
|
|
assert dut_H0 = x"d4817aa5" report "test #6 failed on H0" severity error;
|
696 |
|
|
assert dut_H1 = x"497628e7" report "test #6 failed on H1" severity error;
|
697 |
|
|
assert dut_H2 = x"c77e6b60" report "test #6 failed on H2" severity error;
|
698 |
|
|
assert dut_H3 = x"6107042b" report "test #6 failed on H3" severity error;
|
699 |
|
|
assert dut_H4 = x"bba31308" report "test #6 failed on H4" severity error;
|
700 |
|
|
assert dut_H5 = x"88c5f47a" report "test #6 failed on H5" severity error;
|
701 |
|
|
assert dut_H6 = x"375e6179" report "test #6 failed on H6" severity error;
|
702 |
|
|
assert dut_H7 = x"be789fbb" report "test #6 failed on H7" severity error;
|
703 |
|
|
|
704 |
|
|
-------------------------------------------------------------------------------------------
|
705 |
|
|
-- test vector 7
|
706 |
|
|
-- src: NIST-ADDITIONAL-SHA256
|
707 |
|
|
-- #5) 57 bytes of zeros
|
708 |
|
|
-- msg := 57 x"00"
|
709 |
|
|
-- hash:= 65a16cb7 861335d5 ace3c607 18b5052e 44660726 da4cd13b b745381b 235a1785
|
710 |
|
|
test_case <= 7;
|
711 |
|
|
dut_ce <= '0';
|
712 |
|
|
dut_di <= (others => '0');
|
713 |
|
|
dut_bytes <= b"00";
|
714 |
|
|
dut_start <= '0';
|
715 |
|
|
dut_end <= '0';
|
716 |
9 |
jdoin |
dut_di_wr <= '0';
|
717 |
2 |
jdoin |
wait until pclk'event and pclk = '1';
|
718 |
|
|
dut_ce <= '1';
|
719 |
|
|
dut_start <= '1';
|
720 |
6 |
jdoin |
dut_di <= x"00000000";
|
721 |
|
|
dut_bytes <= b"00";
|
722 |
2 |
jdoin |
wait until pclk'event and pclk = '1';
|
723 |
|
|
dut_start <= '0';
|
724 |
9 |
jdoin |
dut_di_wr <= '1';
|
725 |
|
|
if dut_di_req = '0' then
|
726 |
|
|
wait until dut_di_req = '1';
|
727 |
|
|
end if;
|
728 |
2 |
jdoin |
wait until pclk'event and pclk = '1';
|
729 |
|
|
wait until pclk'event and pclk = '1';
|
730 |
|
|
wait until pclk'event and pclk = '1';
|
731 |
|
|
wait until pclk'event and pclk = '1';
|
732 |
|
|
wait until pclk'event and pclk = '1';
|
733 |
|
|
wait until pclk'event and pclk = '1';
|
734 |
|
|
wait until pclk'event and pclk = '1';
|
735 |
|
|
wait until pclk'event and pclk = '1';
|
736 |
|
|
wait until pclk'event and pclk = '1';
|
737 |
|
|
wait until pclk'event and pclk = '1';
|
738 |
|
|
wait until pclk'event and pclk = '1';
|
739 |
|
|
wait until pclk'event and pclk = '1';
|
740 |
|
|
wait until pclk'event and pclk = '1';
|
741 |
|
|
wait until pclk'event and pclk = '1';
|
742 |
|
|
dut_end <= '1';
|
743 |
|
|
dut_bytes <= b"01";
|
744 |
|
|
wait until pclk'event and pclk = '1';
|
745 |
|
|
dut_end <= '0';
|
746 |
9 |
jdoin |
dut_di_wr <= '0';
|
747 |
2 |
jdoin |
if dut_error /= '1' and dut_do_valid /= '1' then
|
748 |
|
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
749 |
|
|
wait until pclk'event and pclk = '1';
|
750 |
|
|
end loop;
|
751 |
|
|
end if;
|
752 |
|
|
wait for CLK_PERIOD*20;
|
753 |
|
|
|
754 |
|
|
-- expected: 65a16cb7 861335d5 ace3c607 18b5052e 44660726 da4cd13b b745381b 235a1785
|
755 |
|
|
assert dut_H0 = x"65a16cb7" report "test #7 failed on H0" severity error;
|
756 |
|
|
assert dut_H1 = x"861335d5" report "test #7 failed on H1" severity error;
|
757 |
|
|
assert dut_H2 = x"ace3c607" report "test #7 failed on H2" severity error;
|
758 |
|
|
assert dut_H3 = x"18b5052e" report "test #7 failed on H3" severity error;
|
759 |
|
|
assert dut_H4 = x"44660726" report "test #7 failed on H4" severity error;
|
760 |
|
|
assert dut_H5 = x"da4cd13b" report "test #7 failed on H5" severity error;
|
761 |
|
|
assert dut_H6 = x"b745381b" report "test #7 failed on H6" severity error;
|
762 |
|
|
assert dut_H7 = x"235a1785" report "test #7 failed on H7" severity error;
|
763 |
|
|
|
764 |
|
|
-------------------------------------------------------------------------------------------
|
765 |
|
|
-- test vector 8
|
766 |
|
|
-- src: NIST-ADDITIONAL-SHA256
|
767 |
|
|
-- #6) 64 bytes of zeros
|
768 |
|
|
-- msg := 64 x"00"
|
769 |
|
|
-- hash:= f5a5fd42 d16a2030 2798ef6e d309979b 43003d23 20d9f0e8 ea9831a9 2759fb4b
|
770 |
|
|
test_case <= 8;
|
771 |
|
|
dut_ce <= '0';
|
772 |
|
|
dut_di <= (others => '0');
|
773 |
|
|
dut_bytes <= b"00";
|
774 |
|
|
dut_start <= '0';
|
775 |
|
|
dut_end <= '0';
|
776 |
9 |
jdoin |
dut_di_wr <= '0';
|
777 |
2 |
jdoin |
wait until pclk'event and pclk = '1';
|
778 |
|
|
dut_ce <= '1';
|
779 |
|
|
dut_start <= '1';
|
780 |
6 |
jdoin |
dut_di <= x"00000000";
|
781 |
|
|
dut_bytes <= b"00";
|
782 |
2 |
jdoin |
wait until pclk'event and pclk = '1';
|
783 |
|
|
dut_start <= '0';
|
784 |
9 |
jdoin |
dut_di_wr <= '1';
|
785 |
|
|
if dut_di_req = '0' then
|
786 |
|
|
wait until dut_di_req = '1';
|
787 |
|
|
end if;
|
788 |
2 |
jdoin |
wait until pclk'event and pclk = '1';
|
789 |
|
|
wait until pclk'event and pclk = '1';
|
790 |
|
|
wait until pclk'event and pclk = '1';
|
791 |
|
|
wait until pclk'event and pclk = '1';
|
792 |
|
|
wait until pclk'event and pclk = '1';
|
793 |
|
|
wait until pclk'event and pclk = '1';
|
794 |
|
|
wait until pclk'event and pclk = '1';
|
795 |
|
|
wait until pclk'event and pclk = '1';
|
796 |
|
|
wait until pclk'event and pclk = '1';
|
797 |
|
|
wait until pclk'event and pclk = '1';
|
798 |
|
|
wait until pclk'event and pclk = '1';
|
799 |
|
|
wait until pclk'event and pclk = '1';
|
800 |
|
|
wait until pclk'event and pclk = '1';
|
801 |
|
|
wait until pclk'event and pclk = '1';
|
802 |
|
|
wait until pclk'event and pclk = '1';
|
803 |
|
|
dut_end <= '1';
|
804 |
|
|
wait until pclk'event and pclk = '1';
|
805 |
|
|
dut_end <= '0';
|
806 |
9 |
jdoin |
dut_di_wr <= '0';
|
807 |
2 |
jdoin |
if dut_error /= '1' and dut_do_valid /= '1' then
|
808 |
|
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
809 |
|
|
wait until pclk'event and pclk = '1';
|
810 |
|
|
end loop;
|
811 |
|
|
end if;
|
812 |
|
|
wait for CLK_PERIOD*20;
|
813 |
|
|
|
814 |
|
|
-- expected: f5a5fd42 d16a2030 2798ef6e d309979b 43003d23 20d9f0e8 ea9831a9 2759fb4b
|
815 |
|
|
assert dut_H0 = x"f5a5fd42" report "test #8 failed on H0" severity error;
|
816 |
|
|
assert dut_H1 = x"d16a2030" report "test #8 failed on H1" severity error;
|
817 |
|
|
assert dut_H2 = x"2798ef6e" report "test #8 failed on H2" severity error;
|
818 |
|
|
assert dut_H3 = x"d309979b" report "test #8 failed on H3" severity error;
|
819 |
|
|
assert dut_H4 = x"43003d23" report "test #8 failed on H4" severity error;
|
820 |
|
|
assert dut_H5 = x"20d9f0e8" report "test #8 failed on H5" severity error;
|
821 |
|
|
assert dut_H6 = x"ea9831a9" report "test #8 failed on H6" severity error;
|
822 |
|
|
assert dut_H7 = x"2759fb4b" report "test #8 failed on H7" severity error;
|
823 |
|
|
|
824 |
|
|
-------------------------------------------------------------------------------------------
|
825 |
|
|
-- test vector 9
|
826 |
|
|
-- src: NIST-ADDITIONAL-SHA256
|
827 |
|
|
-- #7) 1000 bytes of zeros
|
828 |
|
|
-- msg := 1000 x"00"
|
829 |
|
|
-- hash:= 541b3e9d aa09b20b f85fa273 e5cbd3e8 0185aa4e c298e765 db87742b 70138a53
|
830 |
|
|
test_case <= 9;
|
831 |
|
|
dut_ce <= '0';
|
832 |
|
|
dut_di <= (others => '0');
|
833 |
|
|
dut_bytes <= b"00";
|
834 |
|
|
dut_start <= '0';
|
835 |
|
|
dut_end <= '0';
|
836 |
9 |
jdoin |
dut_di_wr <= '0';
|
837 |
2 |
jdoin |
wait until pclk'event and pclk = '1';
|
838 |
|
|
dut_ce <= '1';
|
839 |
|
|
dut_start <= '1';
|
840 |
|
|
wait until pclk'event and pclk = '1';
|
841 |
|
|
dut_start <= '0';
|
842 |
|
|
dut_bytes <= b"00";
|
843 |
|
|
dut_di <= x"00000000";
|
844 |
|
|
count_words := 0;
|
845 |
|
|
words <= count_words;
|
846 |
|
|
count_blocks := 0;
|
847 |
|
|
blocks <= count_blocks;
|
848 |
|
|
loop
|
849 |
|
|
wait until dut_di_req = '1';
|
850 |
9 |
jdoin |
wait until pclk'event and pclk = '1';
|
851 |
|
|
dut_di_wr <= '1';
|
852 |
2 |
jdoin |
loop
|
853 |
|
|
wait until pclk'event and pclk = '1';
|
854 |
|
|
count_words := count_words + 1;
|
855 |
|
|
words <= count_words;
|
856 |
|
|
exit when words = 15;
|
857 |
|
|
end loop;
|
858 |
9 |
jdoin |
dut_di_wr <= '0';
|
859 |
2 |
jdoin |
count_words := 0;
|
860 |
|
|
words <= count_words;
|
861 |
|
|
count_blocks := count_blocks + 1;
|
862 |
|
|
blocks <= count_blocks;
|
863 |
|
|
exit when blocks = 14;
|
864 |
|
|
end loop;
|
865 |
|
|
count_words := 0;
|
866 |
|
|
words <= count_words;
|
867 |
|
|
wait until dut_di_req = '1';
|
868 |
9 |
jdoin |
wait until pclk'event and pclk = '1';
|
869 |
|
|
dut_di_wr <= '1';
|
870 |
2 |
jdoin |
loop
|
871 |
|
|
wait until pclk'event and pclk = '1';
|
872 |
|
|
count_words := count_words + 1;
|
873 |
|
|
words <= count_words;
|
874 |
|
|
exit when words = 8;
|
875 |
|
|
end loop;
|
876 |
|
|
dut_end <= '1';
|
877 |
|
|
wait until pclk'event and pclk = '1';
|
878 |
|
|
dut_end <= '0';
|
879 |
9 |
jdoin |
dut_di_wr <= '0';
|
880 |
2 |
jdoin |
if dut_error /= '1' and dut_do_valid /= '1' then
|
881 |
|
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
882 |
|
|
wait until pclk'event and pclk = '1';
|
883 |
|
|
end loop;
|
884 |
|
|
end if;
|
885 |
|
|
wait for CLK_PERIOD*20;
|
886 |
|
|
|
887 |
|
|
-- expected: 541b3e9d aa09b20b f85fa273 e5cbd3e8 0185aa4e c298e765 db87742b 70138a53
|
888 |
|
|
assert dut_H0 = x"541b3e9d" report "test #9 failed on H0" severity error;
|
889 |
|
|
assert dut_H1 = x"aa09b20b" report "test #9 failed on H1" severity error;
|
890 |
|
|
assert dut_H2 = x"f85fa273" report "test #9 failed on H2" severity error;
|
891 |
|
|
assert dut_H3 = x"e5cbd3e8" report "test #9 failed on H3" severity error;
|
892 |
|
|
assert dut_H4 = x"0185aa4e" report "test #9 failed on H4" severity error;
|
893 |
|
|
assert dut_H5 = x"c298e765" report "test #9 failed on H5" severity error;
|
894 |
|
|
assert dut_H6 = x"db87742b" report "test #9 failed on H6" severity error;
|
895 |
|
|
assert dut_H7 = x"70138a53" report "test #9 failed on H7" severity error;
|
896 |
|
|
|
897 |
|
|
-------------------------------------------------------------------------------------------
|
898 |
|
|
-- test vector 10
|
899 |
|
|
-- src: NIST-ADDITIONAL-SHA256
|
900 |
|
|
-- #8) 1000 bytes of 0x41 'A'
|
901 |
|
|
-- msg := 1000 x"41"
|
902 |
|
|
-- hash:= c2e68682 3489ced2 017f6059 b8b23931 8b6364f6 dcd835d0 a519105a 1eadd6e4
|
903 |
|
|
test_case <= 10;
|
904 |
|
|
dut_ce <= '0';
|
905 |
|
|
dut_di <= (others => '0');
|
906 |
|
|
dut_bytes <= b"00";
|
907 |
|
|
dut_start <= '0';
|
908 |
|
|
dut_end <= '0';
|
909 |
9 |
jdoin |
dut_di_wr <= '0';
|
910 |
2 |
jdoin |
wait until pclk'event and pclk = '1';
|
911 |
|
|
dut_ce <= '1';
|
912 |
|
|
dut_start <= '1';
|
913 |
|
|
wait until pclk'event and pclk = '1';
|
914 |
|
|
dut_start <= '0';
|
915 |
|
|
dut_bytes <= b"00";
|
916 |
|
|
dut_di <= x"41414141";
|
917 |
|
|
count_words := 0;
|
918 |
|
|
words <= count_words;
|
919 |
|
|
count_blocks := 0;
|
920 |
|
|
blocks <= count_blocks;
|
921 |
|
|
loop
|
922 |
|
|
wait until dut_di_req = '1';
|
923 |
9 |
jdoin |
wait until pclk'event and pclk = '1';
|
924 |
|
|
dut_di_wr <= '1';
|
925 |
2 |
jdoin |
loop
|
926 |
|
|
wait until pclk'event and pclk = '1';
|
927 |
|
|
count_words := count_words + 1;
|
928 |
|
|
words <= count_words;
|
929 |
|
|
exit when words = 15;
|
930 |
|
|
end loop;
|
931 |
9 |
jdoin |
dut_di_wr <= '0';
|
932 |
2 |
jdoin |
count_words := 0;
|
933 |
|
|
words <= count_words;
|
934 |
|
|
count_blocks := count_blocks + 1;
|
935 |
|
|
blocks <= count_blocks;
|
936 |
|
|
exit when blocks = 14;
|
937 |
|
|
end loop;
|
938 |
|
|
count_words := 0;
|
939 |
|
|
words <= count_words;
|
940 |
|
|
wait until dut_di_req = '1';
|
941 |
9 |
jdoin |
wait until pclk'event and pclk = '1';
|
942 |
|
|
dut_di_wr <= '1';
|
943 |
2 |
jdoin |
loop
|
944 |
|
|
wait until pclk'event and pclk = '1';
|
945 |
|
|
count_words := count_words + 1;
|
946 |
|
|
words <= count_words;
|
947 |
|
|
exit when words = 8;
|
948 |
|
|
end loop;
|
949 |
|
|
dut_end <= '1';
|
950 |
|
|
wait until pclk'event and pclk = '1';
|
951 |
|
|
dut_end <= '0';
|
952 |
9 |
jdoin |
dut_di_wr <= '0';
|
953 |
2 |
jdoin |
if dut_error /= '1' and dut_do_valid /= '1' then
|
954 |
|
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
955 |
|
|
wait until pclk'event and pclk = '1';
|
956 |
|
|
end loop;
|
957 |
|
|
end if;
|
958 |
|
|
wait for CLK_PERIOD*20;
|
959 |
|
|
|
960 |
|
|
-- expected: c2e68682 3489ced2 017f6059 b8b23931 8b6364f6 dcd835d0 a519105a 1eadd6e4
|
961 |
|
|
assert dut_H0 = x"c2e68682" report "test #10 failed on H0" severity error;
|
962 |
|
|
assert dut_H1 = x"3489ced2" report "test #10 failed on H1" severity error;
|
963 |
|
|
assert dut_H2 = x"017f6059" report "test #10 failed on H2" severity error;
|
964 |
|
|
assert dut_H3 = x"b8b23931" report "test #10 failed on H3" severity error;
|
965 |
|
|
assert dut_H4 = x"8b6364f6" report "test #10 failed on H4" severity error;
|
966 |
|
|
assert dut_H5 = x"dcd835d0" report "test #10 failed on H5" severity error;
|
967 |
|
|
assert dut_H6 = x"a519105a" report "test #10 failed on H6" severity error;
|
968 |
|
|
assert dut_H7 = x"1eadd6e4" report "test #10 failed on H7" severity error;
|
969 |
|
|
|
970 |
|
|
-------------------------------------------------------------------------------------------
|
971 |
|
|
-- test vector 11
|
972 |
|
|
-- src: NIST-ADDITIONAL-SHA256
|
973 |
|
|
-- #9) 1005 bytes of 0x55 'U'
|
974 |
|
|
-- msg := 1000 x"55"
|
975 |
|
|
-- hash:= f4d62dde c0f3dd90 ea1380fa 16a5ff8d c4c54b21 740650f2 4afc4120 903552b0
|
976 |
|
|
test_case <= 11;
|
977 |
|
|
dut_ce <= '0';
|
978 |
|
|
dut_di <= (others => '0');
|
979 |
|
|
dut_bytes <= b"00";
|
980 |
|
|
dut_start <= '0';
|
981 |
|
|
dut_end <= '0';
|
982 |
9 |
jdoin |
dut_di_wr <= '0';
|
983 |
2 |
jdoin |
wait until pclk'event and pclk = '1';
|
984 |
|
|
dut_ce <= '1';
|
985 |
|
|
dut_start <= '1';
|
986 |
|
|
wait until pclk'event and pclk = '1';
|
987 |
|
|
dut_start <= '0';
|
988 |
|
|
dut_bytes <= b"00";
|
989 |
|
|
dut_di <= x"55555555";
|
990 |
|
|
count_words := 0;
|
991 |
|
|
words <= count_words;
|
992 |
|
|
count_blocks := 0;
|
993 |
|
|
blocks <= count_blocks;
|
994 |
|
|
loop
|
995 |
|
|
wait until dut_di_req = '1';
|
996 |
9 |
jdoin |
wait until pclk'event and pclk = '1';
|
997 |
|
|
dut_di_wr <= '1';
|
998 |
2 |
jdoin |
loop
|
999 |
|
|
wait until pclk'event and pclk = '1';
|
1000 |
|
|
count_words := count_words + 1;
|
1001 |
|
|
words <= count_words;
|
1002 |
|
|
exit when words = 15;
|
1003 |
|
|
end loop;
|
1004 |
9 |
jdoin |
dut_di_wr <= '0';
|
1005 |
2 |
jdoin |
count_words := 0;
|
1006 |
|
|
words <= count_words;
|
1007 |
|
|
count_blocks := count_blocks + 1;
|
1008 |
|
|
blocks <= count_blocks;
|
1009 |
|
|
exit when blocks = 14;
|
1010 |
|
|
end loop;
|
1011 |
|
|
count_words := 0;
|
1012 |
|
|
words <= count_words;
|
1013 |
|
|
wait until dut_di_req = '1';
|
1014 |
9 |
jdoin |
wait until pclk'event and pclk = '1';
|
1015 |
|
|
dut_di_wr <= '1';
|
1016 |
2 |
jdoin |
loop
|
1017 |
|
|
wait until pclk'event and pclk = '1';
|
1018 |
|
|
count_words := count_words + 1;
|
1019 |
|
|
words <= count_words;
|
1020 |
|
|
exit when words = 9;
|
1021 |
|
|
end loop;
|
1022 |
|
|
wait until pclk'event and pclk = '1';
|
1023 |
|
|
dut_bytes <= b"01";
|
1024 |
|
|
dut_end <= '1';
|
1025 |
|
|
wait until pclk'event and pclk = '1';
|
1026 |
|
|
dut_end <= '0';
|
1027 |
9 |
jdoin |
dut_di_wr <= '0';
|
1028 |
2 |
jdoin |
if dut_error /= '1' and dut_do_valid /= '1' then
|
1029 |
|
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
1030 |
|
|
wait until pclk'event and pclk = '1';
|
1031 |
|
|
end loop;
|
1032 |
|
|
end if;
|
1033 |
|
|
wait for CLK_PERIOD*20;
|
1034 |
|
|
|
1035 |
|
|
-- expected: f4d62dde c0f3dd90 ea1380fa 16a5ff8d c4c54b21 740650f2 4afc4120 903552b0
|
1036 |
|
|
assert dut_H0 = x"f4d62dde" report "test #11 failed on H0" severity error;
|
1037 |
|
|
assert dut_H1 = x"c0f3dd90" report "test #11 failed on H1" severity error;
|
1038 |
|
|
assert dut_H2 = x"ea1380fa" report "test #11 failed on H2" severity error;
|
1039 |
|
|
assert dut_H3 = x"16a5ff8d" report "test #11 failed on H3" severity error;
|
1040 |
|
|
assert dut_H4 = x"c4c54b21" report "test #11 failed on H4" severity error;
|
1041 |
|
|
assert dut_H5 = x"740650f2" report "test #11 failed on H5" severity error;
|
1042 |
|
|
assert dut_H6 = x"4afc4120" report "test #11 failed on H6" severity error;
|
1043 |
|
|
assert dut_H7 = x"903552b0" report "test #11 failed on H7" severity error;
|
1044 |
|
|
|
1045 |
|
|
-------------------------------------------------------------------------------------------
|
1046 |
|
|
-- test vector 12
|
1047 |
|
|
-- src: NIST-ADDITIONAL-SHA256
|
1048 |
|
|
-- #10) 1000000 bytes of zeros
|
1049 |
|
|
-- msg := 1000000 x"00"
|
1050 |
|
|
-- hash:= d29751f2 649b32ff 572b5e0a 9f541ea6 60a50f94 ff0beedf b0b692b9 24cc8025
|
1051 |
|
|
test_case <= 12;
|
1052 |
|
|
dut_ce <= '0';
|
1053 |
|
|
dut_di <= (others => '0');
|
1054 |
|
|
dut_bytes <= b"00";
|
1055 |
|
|
dut_start <= '0';
|
1056 |
|
|
dut_end <= '0';
|
1057 |
9 |
jdoin |
dut_di_wr <= '0';
|
1058 |
2 |
jdoin |
wait until pclk'event and pclk = '1';
|
1059 |
|
|
dut_ce <= '1';
|
1060 |
|
|
dut_start <= '1';
|
1061 |
|
|
wait until pclk'event and pclk = '1';
|
1062 |
|
|
dut_start <= '0';
|
1063 |
|
|
dut_bytes <= b"00";
|
1064 |
|
|
dut_di <= x"00000000";
|
1065 |
|
|
count_words := 0;
|
1066 |
|
|
words <= count_words;
|
1067 |
|
|
count_blocks := 0;
|
1068 |
|
|
blocks <= count_blocks;
|
1069 |
|
|
loop
|
1070 |
|
|
wait until dut_di_req = '1';
|
1071 |
9 |
jdoin |
wait until pclk'event and pclk = '1';
|
1072 |
|
|
dut_di_wr <= '1';
|
1073 |
2 |
jdoin |
loop
|
1074 |
|
|
wait until pclk'event and pclk = '1';
|
1075 |
|
|
count_words := count_words + 1;
|
1076 |
|
|
words <= count_words;
|
1077 |
|
|
exit when words = 15;
|
1078 |
|
|
end loop;
|
1079 |
9 |
jdoin |
dut_di_wr <= '0';
|
1080 |
2 |
jdoin |
count_words := 0;
|
1081 |
|
|
words <= count_words;
|
1082 |
|
|
count_blocks := count_blocks + 1;
|
1083 |
|
|
blocks <= count_blocks;
|
1084 |
|
|
exit when blocks = 15623;
|
1085 |
|
|
end loop;
|
1086 |
|
|
count_words := 0;
|
1087 |
|
|
words <= count_words;
|
1088 |
|
|
wait until dut_di_req = '1';
|
1089 |
9 |
jdoin |
wait until pclk'event and pclk = '1';
|
1090 |
|
|
dut_di_wr <= '1';
|
1091 |
2 |
jdoin |
loop
|
1092 |
|
|
wait until pclk'event and pclk = '1';
|
1093 |
|
|
count_words := count_words + 1;
|
1094 |
|
|
words <= count_words;
|
1095 |
|
|
exit when words = 14;
|
1096 |
|
|
end loop;
|
1097 |
|
|
dut_end <= '1';
|
1098 |
|
|
wait until pclk'event and pclk = '1';
|
1099 |
|
|
dut_end <= '0';
|
1100 |
9 |
jdoin |
dut_di_wr <= '0';
|
1101 |
2 |
jdoin |
if dut_error /= '1' and dut_do_valid /= '1' then
|
1102 |
|
|
while dut_error /= '1' and dut_do_valid /= '1' loop
|
1103 |
|
|
wait until pclk'event and pclk = '1';
|
1104 |
|
|
end loop;
|
1105 |
|
|
end if;
|
1106 |
|
|
wait for CLK_PERIOD*20;
|
1107 |
|
|
|
1108 |
|
|
-- expected: d29751f2 649b32ff 572b5e0a 9f541ea6 60a50f94 ff0beedf b0b692b9 24cc8025
|
1109 |
|
|
assert dut_H0 = x"d29751f2" report "test #12 failed on H0" severity error;
|
1110 |
|
|
assert dut_H1 = x"649b32ff" report "test #12 failed on H1" severity error;
|
1111 |
|
|
assert dut_H2 = x"572b5e0a" report "test #12 failed on H2" severity error;
|
1112 |
|
|
assert dut_H3 = x"9f541ea6" report "test #12 failed on H3" severity error;
|
1113 |
|
|
assert dut_H4 = x"60a50f94" report "test #12 failed on H4" severity error;
|
1114 |
|
|
assert dut_H5 = x"ff0beedf" report "test #12 failed on H5" severity error;
|
1115 |
|
|
assert dut_H6 = x"b0b692b9" report "test #12 failed on H6" severity error;
|
1116 |
|
|
assert dut_H7 = x"24cc8025" report "test #12 failed on H7" severity error;
|
1117 |
|
|
|
1118 |
|
|
|
1119 |
|
|
assert false report "End Simulation" severity failure; -- stop simulation
|
1120 |
|
|
end process tb1;
|
1121 |
|
|
-- End Test Bench
|
1122 |
|
|
END;
|