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homer.hsin |
/*
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* Copyright 2013, Homer Hsing <homer.hsing@gmail.com>
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/* "is_last" == 0 means byte number is 8, no matter what value "byte_num" is. */
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/* if "in_ready" == 0, then "is_last" should be 0. */
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/* the user switch to next "in" only if "ack" == 1. */
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`define low_pos(w,b) ((w)*64 + (b)*8)
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`define low_pos2(w,b) `low_pos(w,7-b)
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`define high_pos(w,b) (`low_pos(w,b) + 7)
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`define high_pos2(w,b) (`low_pos2(w,b) + 7)
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module keccak(clk, reset, in, in_ready, is_last, byte_num, buffer_full, out, out_ready);
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input clk, reset;
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input [63:0] in;
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input in_ready, is_last;
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input [2:0] byte_num;
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output buffer_full; /* to "user" module */
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output [511:0] out;
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output reg out_ready;
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reg state; /* state == 0: user will send more input data
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* state == 1: user will not send any data */
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wire [575:0] padder_out,
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padder_out_1; /* before reorder byte */
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wire padder_out_ready;
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wire f_ack;
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wire [1599:0] f_out;
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wire f_out_ready;
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wire [511:0] out1; /* before reorder byte */
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reg [10:0] i; /* gen "out_ready" */
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genvar w, b;
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assign out1 = f_out[1599:1599-511];
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always @ (posedge clk)
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if (reset)
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i <= 0;
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else
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i <= {i[9:0], state & f_ack};
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always @ (posedge clk)
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if (reset)
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state <= 0;
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else if (is_last)
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state <= 1;
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/* reorder byte ~ ~ */
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generate
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for(w=0; w<8; w=w+1)
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begin : L0
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for(b=0; b<8; b=b+1)
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begin : L1
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assign out[`high_pos(w,b):`low_pos(w,b)] = out1[`high_pos2(w,b):`low_pos2(w,b)];
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end
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end
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endgenerate
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generate
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for(w=0; w<9; w=w+1)
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begin : L2
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for(b=0; b<8; b=b+1)
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begin : L3
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assign padder_out[`high_pos(w,b):`low_pos(w,b)] = padder_out_1[`high_pos2(w,b):`low_pos2(w,b)];
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end
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end
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endgenerate
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always @ (posedge clk)
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if (reset)
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out_ready <= 0;
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else if (i[10])
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out_ready <= 1;
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padder
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padder_ (clk, reset, in, in_ready, is_last, byte_num, buffer_full, padder_out_1, padder_out_ready, f_ack);
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f_permutation
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f_permutation_ (clk, reset, padder_out, padder_out_ready, f_ack, f_out, f_out_ready);
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endmodule
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`undef low_pos
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`undef low_pos2
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`undef high_pos
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`undef high_pos2
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