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homer.hsin |
/*
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* Copyright 2013, Homer Hsing <homer.hsing@gmail.com>
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/* "is_last" == 0 means byte number is 4, no matter what value "byte_num" is. */
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/* if "in_ready" == 0, then "is_last" should be 0. */
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/* the user switch to next "in" only if "ack" == 1. */
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module padder(clk, reset, in, in_ready, is_last, byte_num, buffer_full, out, out_ready, f_ack);
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input clk, reset;
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input [31:0] in;
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input in_ready, is_last;
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input [1:0] byte_num;
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output buffer_full; /* to "user" module */
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output reg [575:0] out; /* to "f_permutation" module */
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output out_ready; /* to "f_permutation" module */
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input f_ack; /* from "f_permutation" module */
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reg state; /* state == 0: user will send more input data
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* state == 1: user will not send any data */
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reg done; /* == 1: out_ready should be 0 */
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reg [17:0] i; /* length of "out" buffer */
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wire [31:0] v0; /* output of module "padder1" */
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reg [31:0] v1; /* to be shifted into register "out" */
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wire accept, /* accept user input? */
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update;
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assign buffer_full = i[17];
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assign out_ready = buffer_full;
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assign accept = (~ state) & in_ready & (~ buffer_full); // if state == 1, do not eat input
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assign update = (accept | (state & (~ buffer_full))) & (~ done); // don't fill buffer if done
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always @ (posedge clk)
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if (reset)
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out <= 0;
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else if (update)
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out <= {out[575-32:0], v1};
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always @ (posedge clk)
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if (reset)
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i <= 0;
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else if (f_ack | update)
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i <= {i[16:0], 1'b1} & {18{~ f_ack}};
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/* if (f_ack) i <= 0; */
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/* if (update) i <= {i[16:0], 1'b1}; // increase length */
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always @ (posedge clk)
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if (reset)
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state <= 0;
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else if (is_last)
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state <= 1;
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always @ (posedge clk)
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if (reset)
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done <= 0;
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else if (state & out_ready)
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done <= 1;
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padder1 p0 (in, byte_num, v0);
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always @ (*)
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begin
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if (state)
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begin
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v1 = 0;
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v1[7] = v1[7] | i[16]; // "v1[7]" is the MSB of the last byte of "v1"
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end
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else if (is_last == 0)
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v1 = in;
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else
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begin
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v1 = v0;
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v1[7] = v1[7] | i[16];
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end
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end
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endmodule
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