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https://opencores.org/ocsvn/sigma_delta_dac_dual_loop/sigma_delta_dac_dual_loop/trunk
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wzab |
This project implements 2nd order DAC implementable in FPGA.
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The converter generates 1-bit digital signal on the dout output.
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You need to connect a simple RC lowpass filter to convert it into
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the analog signal.
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There are two implementations:
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dsm2 - allows to obtain higher clock frequency, and therefore
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higher oversampling ratio, but number of rising and falling
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slopes in time unit depends on signal value. Therefore
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you may experience nonlinear distortions if those two slopes
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are not symmetrical.
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dsm3 - The output of the DAC is updated once every three clock pulses.
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If there is a '1' on the DAC output, the sequence '110' is generated
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on the dout output. If there is a '0' on the DAC output, the sequence
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'100' is generated. Therefore we always have one rising slope and one
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falling slope generated in each DAC cycle.
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Unfortunately this implementation accepts lower clock frequencies,
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so the oversampling ratio is lower
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To check DAC performance without putting it into real hardware, you can
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run "make" command in the appropriate directory (it requires free tools:
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ghdl, python and pylab). You'll see the spectra of the output signal
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(before low pass filtering) consisting of three sinusoids.
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