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[/] [signed_integer_divider/] [trunk/] [divider_dshift.v] - Blame information for rev 2

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module  divider_dshift(
input   i_clk,
input   i_rst,
input   [31:0]i_dividend,
input   [31:0]i_divisor,
input   i_start,
output  o_ready,
output  reg     [31:0]o_quotient,
output  reg     [31:0]o_remainder
);
 
parameter
                state_1=1,
                state_2=2,
                state_3=4,
                state_4=8,
                state_5=16,
                state_6=32;
 
 
reg     [31:0]PR;                //partial remainder
reg     signed[31:0]PR_1;
reg     [31:0]DR;                //divisor
reg     [5:0]ct,ct_1;            // ct: index for quotient bit under calculation ct_1: shift value for last PR
reg     ct_1_en,ct_1_en_1;                      // enable calculating of ct_1
reg     DD_sign;                //sign of dividend
reg     [5:0]state;
reg     ready;
assign  o_ready=ready?i_start:0;
reg     [30:0]nq;        //negative quotient
reg     [30:0]q; //positive quotient
wire    [30:0]nqp1;      // nq+1
wire    [30:0]qp1;       // q+1
assign  nqp1=nq+1;
assign  qp1=q+1;
 
wire    [31:0]nDR;
assign  nDR=~DR;
wire    nsub;   // not sub      '1' means PR=PR+DR;
                //              '0' means PR=PR-DR;
assign  nsub=PR[31]^DR[31];
 
 
/// over subtract detection during final results adjustment
wire    over_sub;
//assign        over_sub=(state==state_4)||(state==state_3)?DD_sign^PR[62]&(PR[62:31]!=0):0;
assign  over_sub=(DD_sign^PR[31])&(PR[31:0]!=0);
//reg   over_sub;
wire    addback_nDR;
wire    addback_DR;
assign  addback_nDR=over_sub&(~nsub);
assign  addback_DR=over_sub&nsub;
///
/// results adjustment
wire    [30:0]final_nq,final_q;
assign  final_nq=addback_DR?nqp1:nq;
assign  final_q=addback_nDR?qp1:q;
wire    [31:0]remainder_addback;
assign  remainder_addback=      addback_DR?i_divisor:
                                addback_nDR?~i_divisor:0;
///
 
/// main subtractor 
wire    [31:0]a,b;
wire    [31:0]sum;
wire    carry_in;
wire    carry_out;
 
reg     [31:0]reg_a,reg_b;
reg     reg_carry;
reg     [1:0]state_reg;
 
///////////// Dynamic Shift /////////////
reg     [4:0]shifted,shifted_1;
reg     [31:0]sdata;
wire    [31:0]sdata_o;
wire    [4:0]shifted_o;
shifter shifter_0(
sdata,
sdata_o,
shifted_o
);
 
/*
assign  a=
                state==state_4?{1'b1,~final_nq}:
                state==state_5?remainder_addback:
                nsub?DR:nDR;
*/
assign  a=      ct_1_en?{27'd0,shifted_1}:
                state==state_4?{1'b1,~final_nq}:
                state==state_5?remainder_addback:
                nsub?DR:nDR;
assign  b=      ct_1_en?{26'd0,ct_1}:
                state==state_4?{1'b0,final_q}:
                state==state_5?PR_1:PR;
 
assign  carry_in=       ct_1_en?0:
                state==state_4?1:
                state==state_5? addback_nDR?1:0:
                nsub?0:1;
 
adder_32bit     adder_0(
reg_a,
reg_b,
reg_carry,
sum,
carry_out
);
 
 
 
 
// ct calculation
//reg   UDR;    // update Divisor
wire    [5:0]sum_ct;
wire    [25:0]sum_ct_h;
wire    carry_ct;
adder_32bit     adder_1(
{26'd0,ct},
state[5]?{27'd0,shifted}:~{27'd0,shifted},
state[5]?1'b0:1'b1,
{sum_ct_h,sum_ct},
carry_ct
);
 
 
 
 
 
 
///////////////////////////////////////////
 
always@(posedge i_clk or negedge i_rst)
        if(!i_rst)begin
                sdata<=0;
                shifted<=0;
                shifted_1<=0;
                PR<=0;
                PR_1<=0;
                DR<=0;
                //UDR<=0;
                ready<=0;
                ct<=0;
                ct_1<=0;
                ct_1_en<=0;
                ct_1_en_1<=0;
                state<=state_1;
                DD_sign<=0;
                o_quotient<=0;
                o_remainder<=0;
                nq<=0;
                q<=0;
                //over_sub<=0;
                reg_a<=0;
                reg_b<=0;
                reg_carry<=0;
                state_reg<=0;
        end
        else begin
                if(ready&&(!i_start))ready<=0;
                case(state_reg)
                0:
                case(state)
                        state_1:if((!ready)&&i_start)begin
                                sdata<=i_divisor;
                                state<=state_6;
                                q<=0;
                                nq<=0;
                                shifted<=0;
                                //UDR<=1;
                        end
                        state_2:begin
                                sdata<=i_dividend;
                                PR_1<=i_dividend;
                                DD_sign<=i_dividend[31];
                                state<=state_3;
                                state_reg<=1;
                        end
                        state_3:begin
                                if(ct[5])begin
                                        state<=state_4;
                                        ct<=0;
                                        state_reg<=2;
                                end
                                else begin
                                        ct_1_en<=1;
                                        shifted_1<=shifted;
                                        nq[ct]<=nsub;
                                        q[ct]<=~nsub;
                                        sdata<=sum;
                                        state_reg<=1;
                                end
                        end
                        state_4:begin
                                state<=state_5;
                                o_quotient<=sum;
                                PR_1<=PR_1>>>ct_1;
                                state_reg<=2;
                        end
                        state_5:begin
                                o_remainder<=sum;
                                ct_1<=0;
                                state<=state_1;
                                ready<=1;
                        end
 
                        state_6:begin
                                sdata<=sdata_o;
                                shifted<=shifted_o;
                                ct<=sum_ct;
                                if(sdata[31]!=sdata[30])begin
                                        state<=state_2;
                                        DR<=sdata;
                                end
                        end
/*
                        state_6:begin
                                //if(!over_sub)o_remainder<=sum>>>ct_1;
                                o_remainder<=sum;
                                ct_1<=0;
                                state<=state_1;
                                ready<=1;
                        end
 
*/
                endcase
                1:begin
                        PR<=sdata_o;
                        PR_1<=sdata;
/*
                        if(UDR)begin
                                UDR<=0;
                                ct<=shifted;
 
                                if(shifted==0)begin
                                        ct<=0;
                                end
                                else begin
                                        ct<=shifted-1;
                                        DR<={DR[31],DR[31:1]};
                                end
 
                        end
*/
                        shifted<=shifted_o;
                        state_reg<=2;
                        reg_a<=a;       //calculate ct_1
                        reg_b<=b;
                        reg_carry<=carry_in;
                        ct_1_en<=0;
                        ct_1_en_1<=ct_1_en;
                end
                2:begin
                        if(state==state_3)begin
                                ct<=sum_ct;
                        end
                        state_reg<=0;
                        if(ct_1_en_1)begin
                                ct_1<=sum[5:0];
                        end
                        ct_1_en_1<=0;
                        reg_a<=a;       // calculate PR
                        reg_b<=b;
                        reg_carry<=carry_in;
                end
                endcase
        end
 
 
 
 
endmodule

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Subversion Repositories signed_integer_divider

[/] [signed_integer_divider/] [trunk/] [divider_dshift.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	m99	`module divider_dshift(`
2			`input i_clk,`
3			`input i_rst,`
4			`input [31:0]i_dividend,`
5			`input [31:0]i_divisor,`
6			`input i_start,`
7			`output o_ready,`
8			`output reg [31:0]o_quotient,`
9			`output reg [31:0]o_remainder`
10			`);`
11
12			`parameter`
13			`state_1=1,`
14			`state_2=2,`
15			`state_3=4,`
16			`state_4=8,`
17			`state_5=16,`
18			`state_6=32;`
19
20
21			`reg [31:0]PR; //partial remainder`
22			`reg signed[31:0]PR_1;`
23			`reg [31:0]DR; //divisor`
24			`reg [5:0]ct,ct_1; // ct: index for quotient bit under calculation ct_1: shift value for last PR`
25			`reg ct_1_en,ct_1_en_1; // enable calculating of ct_1`
26			`reg DD_sign; //sign of dividend`
27			`reg [5:0]state;`
28			`reg ready;`
29			`assign o_ready=ready?i_start:0;`
30			`reg [30:0]nq; //negative quotient`
31			`reg [30:0]q; //positive quotient`
32			`wire [30:0]nqp1; // nq+1`
33			`wire [30:0]qp1; // q+1`
34			`assign nqp1=nq+1;`
35			`assign qp1=q+1;`
36
37			`wire [31:0]nDR;`
38			`assign nDR=~DR;`
39			`wire nsub; // not sub '1' means PR=PR+DR;`
40			`// '0' means PR=PR-DR;`
41			`assign nsub=PR[31]^DR[31];`
42
43
44			`/// over subtract detection during final results adjustment`
45			`wire over_sub;`
46			`//assign over_sub=(state==state_4)\|\|(state==state_3)?DD_sign^PR[62]&(PR[62:31]!=0):0;`
47			`assign over_sub=(DD_sign^PR[31])&(PR[31:0]!=0);`
48			`//reg over_sub;`
49			`wire addback_nDR;`
50			`wire addback_DR;`
51			`assign addback_nDR=over_sub&(~nsub);`
52			`assign addback_DR=over_sub&nsub;`
53			`///`
54			`/// results adjustment`
55			`wire [30:0]final_nq,final_q;`
56			`assign final_nq=addback_DR?nqp1:nq;`
57			`assign final_q=addback_nDR?qp1:q;`
58			`wire [31:0]remainder_addback;`
59			`assign remainder_addback= addback_DR?i_divisor:`
60			`addback_nDR?~i_divisor:0;`
61			`///`
62
63			`/// main subtractor`
64			`wire [31:0]a,b;`
65			`wire [31:0]sum;`
66			`wire carry_in;`
67			`wire carry_out;`
68
69			`reg [31:0]reg_a,reg_b;`
70			`reg reg_carry;`
71			`reg [1:0]state_reg;`
72
73			`///////////// Dynamic Shift /////////////`
74			`reg [4:0]shifted,shifted_1;`
75			`reg [31:0]sdata;`
76			`wire [31:0]sdata_o;`
77			`wire [4:0]shifted_o;`
78			`shifter shifter_0(`
79			`sdata,`
80			`sdata_o,`
81			`shifted_o`
82			`);`
83
84			`/*`
85			`assign a=`
86			`state==state_4?{1'b1,~final_nq}:`
87			`state==state_5?remainder_addback:`
88			`nsub?DR:nDR;`
89			`*/`
90			`assign a= ct_1_en?{27'd0,shifted_1}:`
91			`state==state_4?{1'b1,~final_nq}:`
92			`state==state_5?remainder_addback:`
93			`nsub?DR:nDR;`
94			`assign b= ct_1_en?{26'd0,ct_1}:`
95			`state==state_4?{1'b0,final_q}:`
96			`state==state_5?PR_1:PR;`
97
98			`assign carry_in= ct_1_en?0:`
99			`state==state_4?1:`
100			`state==state_5? addback_nDR?1:0:`
101			`nsub?0:1;`
102
103			`adder_32bit adder_0(`
104			`reg_a,`
105			`reg_b,`
106			`reg_carry,`
107			`sum,`
108			`carry_out`
109			`);`
110
111
112
113
114			`// ct calculation`
115			`//reg UDR; // update Divisor`
116			`wire [5:0]sum_ct;`
117			`wire [25:0]sum_ct_h;`
118			`wire carry_ct;`
119			`adder_32bit adder_1(`
120			`{26'd0,ct},`
121			`state[5]?{27'd0,shifted}:~{27'd0,shifted},`
122			`state[5]?1'b0:1'b1,`
123			`{sum_ct_h,sum_ct},`
124			`carry_ct`
125			`);`
126
127
128
129
130
131
132			`///////////////////////////////////////////`
133
134			`always@(posedge i_clk or negedge i_rst)`
135			`if(!i_rst)begin`
136			`sdata<=0;`
137			`shifted<=0;`
138			`shifted_1<=0;`
139			`PR<=0;`
140			`PR_1<=0;`
141			`DR<=0;`
142			`//UDR<=0;`
143			`ready<=0;`
144			`ct<=0;`
145			`ct_1<=0;`
146			`ct_1_en<=0;`
147			`ct_1_en_1<=0;`
148			`state<=state_1;`
149			`DD_sign<=0;`
150			`o_quotient<=0;`
151			`o_remainder<=0;`
152			`nq<=0;`
153			`q<=0;`
154			`//over_sub<=0;`
155			`reg_a<=0;`
156			`reg_b<=0;`
157			`reg_carry<=0;`
158			`state_reg<=0;`
159			`end`
160			`else begin`
161			`if(ready&&(!i_start))ready<=0;`
162			`case(state_reg)`
163			`0:`
164			`case(state)`
165			`state_1:if((!ready)&&i_start)begin`
166			`sdata<=i_divisor;`
167			`state<=state_6;`
168			`q<=0;`
169			`nq<=0;`
170			`shifted<=0;`
171			`//UDR<=1;`
172			`end`
173			`state_2:begin`
174			`sdata<=i_dividend;`
175			`PR_1<=i_dividend;`
176			`DD_sign<=i_dividend[31];`
177			`state<=state_3;`
178			`state_reg<=1;`
179			`end`
180			`state_3:begin`
181			`if(ct[5])begin`
182			`state<=state_4;`
183			`ct<=0;`
184			`state_reg<=2;`
185			`end`
186			`else begin`
187			`ct_1_en<=1;`
188			`shifted_1<=shifted;`
189			`nq[ct]<=nsub;`
190			`q[ct]<=~nsub;`
191			`sdata<=sum;`
192			`state_reg<=1;`
193			`end`
194			`end`
195			`state_4:begin`
196			`state<=state_5;`
197			`o_quotient<=sum;`
198			`PR_1<=PR_1>>>ct_1;`
199			`state_reg<=2;`
200			`end`
201			`state_5:begin`
202			`o_remainder<=sum;`
203			`ct_1<=0;`
204			`state<=state_1;`
205			`ready<=1;`
206			`end`
207
208			`state_6:begin`
209			`sdata<=sdata_o;`
210			`shifted<=shifted_o;`
211			`ct<=sum_ct;`
212			`if(sdata[31]!=sdata[30])begin`
213			`state<=state_2;`
214			`DR<=sdata;`
215			`end`
216			`end`
217			`/*`
218			`state_6:begin`
219			`//if(!over_sub)o_remainder<=sum>>>ct_1;`
220			`o_remainder<=sum;`
221			`ct_1<=0;`
222			`state<=state_1;`
223			`ready<=1;`
224			`end`
225
226			`*/`
227			`endcase`
228			`1:begin`
229			`PR<=sdata_o;`
230			`PR_1<=sdata;`
231			`/*`
232			`if(UDR)begin`
233			`UDR<=0;`
234			`ct<=shifted;`
235
236			`if(shifted==0)begin`
237			`ct<=0;`
238			`end`
239			`else begin`
240			`ct<=shifted-1;`
241			`DR<={DR[31],DR[31:1]};`
242			`end`
243
244			`end`
245			`*/`
246			`shifted<=shifted_o;`
247			`state_reg<=2;`
248			`reg_a<=a; //calculate ct_1`
249			`reg_b<=b;`
250			`reg_carry<=carry_in;`
251			`ct_1_en<=0;`
252			`ct_1_en_1<=ct_1_en;`
253			`end`
254			`2:begin`
255			`if(state==state_3)begin`
256			`ct<=sum_ct;`
257			`end`
258			`state_reg<=0;`
259			`if(ct_1_en_1)begin`
260			`ct_1<=sum[5:0];`
261			`end`
262			`ct_1_en_1<=0;`
263			`reg_a<=a; // calculate PR`
264			`reg_b<=b;`
265			`reg_carry<=carry_in;`
266			`end`
267			`endcase`
268			`end`
269
270
271
272
273			`endmodule`