OpenCores
URL https://opencores.org/ocsvn/simpcon/simpcon/trunk

Subversion Repositories simpcon

[/] [simpcon/] [trunk/] [vhdl/] [sc_fpu.vhd] - Blame information for rev 26

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 18 martin 
-- This is the SimpCon interface to the FPU
2 
--
3 
 
4 
Library IEEE;
5 
use IEEE.std_logic_1164.all;
6 
use ieee.std_logic_unsigned.all;
7 
use ieee.numeric_std.all;
8 
 
9 
entity sc_fpu is
10 
generic (ADDR_WIDTH : integer);
11 
 
12 
port (
13 
        clk_i           : in std_logic;
14 
        reset_i : in std_logic;
15 
 
16 
-- SimpCon interface
17 
 
18 
        address_i               : in std_logic_vector(ADDR_WIDTH-1 downto 0);
19 
        wr_data_i               : in std_logic_vector(31 downto 0);
20 
        rd_i, wr_i              : in std_logic;
21 
        rd_data_o               : out std_logic_vector(31 downto 0);
22 
        rdy_cnt_o               : out unsigned(1 downto 0)
23 
 
24 
);
25 
end sc_fpu;
26 
 
27 
architecture rtl of sc_fpu is
28 
 
29 
        component fpu
30 
            port (
31 
                clk_i           : in std_logic;
32 
                opa_i           : in std_logic_vector(31 downto 0);
33 
                opb_i           : in std_logic_vector(31 downto 0);
34 
                fpu_op_i                : in std_logic_vector(2 downto 0);
35 
                rmode_i                 : in std_logic_vector(1 downto 0);
36 
 
37 
                output_o        : out std_logic_vector(31 downto 0);
38 
                        ine_o                   : out std_logic;
39 
                overflow_o      : out std_logic;
40 
                underflow_o     : out std_logic;
41 
                div_zero_o      : out std_logic;
42 
                inf_o                   : out std_logic;
43 
                zero_o                  : out std_logic;
44 
                qnan_o                  : out std_logic;
45 
                snan_o                  : out std_logic;
46 
 
47 
                start_i                 : in  std_logic;
48 
                ready_o                 : out std_logic
49 
                );
50 
        end component;
51 
 
52 
        signal opa_i, opb_i : std_logic_vector(31 downto 0);
53 
        signal fpu_op_i         : std_logic_vector(2 downto 0);
54 
        signal rmode_i : std_logic_vector(1 downto 0);
55 
        signal output_o : std_logic_vector(31 downto 0);
56 
        signal start_i, ready_o : std_logic ;
57 
        --signal ine_o, overflow_o, underflow_o, div_zero_o, inf_o, zero_o, qnan_o, snan_o: std_logic;
58 
 
59 
begin
60 
 
61 
 
62 
    -- instantiate the fpu
63 
    i_fpu: fpu port map (
64 
                        clk_i => clk_i,
65 
                        opa_i => opa_i,
66 
                        opb_i => opb_i,
67 
                        fpu_op_i =>     fpu_op_i,
68 
                        rmode_i => rmode_i,
69 
                        output_o => output_o,
70 
                        ine_o => open,
71 
                        overflow_o => open,
72 
                        underflow_o => open,
73 
                div_zero_o => open,
74 
                inf_o => open,
75 
                zero_o => open,
76 
                qnan_o => open,
77 
                snan_o => open,
78 
                start_i => start_i,
79 
                ready_o => ready_o);
80 
 
81 
rmode_i <= "00"; -- default rounding mode= round-to-nearest-even
82 
 
83 
-- master reads from FPU
84 
process(clk_i, reset_i)
85 
begin
86 
 
87 
        if (reset_i='1') then
88 20 martin 
--              start_i <= '0';
89 18 martin 
        elsif rising_edge(clk_i) then
90 
 
91 20 martin 
--              if rd_i='1' then
92 
--                      -- that's our very simple address decoder
93 
--                      if address_i="0011" then
94 
--                              start_i <= '1';
95 
--                      end if;
96 
--              else
97 
--                      start_i <= '0';
98 
--              end if;
99 18 martin 
        end if;
100 
 
101 
end process;
102 
 
103 
-- set rdy_cnt
104 
process(clk_i)
105 
begin
106 
        if (reset_i='1') then
107 
                rdy_cnt_o <= "11";
108 
        elsif rising_edge(clk_i) then
109 
                if start_i='1' then
110 
                        rdy_cnt_o <= "11";
111 
                elsif ready_o = '1' then
112 
                        rdy_cnt_o <= "00";
113 
                        rd_data_o <= output_o;
114 
                end if;
115 
        end if;
116 
end process;
117 
 
118 
 
119 
-- master writes to FPU
120 
process(clk_i, reset_i)
121 
 
122 
begin
123 
 
124 
        if (reset_i='1') then
125 
                opa_i <= (others => '0');
126 
                opb_i <= (others => '0');
127 
                fpu_op_i <= (others => '0');
128 20 martin 
                start_i <= '0';
129 18 martin 
        elsif rising_edge(clk_i) then
130 20 martin 
                start_i <= '0';
131 18 martin 
 
132 
                if wr_i='1' then
133 
                        if address_i="0000" then
134 
                                        opa_i <= wr_data_i;
135 
                        elsif address_i="0001" then
136 
                                        opb_i <= wr_data_i;
137 
                        elsif address_i="0010" then
138 
                                        fpu_op_i <=wr_data_i(2 downto 0);
139 20 martin 
                                        start_i <= '1';
140 18 martin 
                        end if;
141 
                end if;
142 
 
143 
        end if;
144 
 
145 
end process;
146 
 
147 
 
148 
end rtl;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.