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[/] [simpcon/] [trunk/] [vhdl/] [sc_sram32_flash.vhd] - Blame information for rev 21

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--
--      sc_sram32_flash.vhd
--
--      SimpCon compliant external memory interface
--      for 32-bit SRAM (e.g. Cyclone board)
--
--      Connection between mem_sc and the external memory bus
--
--      memory mapping
--      
--              0x000000-x7ffff external SRAM (w mirror)        max. 512 kW (4*4 MBit)
--              0x080000-xfffff external Flash (w mirror)       max. 512 kB (4 MBit)
--              0x100000-xfffff external NAND flash
--
--      RAM: 32 bit word
--      ROM: 8 bit word (for flash programming)
--
--      todo:
--              
--
--      2005-11-22      first version
--      2005-12-02      added flash interface
--
 
Library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.jop_types.all;
use work.sc_pack.all;
 
entity sc_mem_if is
generic (ram_ws : integer; rom_ws : integer);
 
port (
 
        clk, reset      : in std_logic;
 
--
--      SimpCon memory interface
--
        sc_mem_out              : in sc_mem_out_type;
        sc_mem_in               : out sc_in_type;
 
-- memory interface
 
        ram_addr        : out std_logic_vector(17 downto 0);
        ram_dout        : out std_logic_vector(31 downto 0);
        ram_din         : in std_logic_vector(31 downto 0);
        ram_dout_en     : out std_logic;
        ram_ncs         : out std_logic;
        ram_noe         : out std_logic;
        ram_nwe         : out std_logic;
 
--
--      config/program flash and big nand flash interface
--
        fl_a    : out std_logic_vector(18 downto 0);
        fl_d    : inout std_logic_vector(7 downto 0);
        fl_ncs  : out std_logic;
        fl_ncsb : out std_logic;
        fl_noe  : out std_logic;
        fl_nwe  : out std_logic;
        fl_rdy  : in std_logic
 
);
end sc_mem_if;
 
architecture rtl of sc_mem_if is
 
--
--      signals for mem interface
--
        type state_type         is (
                                                        idl, rd1, rd2, wr1,
                                                        fl_rd1, fl_rd2, fl_wr1, fl_wr2
                                                );
        signal state            : state_type;
        signal next_state       : state_type;
 
        signal nwr_int          : std_logic;
        signal wait_state       : unsigned(3 downto 0);
        signal cnt                      : unsigned(1 downto 0);
 
        signal dout_ena         : std_logic;
        signal ram_data         : std_logic_vector(31 downto 0);
        signal ram_data_ena     : std_logic;
 
        signal flash_dout       : std_logic_vector(7 downto 0);
        signal fl_dout_ena      : std_logic;
        signal flash_data       : std_logic_vector(7 downto 0);
        signal flash_data_ena   : std_logic;
        signal nand_rdy         : std_logic;
 
        signal trans_ram        : std_logic;
        signal trans_flash      : std_logic;
        -- selection for read mux
        signal ram_access       : std_logic;
        -- selection for Flash/NAND ncs
        signal sel_flash        : std_logic;
 
begin
 
        assert MEM_ADDR_SIZE>=21 report "Too less address bits";
        ram_dout_en <= dout_ena;
 
        sc_mem_in.rdy_cnt <= cnt;
 
--
--      decode ram/flash
--      The signals are only valid for the first cycle
--
process(sc_mem_out.address(20 downto 19))
begin
 
        trans_ram <= '0';
        trans_flash <= '0';
 
        case sc_mem_out.address(20 downto 19) is
                when "00" =>
                        trans_ram <= '1';
                when "01" =>
                        trans_flash <= '1';
                when others =>
                        null;
        end case;
 
end process;
 
--
--      Register memory address, write data and read data
--
process(clk, reset)
begin
        if reset='1' then
 
                ram_addr <= (others => '0');
                ram_dout <= (others => '0');
                ram_data <= (others => '0');
                flash_dout <= (others => '0');
                fl_a <= (others => '0');
                sel_flash <= '1';                       -- AMD default
                ram_access <= '1';                      -- RAM default
 
        elsif rising_edge(clk) then
 
                if sc_mem_out.rd='1' or sc_mem_out.wr='1' then
                        if trans_ram='1' then
                                ram_access <= '1';
                                ram_addr <= sc_mem_out.address(17 downto 0);
                        else
                                ram_access <= '0';
                                fl_a <= sc_mem_out.address(18 downto 0);
                                -- select flash type
                                -- and keep it selected
                                if trans_flash='1' then
                                        sel_flash <= '1';
                                else
                                        sel_flash <= '0';
                                end if;
                        end if;
                end if;
                if sc_mem_out.wr='1' then
                        if trans_ram='1' then
                                ram_dout <= sc_mem_out.wr_data;
                        else
                                flash_dout <= sc_mem_out.wr_data(7 downto 0);
                        end if;
                end if;
                if ram_data_ena='1' then
                        ram_data <= ram_din;
                end if;
                if flash_data_ena='1' then
                        -- signal NAND rdy only for NAND access
                        nand_rdy <= fl_rdy and not sel_flash;
                        flash_data <= fl_d;
                end if;
 
        end if;
end process;
 
--
--      MUX registered RAM and Flash data
--
process(ram_access, ram_data, flash_data, nand_rdy)
 
begin
        if (ram_access='1') then
                sc_mem_in.rd_data <= ram_data;
        else
                sc_mem_in.rd_data <= std_logic_vector(to_unsigned(0, 32-9)) & nand_rdy & flash_data;
        end if;
end process;
 
--
--      'delay' nwe 1/2 cycle -> change on falling edge
--
process(clk, reset)
 
begin
        if (reset='1') then
                ram_nwe <= '1';
        elsif falling_edge(clk) then
                ram_nwe <= nwr_int;
        end if;
 
end process;
 
 
--
--      next state logic
--
process(state, sc_mem_out, trans_ram, wait_state)
 
begin
 
        next_state <= state;
 
        case state is
 
                when idl =>
                        if sc_mem_out.rd='1' then
                                if trans_ram='1' then
                                        if ram_ws=0 then
                                                -- then we omit state rd1!
                                                next_state <= rd2;
                                        else
                                                next_state <= rd1;
                                        end if;
                                else
                                        next_state <= fl_rd1;
                                end if;
                        elsif sc_mem_out.wr='1' then
                                if trans_ram='1' then
                                        next_state <= wr1;
                                else
                                        next_state <= fl_wr1;
                                end if;
                        end if;
 
                -- the WS state
                when rd1 =>
                        if wait_state=2 then
                                next_state <= rd2;
                        end if;
 
                -- last read state
                when rd2 =>
                        next_state <= idl;
                        -- This should do to give us a pipeline
                        -- level of 2 for read
                        -- we don't care about a flash trans.
                        -- in the pipeline!
                        if sc_mem_out.rd='1' then
                                if ram_ws=0 then
                                        -- then we omit state rd1!
                                        next_state <= rd2;
                                else
                                        next_state <= rd1;
                                end if;
                        elsif sc_mem_out.wr='1' then
                                next_state <= wr1;
                        end if;
 
                -- the WS state
                when wr1 =>
-- TODO: check what happens on ram_ws=0
-- TODO: do we need a write pipelining?
--      not at the moment, but parhaps later when
--      we write the stack content to main memory
                        if wait_state=1 then
                                next_state <= idl;
                        end if;
 
                when fl_rd1 =>
                        if wait_state=2 then
                                next_state <= fl_rd2;
                        end if;
 
                when fl_rd2 =>
                        next_state <= idl;
                        -- we do no pipelining with the Flashs
 
                when fl_wr1 =>
                        if wait_state=2 then
                                next_state <= fl_wr2;
                        end if;
 
                when fl_wr2 =>
                        next_state <= idl;
 
        end case;
 
end process;
 
--
--      state machine register
--      output register (RAM, Flash control lines)
--
process(clk, reset)
 
begin
        if (reset='1') then
                state <= idl;
                dout_ena <= '0';
                ram_ncs <= '1';
                ram_noe <= '1';
                ram_data_ena <= '0';
 
                fl_noe <= '1';
                fl_nwe <= '1';
                flash_data_ena <= '0';
                fl_dout_ena <= '0';
 
        elsif rising_edge(clk) then
 
                state <= next_state;
                dout_ena <= '0';
                ram_ncs <= '1';
                ram_noe <= '1';
                ram_data_ena <= '0';
 
                fl_noe <= '1';
                fl_nwe <= '1';
                flash_data_ena <= '0';
                fl_dout_ena <= '0';
 
                case next_state is
 
                        when idl =>
 
                        -- the wait state
                        when rd1 =>
                                ram_ncs <= '0';
                                ram_noe <= '0';
 
                        -- last read state
                        when rd2 =>
                                ram_ncs <= '0';
                                ram_noe <= '0';
                                ram_data_ena <= '1';
 
 
                        -- the WS state
                        when wr1 =>
                                ram_ncs <= '0';
                                dout_ena <= '1';
 
                        when fl_rd1 =>
                                fl_noe <= '0';
 
                        when fl_rd2 =>
                                fl_noe <= '0';
                                flash_data_ena <= '1';
 
                        when fl_wr1 =>
                                fl_nwe <= '0';
                                fl_dout_ena <= '1';
 
                        when fl_wr2 =>
                                fl_dout_ena <= '1';
 
                end case;
 
        end if;
end process;
 
--
--      nwr combinatorial processing
--      for the negativ edge
--
process(next_state, state)
begin
 
        nwr_int <= '1';
        if next_state=wr1 then
                nwr_int <= '0';
        end if;
 
end process;
 
--
-- wait_state processing
-- cs delay, dout enable
--
process(clk, reset)
begin
        if (reset='1') then
                wait_state <= (others => '1');
                cnt <= "00";
        elsif rising_edge(clk) then
 
                wait_state <= wait_state-1;
 
                cnt <= "11";
                if next_state=idl then
                        cnt <= "00";
                -- if wait_state<4 then
                elsif wait_state(3 downto 2)="00" then
                        cnt <= wait_state(1 downto 0)-1;
                end if;
 
                if sc_mem_out.rd='1' or sc_mem_out.wr='1' then
                        if trans_ram='1' then
                                wait_state <= to_unsigned(ram_ws+1, 4);
                                if ram_ws<3 then
                                        cnt <= to_unsigned(ram_ws+1, 2);
                                else
                                        cnt <= "11";
                                end if;
                        else
                                wait_state <= to_unsigned(rom_ws+1, 4);
                                cnt <= "11";
                        end if;
                end if;
 
        end if;
end process;
 
--
--      Flash signals
--
 
--
--      leave last ncs. Only toggle between two flashs.
--
        fl_ncs <= not sel_flash;        -- Flash ncs
        fl_ncsb <= sel_flash;           -- NAND ncs
 
--
--      tristate output
--
process(fl_dout_ena, flash_dout)
 
begin
        if (fl_dout_ena='1') then
                fl_d <= flash_dout(7 downto 0);
        else
                fl_d <= (others => 'Z');
        end if;
end process;
 
end rtl;

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[/] [simpcon/] [trunk/] [vhdl/] [sc_sram32_flash.vhd] - Blame information for rev 21

Line No.	Rev	Author	Line
1	18	martin	`--`
2			`-- sc_sram32_flash.vhd`
3			`--`
4			`-- SimpCon compliant external memory interface`
5			`-- for 32-bit SRAM (e.g. Cyclone board)`
6			`--`
7			`-- Connection between mem_sc and the external memory bus`
8			`--`
9			`-- memory mapping`
10			`--`
11			`-- 0x000000-x7ffff external SRAM (w mirror) max. 512 kW (4*4 MBit)`
12			`-- 0x080000-xfffff external Flash (w mirror) max. 512 kB (4 MBit)`
13			`-- 0x100000-xfffff external NAND flash`
14			`--`
15			`-- RAM: 32 bit word`
16			`-- ROM: 8 bit word (for flash programming)`
17			`--`
18			`-- todo:`
19			`--`
20			`--`
21			`-- 2005-11-22 first version`
22			`-- 2005-12-02 added flash interface`
23			`--`
24
25			`Library IEEE;`
26			`use IEEE.std_logic_1164.all;`
27			`use ieee.numeric_std.all;`
28
29			`use work.jop_types.all;`
30			`use work.sc_pack.all;`
31
32			`entity sc_mem_if is`
33			`generic (ram_ws : integer; rom_ws : integer);`
34
35			`port (`
36
37			`clk, reset : in std_logic;`
38
39			`--`
40			`-- SimpCon memory interface`
41			`--`
42			`sc_mem_out : in sc_mem_out_type;`
43			`sc_mem_in : out sc_in_type;`
44
45			`-- memory interface`
46
47			`ram_addr : out std_logic_vector(17 downto 0);`
48			`ram_dout : out std_logic_vector(31 downto 0);`
49			`ram_din : in std_logic_vector(31 downto 0);`
50			`ram_dout_en : out std_logic;`
51			`ram_ncs : out std_logic;`
52			`ram_noe : out std_logic;`
53			`ram_nwe : out std_logic;`
54
55			`--`
56			`-- config/program flash and big nand flash interface`
57			`--`
58			`fl_a : out std_logic_vector(18 downto 0);`
59			`fl_d : inout std_logic_vector(7 downto 0);`
60			`fl_ncs : out std_logic;`
61			`fl_ncsb : out std_logic;`
62			`fl_noe : out std_logic;`
63			`fl_nwe : out std_logic;`
64			`fl_rdy : in std_logic`
65
66			`);`
67			`end sc_mem_if;`
68
69			`architecture rtl of sc_mem_if is`
70
71			`--`
72			`-- signals for mem interface`
73			`--`
74			`type state_type is (`
75			`idl, rd1, rd2, wr1,`
76			`fl_rd1, fl_rd2, fl_wr1, fl_wr2`
77			`);`
78			`signal state : state_type;`
79			`signal next_state : state_type;`
80
81			`signal nwr_int : std_logic;`
82			`signal wait_state : unsigned(3 downto 0);`
83			`signal cnt : unsigned(1 downto 0);`
84
85			`signal dout_ena : std_logic;`
86			`signal ram_data : std_logic_vector(31 downto 0);`
87			`signal ram_data_ena : std_logic;`
88
89			`signal flash_dout : std_logic_vector(7 downto 0);`
90			`signal fl_dout_ena : std_logic;`
91			`signal flash_data : std_logic_vector(7 downto 0);`
92			`signal flash_data_ena : std_logic;`
93			`signal nand_rdy : std_logic;`
94
95			`signal trans_ram : std_logic;`
96			`signal trans_flash : std_logic;`
97			`-- selection for read mux`
98			`signal ram_access : std_logic;`
99			`-- selection for Flash/NAND ncs`
100			`signal sel_flash : std_logic;`
101
102			`begin`
103
104			`assert MEM_ADDR_SIZE>=21 report "Too less address bits";`
105			`ram_dout_en <= dout_ena;`
106
107			`sc_mem_in.rdy_cnt <= cnt;`
108
109			`--`
110			`-- decode ram/flash`
111			`-- The signals are only valid for the first cycle`
112			`--`
113			`process(sc_mem_out.address(20 downto 19))`
114			`begin`
115
116			`trans_ram <= '0';`
117			`trans_flash <= '0';`
118
119			`case sc_mem_out.address(20 downto 19) is`
120			`when "00" =>`
121			`trans_ram <= '1';`
122			`when "01" =>`
123			`trans_flash <= '1';`
124			`when others =>`
125			`null;`
126			`end case;`
127
128			`end process;`
129
130			`--`
131			`-- Register memory address, write data and read data`
132			`--`
133			`process(clk, reset)`
134			`begin`
135			`if reset='1' then`
136
137			`ram_addr <= (others => '0');`
138			`ram_dout <= (others => '0');`
139			`ram_data <= (others => '0');`
140			`flash_dout <= (others => '0');`
141			`fl_a <= (others => '0');`
142			`sel_flash <= '1'; -- AMD default`
143			`ram_access <= '1'; -- RAM default`
144
145			`elsif rising_edge(clk) then`
146
147			`if sc_mem_out.rd='1' or sc_mem_out.wr='1' then`
148			`if trans_ram='1' then`
149			`ram_access <= '1';`
150			`ram_addr <= sc_mem_out.address(17 downto 0);`
151			`else`
152			`ram_access <= '0';`
153			`fl_a <= sc_mem_out.address(18 downto 0);`
154			`-- select flash type`
155			`-- and keep it selected`
156			`if trans_flash='1' then`
157			`sel_flash <= '1';`
158			`else`
159			`sel_flash <= '0';`
160			`end if;`
161			`end if;`
162			`end if;`
163			`if sc_mem_out.wr='1' then`
164			`if trans_ram='1' then`
165			`ram_dout <= sc_mem_out.wr_data;`
166			`else`
167			`flash_dout <= sc_mem_out.wr_data(7 downto 0);`
168			`end if;`
169			`end if;`
170			`if ram_data_ena='1' then`
171			`ram_data <= ram_din;`
172			`end if;`
173			`if flash_data_ena='1' then`
174			`-- signal NAND rdy only for NAND access`
175			`nand_rdy <= fl_rdy and not sel_flash;`
176			`flash_data <= fl_d;`
177			`end if;`
178
179			`end if;`
180			`end process;`
181
182			`--`
183			`-- MUX registered RAM and Flash data`
184			`--`
185			`process(ram_access, ram_data, flash_data, nand_rdy)`
186
187			`begin`
188			`if (ram_access='1') then`
189			`sc_mem_in.rd_data <= ram_data;`
190			`else`
191			`sc_mem_in.rd_data <= std_logic_vector(to_unsigned(0, 32-9)) & nand_rdy & flash_data;`
192			`end if;`
193			`end process;`
194
195			`--`
196			`-- 'delay' nwe 1/2 cycle -> change on falling edge`
197			`--`
198			`process(clk, reset)`
199
200			`begin`
201			`if (reset='1') then`
202			`ram_nwe <= '1';`
203			`elsif falling_edge(clk) then`
204			`ram_nwe <= nwr_int;`
205			`end if;`
206
207			`end process;`
208
209
210			`--`
211			`-- next state logic`
212			`--`
213	21	martin	`process(state, sc_mem_out, trans_ram, wait_state)`
214	18	martin
215			`begin`
216
217			`next_state <= state;`
218
219			`case state is`
220
221			`when idl =>`
222			`if sc_mem_out.rd='1' then`
223			`if trans_ram='1' then`
224			`if ram_ws=0 then`
225			`-- then we omit state rd1!`
226			`next_state <= rd2;`
227			`else`
228			`next_state <= rd1;`
229			`end if;`
230			`else`
231			`next_state <= fl_rd1;`
232			`end if;`
233			`elsif sc_mem_out.wr='1' then`
234			`if trans_ram='1' then`
235			`next_state <= wr1;`
236			`else`
237			`next_state <= fl_wr1;`
238			`end if;`
239			`end if;`
240
241			`-- the WS state`
242			`when rd1 =>`
243			`if wait_state=2 then`
244			`next_state <= rd2;`
245			`end if;`
246
247			`-- last read state`
248			`when rd2 =>`
249			`next_state <= idl;`
250			`-- This should do to give us a pipeline`
251			`-- level of 2 for read`
252			`-- we don't care about a flash trans.`
253			`-- in the pipeline!`
254			`if sc_mem_out.rd='1' then`
255			`if ram_ws=0 then`
256			`-- then we omit state rd1!`
257			`next_state <= rd2;`
258			`else`
259			`next_state <= rd1;`
260			`end if;`
261			`elsif sc_mem_out.wr='1' then`
262			`next_state <= wr1;`
263			`end if;`
264
265			`-- the WS state`
266			`when wr1 =>`
267			`-- TODO: check what happens on ram_ws=0`
268			`-- TODO: do we need a write pipelining?`
269			`-- not at the moment, but parhaps later when`
270			`-- we write the stack content to main memory`
271			`if wait_state=1 then`
272			`next_state <= idl;`
273			`end if;`
274
275			`when fl_rd1 =>`
276			`if wait_state=2 then`
277			`next_state <= fl_rd2;`
278			`end if;`
279
280			`when fl_rd2 =>`
281			`next_state <= idl;`
282			`-- we do no pipelining with the Flashs`
283
284			`when fl_wr1 =>`
285			`if wait_state=2 then`
286			`next_state <= fl_wr2;`
287			`end if;`
288
289			`when fl_wr2 =>`
290			`next_state <= idl;`
291
292			`end case;`
293
294			`end process;`
295
296			`--`
297			`-- state machine register`
298			`-- output register (RAM, Flash control lines)`
299			`--`
300			`process(clk, reset)`
301
302			`begin`
303			`if (reset='1') then`
304			`state <= idl;`
305			`dout_ena <= '0';`
306			`ram_ncs <= '1';`
307			`ram_noe <= '1';`
308			`ram_data_ena <= '0';`
309
310			`fl_noe <= '1';`
311			`fl_nwe <= '1';`
312			`flash_data_ena <= '0';`
313			`fl_dout_ena <= '0';`
314
315			`elsif rising_edge(clk) then`
316
317			`state <= next_state;`
318			`dout_ena <= '0';`
319			`ram_ncs <= '1';`
320			`ram_noe <= '1';`
321			`ram_data_ena <= '0';`
322
323			`fl_noe <= '1';`
324			`fl_nwe <= '1';`
325			`flash_data_ena <= '0';`
326			`fl_dout_ena <= '0';`
327
328			`case next_state is`
329
330			`when idl =>`
331
332			`-- the wait state`
333			`when rd1 =>`
334			`ram_ncs <= '0';`
335			`ram_noe <= '0';`
336
337			`-- last read state`
338			`when rd2 =>`
339			`ram_ncs <= '0';`
340			`ram_noe <= '0';`
341			`ram_data_ena <= '1';`
342
343
344			`-- the WS state`
345			`when wr1 =>`
346			`ram_ncs <= '0';`
347			`dout_ena <= '1';`
348
349			`when fl_rd1 =>`
350			`fl_noe <= '0';`
351
352			`when fl_rd2 =>`
353			`fl_noe <= '0';`
354			`flash_data_ena <= '1';`
355
356			`when fl_wr1 =>`
357			`fl_nwe <= '0';`
358			`fl_dout_ena <= '1';`
359
360			`when fl_wr2 =>`
361			`fl_dout_ena <= '1';`
362
363			`end case;`
364
365			`end if;`
366			`end process;`
367
368			`--`
369			`-- nwr combinatorial processing`
370			`-- for the negativ edge`
371			`--`
372			`process(next_state, state)`
373			`begin`
374
375			`nwr_int <= '1';`
376			`if next_state=wr1 then`
377			`nwr_int <= '0';`
378			`end if;`
379
380			`end process;`
381
382			`--`
383			`-- wait_state processing`
384			`-- cs delay, dout enable`
385			`--`
386			`process(clk, reset)`
387			`begin`
388			`if (reset='1') then`
389			`wait_state <= (others => '1');`
390			`cnt <= "00";`
391			`elsif rising_edge(clk) then`
392
393			`wait_state <= wait_state-1;`
394
395			`cnt <= "11";`
396			`if next_state=idl then`
397			`cnt <= "00";`
398			`-- if wait_state<4 then`
399			`elsif wait_state(3 downto 2)="00" then`
400			`cnt <= wait_state(1 downto 0)-1;`
401			`end if;`
402
403			`if sc_mem_out.rd='1' or sc_mem_out.wr='1' then`
404			`if trans_ram='1' then`
405			`wait_state <= to_unsigned(ram_ws+1, 4);`
406			`if ram_ws<3 then`
407			`cnt <= to_unsigned(ram_ws+1, 2);`
408			`else`
409			`cnt <= "11";`
410			`end if;`
411			`else`
412			`wait_state <= to_unsigned(rom_ws+1, 4);`
413			`cnt <= "11";`
414			`end if;`
415			`end if;`
416
417			`end if;`
418			`end process;`
419
420			`--`
421			`-- Flash signals`
422			`--`
423
424			`--`
425			`-- leave last ncs. Only toggle between two flashs.`
426			`--`
427			`fl_ncs <= not sel_flash; -- Flash ncs`
428			`fl_ncsb <= sel_flash; -- NAND ncs`
429
430			`--`
431			`-- tristate output`
432			`--`
433			`process(fl_dout_ena, flash_dout)`
434
435			`begin`
436			`if (fl_dout_ena='1') then`
437			`fl_d <= flash_dout(7 downto 0);`
438			`else`
439			`fl_d <= (others => 'Z');`
440			`end if;`
441			`end process;`
442
443			`end rtl;`