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--

--      scio_min.vhd

--

--      io devices for minimal configuration

--      only counter, wd and serial line, alle io pins are tri statet

--

--

--      io address mapping:

--

--      IO Base is 0xffffff80 for 'fast' constants (bipush)

--

--              0x00 0-3                system clock counter, us counter, timer int, wd bit

--              0x10 0-1                uart (download)

--

--      status word in uarts:

--              0        uart transmit data register empty

--              1       uart read data register full

--

--

--      todo:

--

--

--      2003-07-09      created

--      2005-08-27      ignore ncts on uart

--      2005-11-30      changed to SimpCon

--      2007-03-17      use records

--

--

Library IEEE;

use IEEE.std_logic_1164.all;

use ieee.numeric_std.all;

use work.jop_types.all;

use work.sc_pack.all;

use work.jop_config.all;

entity scio is

generic (cpu_id : integer := 0);

port (

        clk             : in std_logic;

        reset   : in std_logic;

--

--      SimpCon IO interface

--

        sc_io_out               : in sc_io_out_type;

        sc_io_in                : out sc_in_type;

--

--      Interrupts from IO devices

--

        irq_in                  : out irq_in_type;

        exc_req                 : in exception_type;

-- CMP

        sync_out : in sync_out_type := NO_SYNC;

        sync_in  : out sync_in_type;

-- serial interface

        txd                     : out std_logic;

        rxd                     : in std_logic;

        ncts            : in std_logic;

        nrts            : out std_logic;

-- watch dog

        wd                      : out std_logic;

-- core i/o pins

        l                       : inout std_logic_vector(20 downto 1);

        r                       : inout std_logic_vector(20 downto 1);

        t                       : inout std_logic_vector(6 downto 1);

        b                       : inout std_logic_vector(10 downto 1)

);

end scio;

architecture rtl of scio is

        constant SLAVE_CNT : integer := 3;

        -- SLAVE_CNT <= 2**DECODE_BITS

        -- take care of USB address 0x20!

        constant DECODE_BITS : integer := 2;

        -- number of bits that can be used inside the slave

        constant SLAVE_ADDR_BITS : integer := 4;

        type slave_bit is array(0 to SLAVE_CNT-1) of std_logic;

        signal sc_rd, sc_wr             : slave_bit;

        type slave_dout is array(0 to SLAVE_CNT-1) of std_logic_vector(31 downto 0);

        signal sc_dout                  : slave_dout;

        type slave_rdy_cnt is array(0 to SLAVE_CNT-1) of unsigned(1 downto 0);

        signal sc_rdy_cnt               : slave_rdy_cnt;

        signal sel, sel_reg             : integer range 0 to 2**DECODE_BITS-1;

begin

--

--      unused and input pins tri state

--

        l <= (others => 'Z');

        r <= (others => 'Z');

        t <= (others => 'Z');

        b <= (others => 'Z');

        assert SLAVE_CNT <= 2**DECODE_BITS report "Wrong constant in scio";

        sel <= to_integer(unsigned(sc_io_out.address(SLAVE_ADDR_BITS+DECODE_BITS-1 downto SLAVE_ADDR_BITS)));

        -- What happens when sel_reg > SLAVE_CNT-1??

        sc_io_in.rd_data <= sc_dout(sel_reg);

        sc_io_in.rdy_cnt <= sc_rdy_cnt(sel_reg);

        -- default for unused USB device

        sc_dout(2) <= (others => '0');

        sc_rdy_cnt(2) <= (others => '0');

        --

        -- Connect SLAVE_CNT simple test slaves

        --

        gsl: for i in 0 to SLAVE_CNT-1 generate

                sc_rd(i) <= sc_io_out.rd when i=sel else '0';

                sc_wr(i) <= sc_io_out.wr when i=sel else '0';

        end generate;

        --

        --      Register read mux selector

        --

        process(clk, reset)

        begin

                if (reset='1') then

                        sel_reg <= 0;

                elsif rising_edge(clk) then

                        if sc_io_out.rd='1' then

                                sel_reg <= sel;

                        end if;

                end if;

        end process;

        cmp_sys: entity work.sc_sys generic map (

                        addr_bits => SLAVE_ADDR_BITS,

                        clk_freq => clk_freq,

                        cpu_id => cpu_id

                )

                port map(

                        clk => clk,

                        reset => reset,

                        address => sc_io_out.address(SLAVE_ADDR_BITS-1 downto 0),

                        wr_data => sc_io_out.wr_data,

                        rd => sc_rd(0),

                        wr => sc_wr(0),

                        rd_data => sc_dout(0),

                        rdy_cnt => sc_rdy_cnt(0),

                        irq_in => irq_in,

                        exc_req => exc_req,

                        sync_out => sync_out,

                        sync_in => sync_in,

                        wd => wd

                );

        cmp_ua: entity work.sc_uart generic map (

                        addr_bits => SLAVE_ADDR_BITS,

                        clk_freq => clk_freq,

                        baud_rate => 115200,

                        txf_depth => 2,

                        txf_thres => 1,

                        rxf_depth => 2,

                        rxf_thres => 1

                )

                port map(

                        clk => clk,

                        reset => reset,

                        address => sc_io_out.address(SLAVE_ADDR_BITS-1 downto 0),

                        wr_data => sc_io_out.wr_data,

                        rd => sc_rd(1),

                        wr => sc_wr(1),

                        rd_data => sc_dout(1),

                        rdy_cnt => sc_rdy_cnt(1),

                        txd      => txd,

                        rxd      => rxd,

                        ncts => '0',

                        nrts => nrts

        );

end rtl;