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https://opencores.org/ocsvn/simple_fm_receiver/simple_fm_receiver/trunk
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arif_endro |
$Id: README,v 1.1.1.1 2005-01-04 02:05:54 arif_endro Exp $
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Do not edit files in directory export directly
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but changes in source directory then use ALLIANCE tools
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to analyze and sintesis them.
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there is three test bench the first (e.g modelsim-bench) is for quick test
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e.g just hit run -all then this will test in one loop
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other can be used for modifying clock signal and
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applying reset signal to fm.
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directory layout:
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source => contain source code development (primary source)
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export => contain VHDL and VERILOG exportable code that can
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be used on many synthesize tools.
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docs => contains documents for reports
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bench => the test bench clock and reset can be modified
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bench_xil => test bench for Xilinx, this because Xilinx uses
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std_logic for signal in synthesized component.
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modelsim-bench => quick test bench the clock and reset signal is
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supplied by testbench (the old one).
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NOTES: the report is better displayed on postscript than pdf format
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this is may be because the dvipdf driver not produces good pdf file.
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if you have ghostview or any postscript viewer see the postscript
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file to get the best view.
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