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[/] [simple_fm_receiver/] [tags/] [VSFR_1/] [source/] [adder_10bit.vhdl] - Blame information for rev 32

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1 2 arif_endro 
-- $Id: adder_10bit.vhdl,v 1.1.1.1 2005-01-04 02:05:58 arif_endro Exp $
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-------------------------------------------------------------------------------
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-- Title       : Adder 10 bit
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-- Project     : FM Receiver
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-------------------------------------------------------------------------------
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-- File        : adder_10bit.vhdl
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-- Author      : "Arif E. Nugroho" <arif_endro@yahoo.com>
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-- Created     : 2004/12/23
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-- Last update :
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-- Simulators  : Modelsim 6.0
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-- Synthesizers:
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-- Target      :
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-------------------------------------------------------------------------------
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-- Description : Ripple carry adder 10 bit with output 11 bit
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-------------------------------------------------------------------------------
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-- Copyright (c) 2004 Arif E. Nugroho
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-- This VHDL design file is an open design; you can redistribute it and/or
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-- modify it and/or implement it after contacting the author
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_arith.ALL;
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entity adder_10bit is
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   port (
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      addend_10bit  : in  bit_vector (09 downto 0);
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      augend_10bit  : in  bit_vector (09 downto 0);
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      adder10_output: out bit_vector (10 downto 0)
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      );
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end adder_10bit;
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architecture structural of adder_10bit is
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   component fulladder
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      port (
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      addend        : in   bit;
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      augend        : in   bit;
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      carry_in      : in   bit;
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      sum           : out  bit;
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      carry         : out  bit
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      );
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   end component;
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signal c00 : bit;
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signal c01 : bit;
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signal c02 : bit;
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signal c03 : bit;
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signal c04 : bit;
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signal c05 : bit;
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signal c06 : bit;
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signal c07 : bit;
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signal c08 : bit;
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signal c09 : bit;
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signal c10 : bit;
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signal over10 : bit;
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signal adder10_output_int : bit_vector (10 downto 0);
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begin
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c00                     <= '0';
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over10                  <= (addend_10bit (09) xor augend_10bit (09));
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adder10_output_int (10) <= ((adder10_output_int (09) and over10) or
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                           (c10 and (not (over10))));
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adder10_output          <= adder10_output_int;
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fa09 : fulladder
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   port map (
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      addend     => addend_10bit(09),
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      augend     => augend_10bit(09),
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      carry_in   => c09,
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      sum        => adder10_output_int(09),
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      carry      => c10
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      );
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fa08 : fulladder
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   port map (
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      addend     => addend_10bit(08),
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      augend     => augend_10bit(08),
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      carry_in   => c08,
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      sum        => adder10_output_int(08),
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      carry      => c09
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      );
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fa07 : fulladder
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   port map (
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      addend     => addend_10bit(07),
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      augend     => augend_10bit(07),
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      carry_in   => c07,
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      sum        => adder10_output_int(07),
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      carry      => c08
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      );
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fa06 : fulladder
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   port map (
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      addend     => addend_10bit(06),
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      augend     => augend_10bit(06),
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      carry_in   => c06,
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      sum        => adder10_output_int(06),
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      carry      => c07
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      );
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fa05 : fulladder
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   port map (
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      addend     => addend_10bit(05),
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      augend     => augend_10bit(05),
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      carry_in   => c05,
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      sum        => adder10_output_int(05),
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      carry      => c06
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      );
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fa04 : fulladder
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   port map (
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      addend     => addend_10bit(04),
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      augend     => augend_10bit(04),
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      carry_in   => c04,
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      sum        => adder10_output_int(04),
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      carry      => c05
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      );
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fa03 : fulladder
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   port map (
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      addend     => addend_10bit(03),
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      augend     => augend_10bit(03),
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      carry_in   => c03,
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      sum        => adder10_output_int(03),
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      carry      => c04
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      );
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fa02 : fulladder
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   port map (
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      addend     => addend_10bit(02),
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      augend     => augend_10bit(02),
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      carry_in   => c02,
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      sum        => adder10_output_int(02),
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      carry      => c03
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      );
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fa01 : fulladder
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   port map (
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      addend     => addend_10bit(01),
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      augend     => augend_10bit(01),
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      carry_in   => c01,
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      sum        => adder10_output_int(01),
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      carry      => c02
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      );
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fa00 : fulladder
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   port map (
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      addend     => addend_10bit(00),
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      augend     => augend_10bit(00),
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      carry_in   => c00,
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      sum        => adder10_output_int(00),
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      carry      => c01
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      );
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end structural;

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