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arif_endro |
-- $Id: loop_filter.vhdl,v 1.1.1.1 2005-01-04 02:05:58 arif_endro Exp $
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-------------------------------------------------------------------------------
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-- Title : Loop filter component
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-- Project : FM Receiver
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-------------------------------------------------------------------------------
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-- File : loop_filter.vhdl
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-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
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-- Created : 2004/11/12
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-- Last update :
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-- Simulators : Modelsim 6.0
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-- Synthesizers:
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-- Target :
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-------------------------------------------------------------------------------
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-- Description : loop filter in PLL loop
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-------------------------------------------------------------------------------
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-- Copyright (c) 2004 Arif E. Nugroho
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-- This VHDL design file is an open design; you can redistribute it and/or
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-- modify it and/or implement it after contacting the author
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_arith.ALL;
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entity loop_filter is
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port (
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input_loop : in bit_vector (07 downto 0);
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clock : in bit;
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output_loop : out bit_vector (11 downto 0);
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clear : in bit
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);
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end loop_filter;
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architecture structural of loop_filter is
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component adder_12bit
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port (
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addend_12bit : in bit_vector (11 downto 0);
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augend_12bit : in bit_vector (11 downto 0);
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adder12_output : out bit_vector (12 downto 0)
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);
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end component;
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component sub_12bit
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port (
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addend_12bit : in bit_vector (11 downto 0);
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subtrahend_12bit : in bit_vector (11 downto 0);
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subtractor12_output : out bit_vector (11 downto 0)
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);
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end component;
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signal input_recv : bit_vector (11 downto 0);
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signal loop_out : bit_vector (11 downto 0);
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signal loop_out_div : bit_vector (11 downto 0);
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signal loop_out_back1 : bit_vector (11 downto 0);
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signal multiply_output01 : bit_vector (11 downto 0);
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signal adder_output01 : bit_vector (12 downto 0);
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signal adder_output01_reg: bit_vector (12 downto 0);
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begin
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input_recv (11) <= input_loop (07); -- 1
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input_recv (10) <= input_loop (07); -- 1/2
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input_recv (09) <= input_loop (07); -- 1/4
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input_recv (08) <= input_loop (07); -- 1/8
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input_recv (07) <= input_loop (07); -- 1/16
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input_recv (06) <= input_loop (06);
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input_recv (05) <= input_loop (05);
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input_recv (04) <= input_loop (04);
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input_recv (03) <= input_loop (03);
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input_recv (02) <= input_loop (02);
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input_recv (01) <= input_loop (01);
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input_recv (00) <= input_loop (00);
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adder01 : adder_12bit
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port map (
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addend_12bit => loop_out_div,
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augend_12bit => input_recv,
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adder12_output => adder_output01
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);
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loop_out_back1(11) <= loop_out(11); -- 1
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loop_out_back1(10) <= loop_out(11); -- 1/2
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loop_out_back1(09) <= loop_out(11); -- 1/4
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loop_out_back1(08) <= loop_out(11); -- 1/8
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loop_out_back1(07) <= loop_out(11); -- 1/16
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loop_out_back1(06) <= loop_out(10);
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loop_out_back1(05) <= loop_out(09);
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loop_out_back1(04) <= loop_out(08);
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loop_out_back1(03) <= loop_out(07);
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loop_out_back1(02) <= loop_out(06);
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loop_out_back1(01) <= loop_out(05);
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loop_out_back1(00) <= loop_out(04);
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multiply01 : sub_12bit
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port map (
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addend_12bit => loop_out,
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subtrahend_12bit => loop_out_back1,
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subtractor12_output => multiply_output01
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);
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loop_out_div <= multiply_output01;
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adder_output01_reg (11) <= (adder_output01 (11) and not(clear));
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adder_output01_reg (10) <= (adder_output01 (10) and not(clear));
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adder_output01_reg (09) <= (adder_output01 (09) and not(clear));
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adder_output01_reg (08) <= (adder_output01 (08) and not(clear));
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adder_output01_reg (07) <= (adder_output01 (07) and not(clear));
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adder_output01_reg (06) <= (adder_output01 (06) and not(clear));
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adder_output01_reg (05) <= (adder_output01 (05) and not(clear));
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adder_output01_reg (04) <= (adder_output01 (04) and not(clear));
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adder_output01_reg (03) <= (adder_output01 (03) and not(clear));
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adder_output01_reg (02) <= (adder_output01 (02) and not(clear));
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adder_output01_reg (01) <= (adder_output01 (01) and not(clear));
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adder_output01_reg (00) <= (adder_output01 (00) and not(clear));
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process (clock)
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begin
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--if (((clock = '1') and (not (clear = '1'))) and clock'event) then
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if ((clock = '1') and clock'event) then
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-- loop_out (11) <= adder_output01_reg (12);
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loop_out (11) <= adder_output01_reg (11);
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loop_out (10) <= adder_output01_reg (10);
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loop_out (09) <= adder_output01_reg (09);
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loop_out (08) <= adder_output01_reg (08);
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loop_out (07) <= adder_output01_reg (07);
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loop_out (06) <= adder_output01_reg (06);
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loop_out (05) <= adder_output01_reg (05);
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loop_out (04) <= adder_output01_reg (04);
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loop_out (03) <= adder_output01_reg (03);
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loop_out (02) <= adder_output01_reg (02);
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loop_out (01) <= adder_output01_reg (01);
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loop_out (00) <= adder_output01_reg (00);
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-- end if;
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-- elsif (clear = '1') then -- can't be synhesized in Xilinx
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-- loop_out <= (others => '0');
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end if;
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end process;
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output_loop <= loop_out;
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end structural;
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