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-- $Id: mult_8bit.vhdl,v 1.1.1.1 2005-01-04 02:05:58 arif_endro Exp $
-------------------------------------------------------------------------------
-- Title       : Eight bit multiplier
-- Project     : FM Receiver 
-------------------------------------------------------------------------------
-- File        : mult_8bit.vhdl
-- Author      : "Arif E. Nugroho" <arif_endro@yahoo.com>
-- Created     : 2004/12/20
-- Last update : 
-- Simulators  : Modelsim 6.0
-- Synthesizers: 
-- Target      : 
-------------------------------------------------------------------------------
-- Description : Multiplier used in phase detector
-------------------------------------------------------------------------------
-- Copyright (c) 2004 Arif E. Nugroho
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
 
entity mult_8bit is
   port (
   mult_01     : in  bit_vector (07 downto 0);
   mult_02     : in  bit_vector (07 downto 0);
   result_mult : out bit_vector (15 downto 0)
   );
end mult_8bit;
 
architecture structural of mult_8bit is
   component adder_16bit
     port (
     addend_16bit   : in  bit_vector (15 downto 0);
     augend_16bit   : in  bit_vector (15 downto 0);
     adder16_output : out bit_vector (16 downto 0)
     );
   end component;
 
   component adder_16bit_u
     port (
     addend_16bit   : in  bit_vector (15 downto 0);
     augend_16bit   : in  bit_vector (15 downto 0);
     adder16_output : out bit_vector (15 downto 0)
     );
   end component;
 
   component adder_15bit
     port (
     addend_15bit   : in  bit_vector (14 downto 0);
     augend_15bit   : in  bit_vector (14 downto 0);
     adder15_output : out bit_vector (15 downto 0)
     );
   end component;
 
   component adder_14bit
     port (
     addend_14bit   : in  bit_vector (13 downto 0);
     augend_14bit   : in  bit_vector (13 downto 0);
     adder14_output : out bit_vector (14 downto 0)
     );
   end component;
 
   component adder_13bit
     port (
     addend_13bit   : in  bit_vector (12 downto 0);
     augend_13bit   : in  bit_vector (12 downto 0);
     adder13_output : out bit_vector (13 downto 0)
     );
   end component;
 
   component adder_12bit
     port (
     addend_12bit   : in  bit_vector (11 downto 0);
     augend_12bit   : in  bit_vector (11 downto 0);
     adder12_output : out bit_vector (12 downto 0)
     );
   end component;
 
   component adder_11bit
     port (
     addend_11bit   : in  bit_vector (10 downto 0);
     augend_11bit   : in  bit_vector (10 downto 0);
     adder11_output : out bit_vector (11 downto 0)
     );
   end component;
 
   component adder_10bit
     port (
     addend_10bit   : in  bit_vector (09 downto 0);
     augend_10bit   : in  bit_vector (09 downto 0);
     adder10_output : out bit_vector (10 downto 0)
     );
   end component;
 
   component adder_09bit
     port (
     addend_09bit   : in  bit_vector (08 downto 0);
     augend_09bit   : in  bit_vector (08 downto 0);
     adder09_output : out bit_vector (09 downto 0)
     );
   end component;
 
   signal input_phase    : bit_vector (07 downto 0);
   signal signal_nco     : bit_vector (07 downto 0);
 
   signal sum_part01     : bit_vector (08 downto 0);
   signal sum_part01_z   : bit_vector (08 downto 0);
   signal sum_part02     : bit_vector (09 downto 0);
   signal sum_part03     : bit_vector (10 downto 0);
   signal sum_part04     : bit_vector (11 downto 0);
   signal sum_part05     : bit_vector (12 downto 0);
   signal sum_part06     : bit_vector (13 downto 0);
   signal sum_part07     : bit_vector (14 downto 0);
   signal sum_part08_t   : bit_vector (15 downto 0);
   signal sum_part08_o   : bit_vector (15 downto 0);
   signal sum_part08_a   : bit_vector (15 downto 0);
   signal sum_part08     : bit_vector (15 downto 0);
 
   signal adder_stage_01 : bit_vector (09 downto 0);
   signal adder_stage_02 : bit_vector (10 downto 0);
   signal adder_stage_03 : bit_vector (11 downto 0);
   signal adder_stage_04 : bit_vector (12 downto 0);
   signal adder_stage_05 : bit_vector (13 downto 0);
   signal adder_stage_06 : bit_vector (14 downto 0);
   signal adder_stage_07 : bit_vector (15 downto 0);
   signal adder_stage_08 : bit_vector (16 downto 0);
 
   begin
 
   sum_part01_z (00) <= '0';
   sum_part01_z (01) <= '0';
   sum_part01_z (02) <= '0';
   sum_part01_z (03) <= '0';
   sum_part01_z (04) <= '0';
   sum_part01_z (05) <= '0';
   sum_part01_z (06) <= '0';
   sum_part01_z (07) <= '0';
   sum_part01_z (08) <= '0';
 
   sum_part01(00) <= signal_nco(0) and input_phase(0);
   sum_part01(01) <= signal_nco(0) and input_phase(1);
   sum_part01(02) <= signal_nco(0) and input_phase(2);
   sum_part01(03) <= signal_nco(0) and input_phase(3);
   sum_part01(04) <= signal_nco(0) and input_phase(4);
   sum_part01(05) <= signal_nco(0) and input_phase(5);
   sum_part01(06) <= signal_nco(0) and input_phase(6);
   sum_part01(07) <= signal_nco(0) and input_phase(7);
   sum_part01(08) <= signal_nco(0) and input_phase(7);
 
   sum_part02(00) <= '0';
   sum_part02(01) <= signal_nco(1) and input_phase(0);
   sum_part02(02) <= signal_nco(1) and input_phase(1);
   sum_part02(03) <= signal_nco(1) and input_phase(2);
   sum_part02(04) <= signal_nco(1) and input_phase(3);
   sum_part02(05) <= signal_nco(1) and input_phase(4);
   sum_part02(06) <= signal_nco(1) and input_phase(5);
   sum_part02(07) <= signal_nco(1) and input_phase(6);
   sum_part02(08) <= signal_nco(1) and input_phase(7);
   sum_part02(09) <= signal_nco(1) and input_phase(7);
 
   sum_part03(00) <= '0';
   sum_part03(01) <= '0';
   sum_part03(02) <= signal_nco(2) and input_phase(0);
   sum_part03(03) <= signal_nco(2) and input_phase(1);
   sum_part03(04) <= signal_nco(2) and input_phase(2);
   sum_part03(05) <= signal_nco(2) and input_phase(3);
   sum_part03(06) <= signal_nco(2) and input_phase(4);
   sum_part03(07) <= signal_nco(2) and input_phase(5);
   sum_part03(08) <= signal_nco(2) and input_phase(6);
   sum_part03(09) <= signal_nco(2) and input_phase(7);
   sum_part03(10) <= signal_nco(2) and input_phase(7);
 
   sum_part04(00) <= '0';
   sum_part04(01) <= '0';
   sum_part04(02) <= '0';
   sum_part04(03) <= signal_nco(3) and input_phase(0);
   sum_part04(04) <= signal_nco(3) and input_phase(1);
   sum_part04(05) <= signal_nco(3) and input_phase(2);
   sum_part04(06) <= signal_nco(3) and input_phase(3);
   sum_part04(07) <= signal_nco(3) and input_phase(4);
   sum_part04(08) <= signal_nco(3) and input_phase(5);
   sum_part04(09) <= signal_nco(3) and input_phase(6);
   sum_part04(10) <= signal_nco(3) and input_phase(7);
   sum_part04(11) <= signal_nco(3) and input_phase(7);
 
   sum_part05(00) <= '0';
   sum_part05(01) <= '0';
   sum_part05(02) <= '0';
   sum_part05(03) <= '0';
   sum_part05(04) <= signal_nco(4) and input_phase(0);
   sum_part05(05) <= signal_nco(4) and input_phase(1);
   sum_part05(06) <= signal_nco(4) and input_phase(2);
   sum_part05(07) <= signal_nco(4) and input_phase(3);
   sum_part05(08) <= signal_nco(4) and input_phase(4);
   sum_part05(09) <= signal_nco(4) and input_phase(5);
   sum_part05(10) <= signal_nco(4) and input_phase(6);
   sum_part05(11) <= signal_nco(4) and input_phase(7);
   sum_part05(12) <= signal_nco(4) and input_phase(7);
 
   sum_part06(00) <= '0';
   sum_part06(01) <= '0';
   sum_part06(02) <= '0';
   sum_part06(03) <= '0';
   sum_part06(04) <= '0';
   sum_part06(05) <= signal_nco(5) and input_phase(0);
   sum_part06(06) <= signal_nco(5) and input_phase(1);
   sum_part06(07) <= signal_nco(5) and input_phase(2);
   sum_part06(08) <= signal_nco(5) and input_phase(3);
   sum_part06(09) <= signal_nco(5) and input_phase(4);
   sum_part06(10) <= signal_nco(5) and input_phase(5);
   sum_part06(11) <= signal_nco(5) and input_phase(6);
   sum_part06(12) <= signal_nco(5) and input_phase(7);
   sum_part06(13) <= signal_nco(5) and input_phase(7);
 
   sum_part07(00) <= '0';
   sum_part07(01) <= '0';
   sum_part07(02) <= '0';
   sum_part07(03) <= '0';
   sum_part07(04) <= '0';
   sum_part07(05) <= '0';
   sum_part07(06) <= signal_nco(6) and input_phase(0);
   sum_part07(07) <= signal_nco(6) and input_phase(1);
   sum_part07(08) <= signal_nco(6) and input_phase(2);
   sum_part07(09) <= signal_nco(6) and input_phase(3);
   sum_part07(10) <= signal_nco(6) and input_phase(4);
   sum_part07(11) <= signal_nco(6) and input_phase(5);
   sum_part07(12) <= signal_nco(6) and input_phase(6);
   sum_part07(13) <= signal_nco(6) and input_phase(7);
   sum_part07(14) <= signal_nco(6) and input_phase(7);
 
   sum_part08(00) <= '0';
   sum_part08(01) <= '0';
   sum_part08(02) <= '0';
   sum_part08(03) <= '0';
   sum_part08(04) <= '0';
   sum_part08(05) <= '0';
   sum_part08(06) <= '0';
   sum_part08(07) <= signal_nco(7) and input_phase(0);
   sum_part08(08) <= signal_nco(7) and input_phase(1);
   sum_part08(09) <= signal_nco(7) and input_phase(2);
   sum_part08(10) <= signal_nco(7) and input_phase(3);
   sum_part08(11) <= signal_nco(7) and input_phase(4);
   sum_part08(12) <= signal_nco(7) and input_phase(5);
   sum_part08(13) <= signal_nco(7) and input_phase(6);
   sum_part08(14) <= signal_nco(7) and input_phase(7);
   sum_part08(15) <= signal_nco(7) and input_phase(7);
 
   sum_part08_t (00) <= (not (sum_part08 (00)));
   sum_part08_t (01) <= (not (sum_part08 (01)));
   sum_part08_t (02) <= (not (sum_part08 (02)));
   sum_part08_t (03) <= (not (sum_part08 (03)));
   sum_part08_t (04) <= (not (sum_part08 (04)));
   sum_part08_t (05) <= (not (sum_part08 (05)));
   sum_part08_t (06) <= (not (sum_part08 (06)));
   sum_part08_t (07) <= (not (sum_part08 (07)));
   sum_part08_t (08) <= (not (sum_part08 (08)));
   sum_part08_t (09) <= (not (sum_part08 (09)));
   sum_part08_t (10) <= (not (sum_part08 (10)));
   sum_part08_t (11) <= (not (sum_part08 (11)));
   sum_part08_t (12) <= (not (sum_part08 (12)));
   sum_part08_t (13) <= (not (sum_part08 (13)));
   sum_part08_t (14) <= (not (sum_part08 (14)));
   sum_part08_t (15) <= (not (sum_part08 (15)));
 
   sum_part08_o (00) <= '1';
   sum_part08_o (01) <= '0';
   sum_part08_o (02) <= '0';
   sum_part08_o (03) <= '0';
   sum_part08_o (04) <= '0';
   sum_part08_o (05) <= '0';
   sum_part08_o (06) <= '0';
   sum_part08_o (07) <= '0';
   sum_part08_o (08) <= '0';
   sum_part08_o (09) <= '0';
   sum_part08_o (10) <= '0';
   sum_part08_o (11) <= '0';
   sum_part08_o (12) <= '0';
   sum_part08_o (13) <= '0';
   sum_part08_o (14) <= '0';
   sum_part08_o (15) <= '0';
 
stage_01 : adder_09bit
   port map (
   addend_09bit   (08 downto 0)  => sum_part01_z,
   augend_09bit   (08 downto 0)  => sum_part01,
   adder09_output (09 downto 0)  => adder_stage_01
   );
 
stage_02 : adder_10bit
   port map (
   addend_10bit   (09 downto 0)  => adder_stage_01,
   augend_10bit   (09 downto 0)  => sum_part02,
   adder10_output (10 downto 0)  => adder_stage_02
   );
 
stage_03 : adder_11bit
   port map (
   addend_11bit   (10 downto 0)  => adder_stage_02,
   augend_11bit   (10 downto 0)  => sum_part03,
   adder11_output (11 downto 0)  => adder_stage_03
   );
 
stage_04 : adder_12bit
   port map (
   addend_12bit   (11 downto 0)  => adder_stage_03,
   augend_12bit   (11 downto 0)  => sum_part04,
   adder12_output (12 downto 0)  => adder_stage_04
   );
 
stage_05 : adder_13bit
   port map (
   addend_13bit   (12 downto 0)  => adder_stage_04,
   augend_13bit   (12 downto 0)  => sum_part05,
   adder13_output (13 downto 0)  => adder_stage_05
   );
 
stage_06 : adder_14bit
   port map (
   addend_14bit   (13 downto 0)  => adder_stage_05,
   augend_14bit   (13 downto 0)  => sum_part06,
   adder14_output (14 downto 0)  => adder_stage_06
   );
 
stage_07 : adder_15bit
   port map (
   addend_15bit   (14 downto 0)  => adder_stage_06,
   augend_15bit   (14 downto 0)  => sum_part07,
   adder15_output (15 downto 0)  => adder_stage_07
   );
 
stage_08_a : adder_16bit_u
   port map (
   addend_16bit   (15 downto 0)  => sum_part08_t,
   augend_16bit   (15 downto 0)  => sum_part08_o,
   adder16_output (15 downto 0)  => sum_part08_a
   );
 
stage_08 : adder_16bit
   port map (
   addend_16bit   (15 downto 0)  => adder_stage_07,
   augend_16bit   (15 downto 0)  => sum_part08_a,
   adder16_output (16 downto 0)  => adder_stage_08
   );
 
   input_phase <= mult_01;
   signal_nco  <= mult_02;
   result_mult <= adder_stage_08(15 downto 0);
 
end structural;

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Subversion Repositories simple_fm_receiver

[/] [simple_fm_receiver/] [tags/] [VSFR_1/] [source/] [mult_8bit.vhdl] - Blame information for rev 32

Line No.	Rev	Author	Line
1	2	arif_endro	`-- $Id: mult_8bit.vhdl,v 1.1.1.1 2005-01-04 02:05:58 arif_endro Exp $`
2			`-------------------------------------------------------------------------------`
3			`-- Title : Eight bit multiplier`
4			`-- Project : FM Receiver`
5			`-------------------------------------------------------------------------------`
6			`-- File : mult_8bit.vhdl`
7			`-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>`
8			`-- Created : 2004/12/20`
9			`-- Last update :`
10			`-- Simulators : Modelsim 6.0`
11			`-- Synthesizers:`
12			`-- Target :`
13			`-------------------------------------------------------------------------------`
14			`-- Description : Multiplier used in phase detector`
15			`-------------------------------------------------------------------------------`
16			`-- Copyright (c) 2004 Arif E. Nugroho`
17			`-- This VHDL design file is an open design; you can redistribute it and/or`
18			`-- modify it and/or implement it after contacting the author`
19			`-------------------------------------------------------------------------------`
20
21			`library IEEE;`
22			`use IEEE.STD_LOGIC_1164.ALL;`
23			`use IEEE.STD_LOGIC_arith.ALL;`
24
25			`entity mult_8bit is`
26			`port (`
27			`mult_01 : in bit_vector (07 downto 0);`
28			`mult_02 : in bit_vector (07 downto 0);`
29			`result_mult : out bit_vector (15 downto 0)`
30			`);`
31			`end mult_8bit;`
32
33			`architecture structural of mult_8bit is`
34			`component adder_16bit`
35			`port (`
36			`addend_16bit : in bit_vector (15 downto 0);`
37			`augend_16bit : in bit_vector (15 downto 0);`
38			`adder16_output : out bit_vector (16 downto 0)`
39			`);`
40			`end component;`
41
42			`component adder_16bit_u`
43			`port (`
44			`addend_16bit : in bit_vector (15 downto 0);`
45			`augend_16bit : in bit_vector (15 downto 0);`
46			`adder16_output : out bit_vector (15 downto 0)`
47			`);`
48			`end component;`
49
50			`component adder_15bit`
51			`port (`
52			`addend_15bit : in bit_vector (14 downto 0);`
53			`augend_15bit : in bit_vector (14 downto 0);`
54			`adder15_output : out bit_vector (15 downto 0)`
55			`);`
56			`end component;`
57
58			`component adder_14bit`
59			`port (`
60			`addend_14bit : in bit_vector (13 downto 0);`
61			`augend_14bit : in bit_vector (13 downto 0);`
62			`adder14_output : out bit_vector (14 downto 0)`
63			`);`
64			`end component;`
65
66			`component adder_13bit`
67			`port (`
68			`addend_13bit : in bit_vector (12 downto 0);`
69			`augend_13bit : in bit_vector (12 downto 0);`
70			`adder13_output : out bit_vector (13 downto 0)`
71			`);`
72			`end component;`
73
74			`component adder_12bit`
75			`port (`
76			`addend_12bit : in bit_vector (11 downto 0);`
77			`augend_12bit : in bit_vector (11 downto 0);`
78			`adder12_output : out bit_vector (12 downto 0)`
79			`);`
80			`end component;`
81
82			`component adder_11bit`
83			`port (`
84			`addend_11bit : in bit_vector (10 downto 0);`
85			`augend_11bit : in bit_vector (10 downto 0);`
86			`adder11_output : out bit_vector (11 downto 0)`
87			`);`
88			`end component;`
89
90			`component adder_10bit`
91			`port (`
92			`addend_10bit : in bit_vector (09 downto 0);`
93			`augend_10bit : in bit_vector (09 downto 0);`
94			`adder10_output : out bit_vector (10 downto 0)`
95			`);`
96			`end component;`
97
98			`component adder_09bit`
99			`port (`
100			`addend_09bit : in bit_vector (08 downto 0);`
101			`augend_09bit : in bit_vector (08 downto 0);`
102			`adder09_output : out bit_vector (09 downto 0)`
103			`);`
104			`end component;`
105
106			`signal input_phase : bit_vector (07 downto 0);`
107			`signal signal_nco : bit_vector (07 downto 0);`
108
109			`signal sum_part01 : bit_vector (08 downto 0);`
110			`signal sum_part01_z : bit_vector (08 downto 0);`
111			`signal sum_part02 : bit_vector (09 downto 0);`
112			`signal sum_part03 : bit_vector (10 downto 0);`
113			`signal sum_part04 : bit_vector (11 downto 0);`
114			`signal sum_part05 : bit_vector (12 downto 0);`
115			`signal sum_part06 : bit_vector (13 downto 0);`
116			`signal sum_part07 : bit_vector (14 downto 0);`
117			`signal sum_part08_t : bit_vector (15 downto 0);`
118			`signal sum_part08_o : bit_vector (15 downto 0);`
119			`signal sum_part08_a : bit_vector (15 downto 0);`
120			`signal sum_part08 : bit_vector (15 downto 0);`
121
122			`signal adder_stage_01 : bit_vector (09 downto 0);`
123			`signal adder_stage_02 : bit_vector (10 downto 0);`
124			`signal adder_stage_03 : bit_vector (11 downto 0);`
125			`signal adder_stage_04 : bit_vector (12 downto 0);`
126			`signal adder_stage_05 : bit_vector (13 downto 0);`
127			`signal adder_stage_06 : bit_vector (14 downto 0);`
128			`signal adder_stage_07 : bit_vector (15 downto 0);`
129			`signal adder_stage_08 : bit_vector (16 downto 0);`
130
131			`begin`
132
133			`sum_part01_z (00) <= '0';`
134			`sum_part01_z (01) <= '0';`
135			`sum_part01_z (02) <= '0';`
136			`sum_part01_z (03) <= '0';`
137			`sum_part01_z (04) <= '0';`
138			`sum_part01_z (05) <= '0';`
139			`sum_part01_z (06) <= '0';`
140			`sum_part01_z (07) <= '0';`
141			`sum_part01_z (08) <= '0';`
142
143			`sum_part01(00) <= signal_nco(0) and input_phase(0);`
144			`sum_part01(01) <= signal_nco(0) and input_phase(1);`
145			`sum_part01(02) <= signal_nco(0) and input_phase(2);`
146			`sum_part01(03) <= signal_nco(0) and input_phase(3);`
147			`sum_part01(04) <= signal_nco(0) and input_phase(4);`
148			`sum_part01(05) <= signal_nco(0) and input_phase(5);`
149			`sum_part01(06) <= signal_nco(0) and input_phase(6);`
150			`sum_part01(07) <= signal_nco(0) and input_phase(7);`
151			`sum_part01(08) <= signal_nco(0) and input_phase(7);`
152
153			`sum_part02(00) <= '0';`
154			`sum_part02(01) <= signal_nco(1) and input_phase(0);`
155			`sum_part02(02) <= signal_nco(1) and input_phase(1);`
156			`sum_part02(03) <= signal_nco(1) and input_phase(2);`
157			`sum_part02(04) <= signal_nco(1) and input_phase(3);`
158			`sum_part02(05) <= signal_nco(1) and input_phase(4);`
159			`sum_part02(06) <= signal_nco(1) and input_phase(5);`
160			`sum_part02(07) <= signal_nco(1) and input_phase(6);`
161			`sum_part02(08) <= signal_nco(1) and input_phase(7);`
162			`sum_part02(09) <= signal_nco(1) and input_phase(7);`
163
164			`sum_part03(00) <= '0';`
165			`sum_part03(01) <= '0';`
166			`sum_part03(02) <= signal_nco(2) and input_phase(0);`
167			`sum_part03(03) <= signal_nco(2) and input_phase(1);`
168			`sum_part03(04) <= signal_nco(2) and input_phase(2);`
169			`sum_part03(05) <= signal_nco(2) and input_phase(3);`
170			`sum_part03(06) <= signal_nco(2) and input_phase(4);`
171			`sum_part03(07) <= signal_nco(2) and input_phase(5);`
172			`sum_part03(08) <= signal_nco(2) and input_phase(6);`
173			`sum_part03(09) <= signal_nco(2) and input_phase(7);`
174			`sum_part03(10) <= signal_nco(2) and input_phase(7);`
175
176			`sum_part04(00) <= '0';`
177			`sum_part04(01) <= '0';`
178			`sum_part04(02) <= '0';`
179			`sum_part04(03) <= signal_nco(3) and input_phase(0);`
180			`sum_part04(04) <= signal_nco(3) and input_phase(1);`
181			`sum_part04(05) <= signal_nco(3) and input_phase(2);`
182			`sum_part04(06) <= signal_nco(3) and input_phase(3);`
183			`sum_part04(07) <= signal_nco(3) and input_phase(4);`
184			`sum_part04(08) <= signal_nco(3) and input_phase(5);`
185			`sum_part04(09) <= signal_nco(3) and input_phase(6);`
186			`sum_part04(10) <= signal_nco(3) and input_phase(7);`
187			`sum_part04(11) <= signal_nco(3) and input_phase(7);`
188
189			`sum_part05(00) <= '0';`
190			`sum_part05(01) <= '0';`
191			`sum_part05(02) <= '0';`
192			`sum_part05(03) <= '0';`
193			`sum_part05(04) <= signal_nco(4) and input_phase(0);`
194			`sum_part05(05) <= signal_nco(4) and input_phase(1);`
195			`sum_part05(06) <= signal_nco(4) and input_phase(2);`
196			`sum_part05(07) <= signal_nco(4) and input_phase(3);`
197			`sum_part05(08) <= signal_nco(4) and input_phase(4);`
198			`sum_part05(09) <= signal_nco(4) and input_phase(5);`
199			`sum_part05(10) <= signal_nco(4) and input_phase(6);`
200			`sum_part05(11) <= signal_nco(4) and input_phase(7);`
201			`sum_part05(12) <= signal_nco(4) and input_phase(7);`
202
203			`sum_part06(00) <= '0';`
204			`sum_part06(01) <= '0';`
205			`sum_part06(02) <= '0';`
206			`sum_part06(03) <= '0';`
207			`sum_part06(04) <= '0';`
208			`sum_part06(05) <= signal_nco(5) and input_phase(0);`
209			`sum_part06(06) <= signal_nco(5) and input_phase(1);`
210			`sum_part06(07) <= signal_nco(5) and input_phase(2);`
211			`sum_part06(08) <= signal_nco(5) and input_phase(3);`
212			`sum_part06(09) <= signal_nco(5) and input_phase(4);`
213			`sum_part06(10) <= signal_nco(5) and input_phase(5);`
214			`sum_part06(11) <= signal_nco(5) and input_phase(6);`
215			`sum_part06(12) <= signal_nco(5) and input_phase(7);`
216			`sum_part06(13) <= signal_nco(5) and input_phase(7);`
217
218			`sum_part07(00) <= '0';`
219			`sum_part07(01) <= '0';`
220			`sum_part07(02) <= '0';`
221			`sum_part07(03) <= '0';`
222			`sum_part07(04) <= '0';`
223			`sum_part07(05) <= '0';`
224			`sum_part07(06) <= signal_nco(6) and input_phase(0);`
225			`sum_part07(07) <= signal_nco(6) and input_phase(1);`
226			`sum_part07(08) <= signal_nco(6) and input_phase(2);`
227			`sum_part07(09) <= signal_nco(6) and input_phase(3);`
228			`sum_part07(10) <= signal_nco(6) and input_phase(4);`
229			`sum_part07(11) <= signal_nco(6) and input_phase(5);`
230			`sum_part07(12) <= signal_nco(6) and input_phase(6);`
231			`sum_part07(13) <= signal_nco(6) and input_phase(7);`
232			`sum_part07(14) <= signal_nco(6) and input_phase(7);`
233
234			`sum_part08(00) <= '0';`
235			`sum_part08(01) <= '0';`
236			`sum_part08(02) <= '0';`
237			`sum_part08(03) <= '0';`
238			`sum_part08(04) <= '0';`
239			`sum_part08(05) <= '0';`
240			`sum_part08(06) <= '0';`
241			`sum_part08(07) <= signal_nco(7) and input_phase(0);`
242			`sum_part08(08) <= signal_nco(7) and input_phase(1);`
243			`sum_part08(09) <= signal_nco(7) and input_phase(2);`
244			`sum_part08(10) <= signal_nco(7) and input_phase(3);`
245			`sum_part08(11) <= signal_nco(7) and input_phase(4);`
246			`sum_part08(12) <= signal_nco(7) and input_phase(5);`
247			`sum_part08(13) <= signal_nco(7) and input_phase(6);`
248			`sum_part08(14) <= signal_nco(7) and input_phase(7);`
249			`sum_part08(15) <= signal_nco(7) and input_phase(7);`
250
251			`sum_part08_t (00) <= (not (sum_part08 (00)));`
252			`sum_part08_t (01) <= (not (sum_part08 (01)));`
253			`sum_part08_t (02) <= (not (sum_part08 (02)));`
254			`sum_part08_t (03) <= (not (sum_part08 (03)));`
255			`sum_part08_t (04) <= (not (sum_part08 (04)));`
256			`sum_part08_t (05) <= (not (sum_part08 (05)));`
257			`sum_part08_t (06) <= (not (sum_part08 (06)));`
258			`sum_part08_t (07) <= (not (sum_part08 (07)));`
259			`sum_part08_t (08) <= (not (sum_part08 (08)));`
260			`sum_part08_t (09) <= (not (sum_part08 (09)));`
261			`sum_part08_t (10) <= (not (sum_part08 (10)));`
262			`sum_part08_t (11) <= (not (sum_part08 (11)));`
263			`sum_part08_t (12) <= (not (sum_part08 (12)));`
264			`sum_part08_t (13) <= (not (sum_part08 (13)));`
265			`sum_part08_t (14) <= (not (sum_part08 (14)));`
266			`sum_part08_t (15) <= (not (sum_part08 (15)));`
267
268			`sum_part08_o (00) <= '1';`
269			`sum_part08_o (01) <= '0';`
270			`sum_part08_o (02) <= '0';`
271			`sum_part08_o (03) <= '0';`
272			`sum_part08_o (04) <= '0';`
273			`sum_part08_o (05) <= '0';`
274			`sum_part08_o (06) <= '0';`
275			`sum_part08_o (07) <= '0';`
276			`sum_part08_o (08) <= '0';`
277			`sum_part08_o (09) <= '0';`
278			`sum_part08_o (10) <= '0';`
279			`sum_part08_o (11) <= '0';`
280			`sum_part08_o (12) <= '0';`
281			`sum_part08_o (13) <= '0';`
282			`sum_part08_o (14) <= '0';`
283			`sum_part08_o (15) <= '0';`
284
285			`stage_01 : adder_09bit`
286			`port map (`
287			`addend_09bit (08 downto 0) => sum_part01_z,`
288			`augend_09bit (08 downto 0) => sum_part01,`
289			`adder09_output (09 downto 0) => adder_stage_01`
290			`);`
291
292			`stage_02 : adder_10bit`
293			`port map (`
294			`addend_10bit (09 downto 0) => adder_stage_01,`
295			`augend_10bit (09 downto 0) => sum_part02,`
296			`adder10_output (10 downto 0) => adder_stage_02`
297			`);`
298
299			`stage_03 : adder_11bit`
300			`port map (`
301			`addend_11bit (10 downto 0) => adder_stage_02,`
302			`augend_11bit (10 downto 0) => sum_part03,`
303			`adder11_output (11 downto 0) => adder_stage_03`
304			`);`
305
306			`stage_04 : adder_12bit`
307			`port map (`
308			`addend_12bit (11 downto 0) => adder_stage_03,`
309			`augend_12bit (11 downto 0) => sum_part04,`
310			`adder12_output (12 downto 0) => adder_stage_04`
311			`);`
312
313			`stage_05 : adder_13bit`
314			`port map (`
315			`addend_13bit (12 downto 0) => adder_stage_04,`
316			`augend_13bit (12 downto 0) => sum_part05,`
317			`adder13_output (13 downto 0) => adder_stage_05`
318			`);`
319
320			`stage_06 : adder_14bit`
321			`port map (`
322			`addend_14bit (13 downto 0) => adder_stage_05,`
323			`augend_14bit (13 downto 0) => sum_part06,`
324			`adder14_output (14 downto 0) => adder_stage_06`
325			`);`
326
327			`stage_07 : adder_15bit`
328			`port map (`
329			`addend_15bit (14 downto 0) => adder_stage_06,`
330			`augend_15bit (14 downto 0) => sum_part07,`
331			`adder15_output (15 downto 0) => adder_stage_07`
332			`);`
333
334			`stage_08_a : adder_16bit_u`
335			`port map (`
336			`addend_16bit (15 downto 0) => sum_part08_t,`
337			`augend_16bit (15 downto 0) => sum_part08_o,`
338			`adder16_output (15 downto 0) => sum_part08_a`
339			`);`
340
341			`stage_08 : adder_16bit`
342			`port map (`
343			`addend_16bit (15 downto 0) => adder_stage_07,`
344			`augend_16bit (15 downto 0) => sum_part08_a,`
345			`adder16_output (16 downto 0) => adder_stage_08`
346			`);`
347
348			`input_phase <= mult_01;`
349			`signal_nco <= mult_02;`
350			`result_mult <= adder_stage_08(15 downto 0);`
351
352			`end structural;`