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-- ------------------------------------------------------------------------
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arif_endro |
-- Copyright (C) 2004 Arif Endro Nugroho
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arif_endro |
-- All rights reserved.
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arif_endro |
--
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arif_endro |
-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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arif_endro |
--
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arif_endro |
-- 1. Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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arif_endro |
--
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-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
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-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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arif_endro |
--
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arif_endro |
-- End Of License.
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-- ------------------------------------------------------------------------
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arif_endro |
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-------------------------------------------------------------------------------
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-- Notes on Implementations
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-- Generates ILA, ICON, and VIO cores using Xilinx ChipScope with
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-- following options:
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-- ICON => generates to control two devices (e.g. two control port)
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-- ILA => generates to capture two output signal (e.g. two trigger)
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-- VIO => generates one async control output to control reset signal on design
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity xilinx_fpga is
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port (
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clock : in bit
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);
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end xilinx_fpga;
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architecture structural of xilinx_fpga is
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-------------------------------------------------------------------
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--
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-- Design Under Test
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--
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-------------------------------------------------------------------
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component bench
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port (
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clock : in bit;
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reset : in bit;
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output_fm : out bit_vector (11 downto 0);
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output_fmTri : out bit_vector (11 downto 0)
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);
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end component;
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-------------------------------------------------------------------
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--
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-- DUT Signal declaration
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--
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-------------------------------------------------------------------
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signal reset : bit;
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signal output_fm : bit_vector (11 downto 0);
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signal output_fmTri : bit_vector (11 downto 0);
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-------------------------------------------------------------------
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--
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-- ICON core component declaration
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--
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-------------------------------------------------------------------
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component icon
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port
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(
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control0 : out std_logic_vector(35 downto 0);
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control1 : out std_logic_vector(35 downto 0)
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);
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end component;
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-------------------------------------------------------------------
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--
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-- ICON core signal declarations
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--
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-------------------------------------------------------------------
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signal control0 : std_logic_vector(35 downto 0);
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signal control1 : std_logic_vector(35 downto 0);
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-------------------------------------------------------------------
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--
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-- ILA core component declaration
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--
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-------------------------------------------------------------------
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component ila
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port
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(
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control : in std_logic_vector(35 downto 0);
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clk : in std_logic;
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trig0 : in std_logic_vector(11 downto 0);
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trig1 : in std_logic_vector(11 downto 0)
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);
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end component;
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-------------------------------------------------------------------
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--
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-- ILA core signal declarations
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--
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-------------------------------------------------------------------
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-- signal control : std_logic_vector(35 downto 0);
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signal clk : std_logic;
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signal trig0 : std_logic_vector(11 downto 0);
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signal trig1 : std_logic_vector(11 downto 0);
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-------------------------------------------------------------------
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--
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-- VIO core component declaration
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--
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-------------------------------------------------------------------
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component vio
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port
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(
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control : in std_logic_vector(35 downto 0);
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async_out : out std_logic_vector(0 downto 0)
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);
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end component;
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-------------------------------------------------------------------
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--
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-- VIO core signal declarations
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--
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-------------------------------------------------------------------
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-- signal control : std_logic_vector(35 downto 0);
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signal async_out : std_logic_vector(0 downto 0);
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begin
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-------------------------------------------------------------------
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-- Design Under Test
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-- Design + Test bench to make easy input date (lazy person)
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-------------------------------------------------------------------
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my_design : bench
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port map
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(
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clock => clock,
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reset => reset,
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output_fm => output_fm,
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output_fmTri => output_fmTri
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);
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-------------------------------------------------------------------
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--
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-- ICON core instance
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--
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-------------------------------------------------------------------
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i_icon : icon
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port map
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(
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control0 => control0,
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control1 => control1
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);
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-------------------------------------------------------------------
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--
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-- ILA core instance
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--
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-------------------------------------------------------------------
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i_ila : ila
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port map
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(
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control => control0,
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clk => clk,
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trig0 => trig0,
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trig1 => trig1
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);
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clk <= to_stdulogic (clock);
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trig0 <= to_stdlogicvector (output_fm);
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trig1 <= to_stdlogicvector (output_fmTri);
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-------------------------------------------------------------------
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--
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-- VIO core instance
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--
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-------------------------------------------------------------------
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i_vio : vio
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port map
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(
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control => control1,
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async_out => async_out
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);
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reset <= to_bit (async_out(0));
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end structural;
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