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[/] [simple_fm_receiver/] [trunk/] [modelsim-bench/] [bench.vhdl] - Blame information for rev 47

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1 46 arif_endro
-- ------------------------------------------------------------------------
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-- Copyright (C) 2004 Arif Endro Nugroho
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-- All rights reserved.
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-- 
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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-- 
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-- 1. Redistributions of source code must retain the above copyright
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--    notice, this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above copyright
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--    notice, this list of conditions and the following disclaimer in the
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--    documentation and/or other materials provided with the distribution.
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-- 
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-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
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-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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-- 
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-- End Of License.
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-- ------------------------------------------------------------------------
29 2 arif_endro
 
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_arith.ALL;
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use IEEE.STD_LOGIC_unsigned.ALL;
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entity bench is
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--  port (
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--   clock : out bit;
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--   fmout : out bit;
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--   reset : out bit;
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-- );
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end bench;
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architecture structural of bench is
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  component fm
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  port (
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    CLK              : in  bit;
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    RESET            : in  bit;
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    FMIN             : in  bit_vector (07 downto 0);
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    DMOUT            : out bit_vector (11 downto 0)
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    );
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  end component;
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  component input
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  port (
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    clock_out        : out bit;
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    test_signal_fm   : out bit_vector (07 downto 0);
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    test_signal_fmTri: out bit_vector (07 downto 0);
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    signal_fm_bit    : out bit;
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    signal_fmTri_bit : out bit
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    );
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  end component;
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  signal clock       : bit;
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  signal reset       : bit;
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  signal signal_fm   : bit;
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  signal signal_fmTri: bit;
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  signal test_signal_fm : bit_vector (07 downto 0);
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  signal test_signal_fmTri : bit_vector (07 downto 0);
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  signal output_fm   : bit_vector (11 downto 0);
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  begin
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  reset <= '0';
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  myinput : input
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   port map (
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    clock_out        => clock,
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    test_signal_fm   => test_signal_fm,
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    test_signal_fmTri=> test_signal_fmTri,
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    signal_fm_bit    => signal_fm,
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    signal_fmTri_bit => signal_fmTri
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    );
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  myfm : fm
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   port map (
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    CLK                  => clock,
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    RESET                => reset,
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    FMIN                 => test_signal_fm,
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    DMOUT (11 downto 0)  => output_fm
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    );
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end structural;

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