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arif_endro |
-- ------------------------------------------------------------------------
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-- Copyright (C) 2004 Arif Endro Nugroho
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- 1. Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
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-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- End Of License.
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-- ------------------------------------------------------------------------
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arif_endro |
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_arith.ALL;
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use IEEE.STD_LOGIC_unsigned.ALL;
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library IEEE;
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library STD;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_arith.ALL;
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use IEEE.STD_LOGIC_unsigned.ALL;
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use STD.TEXTIO.ALL;
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entity chip_view is
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port (
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clock_out : out bit;
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DMOUT_FM : out bit_vector (11 downto 0);
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DMOUT_FMTRI : out bit_vector (11 downto 0);
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DMOUT_FM_BIT : out bit;
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DMOUT_FMTRI_BIT : out bit
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);
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end chip_view;
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architecture viewer of chip_view is
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type char_to_stdlogic_t is array (character) of std_logic;
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file file_pointer_fm : text open read_mode is "fm_square_fpga.txt";
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file file_pointer_fmTri : text open read_mode is "fm_triangular_fpga.txt";
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constant to_std_logic : char_to_stdlogic_t := (
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'U' => 'U',
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'X' => 'X',
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'0' => '0',
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'1' => '1',
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'Z' => 'Z',
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'W' => 'W',
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'L' => 'L',
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'H' => 'H',
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'-' => '-',
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others => 'X'
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);
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signal signal_fm_bit : std_logic;
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signal signal_fmTri_bit : std_logic;
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signal clock : std_logic;
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begin
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process
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variable line_input_fm : line;
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variable line_input_fmTri : line;
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variable vector_fm : string(1 to 12) := " ";
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variable vector_fmTri : string(1 to 12) := " ";
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variable input_length_fm : integer;
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variable input_length_fmTri : integer;
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variable delay_time : time := 1 ns;
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variable var_fm : std_logic_vector (11 downto 0);
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variable var_fmTri : std_logic_vector (11 downto 0);
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begin
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while not (endfile(file_pointer_fm) and endfile(file_pointer_fmTri)) loop
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readline(file_pointer_fm, line_input_fm);
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readline(file_pointer_fmTri, line_input_fmTri);
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if (line_input_fm /= NULL) and (line_input_fm'length > 0) and (line_input_fmTri /= NULL) and (line_input_fmTri'length > 0) then
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read(line_input_fm, vector_fm);
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read(line_input_fmTri, vector_fmTri);
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input_length_fm := vector_fm'length - 1;
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input_length_fmTri := vector_fmTri'length - 1;
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for a in vector_fm'range loop
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var_fm(input_length_fm) := to_std_logic(vector_fm(a));
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signal_fm_bit <= to_std_logic(vector_fm(a));
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input_length_fm := input_length_fm - 1;
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end loop;
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for a in vector_fmTri'range loop
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var_fmTri(input_length_fmTri) := to_std_logic(vector_fmTri(a));
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signal_fmTri_bit <= to_std_logic(vector_fmTri(a));
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input_length_fmTri := input_length_fmTri - 1;
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end loop;
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DMOUT_FM <= to_bitvector(var_fm);
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DMOUT_FMTRI <= to_bitvector(var_fmTri);
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clock <= '1';
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wait for delay_time;
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clock <= '0';
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wait for delay_time;
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end if;
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end loop;
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wait;
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end process;
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DMOUT_FM_BIT <= to_bit(signal_fm_bit);
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DMOUT_FMTRI_BIT <= to_bit(signal_fmTri_bit);
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clock_out <= to_bit(clock);
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end viewer;
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